TS8388BCFB/Q - E2V Technologies (UK), Ltd.

Features

•8-bit Resolution

•ADC Gain Adjust

•1.5 GHz Full Power Input Bandwidth (-3 dB)

•1 GSPS (min) Sampling Rate

•SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,

at FS = 1 GSPS, FIN = 20 MHz

•SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,

at FS = 1 GSPS, FIN = 500 MHz

•SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,

at FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS)

•2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS

•DNL = 0.3 lsb, INL = 0.7 lsb

•Low Bit Error Rate (10-13) at 1 GSPS

•Very Low Input Capacitan ce: 3 pF

•500 mVpp Differential or Single-ended Analog Inputs

•Differ enti al or Single-ended 50Ω ECL Compatible Clock Inputs

•ECL or LVDS/HSTL Output Compatibility

•Data Ready Output with Asynchronous Reset

•Gray or Binary Selectable Output Data; NRZ Output Mode

•Power Consumption: 3.4W at Tj = 70°C Typical

•Radiation Tolerance Oriented Design (150 Krad (Si) measured)

•Two Package Versions

•ESA/SCC Detailed Specification Available on Request

•Enhanced CQFP68 Packaged Device: TS8388BFS

•Evaluation board: TSEV8388BF

•Demultiplexer: TS81102G0: Companion Device Available

Applications

• Digital Sampling Oscilloscopes

• Satellite Receiver

• Electronic Countermeasures/Electronic Warfare

• Direct RF Down-conversion

Screening

• Atmel Standard Screening Level

• Mil-PRF-38535, QML Level Q for Package Version, DSCC 5962-0050401QYC

• Temperature Range: up to -55°C < Tc; Tj < +125°C

Description

The TS83 88B F i s a mo nol it hic 8 -bit ana log-to- dig ita l c on ve rter , de si gne d for di git iz ing

wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.

The TS8388BF uses an innovative architecture,

including an on-chip Sample and Hold (S/H),

and is fabricated with an advanced

high speed bipolar process.

The on-chip S/H has a 1.5 GHz full power

input bandwidth, providing excellent dynamic

performance in undersampling applications

(High IF digitizing).

ADC 8-bit

1 GSPS

TS8388BF

Rev. 2144A–BDC–04/02

F Suffix: CQFP 68

Ceramic Quad Flat Pack

2TS8388BF 2144A–BDC–04/02

Functional

Description

Block Diagram The following figure shows the simplified block diagram.

Figure 1. Simplified Block Diagram

Functional

Description The TS8388BF is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology

featuring a cutoff frequency of 25 GHz.

The TS838 8BF includes a front- end ma ster/ slave Tr ack a nd Hold stage (S /H), follo wed b y an

analog encoding stage and interpolation circuitry.

Succes sive ban ks of latc hes r egenerate the ana log re sidues in to lo gical data before en terin g

an error correction circuitry and a resynchronization stage followed by 75Ω differential output

buffers.

The TS8388BF works in fully differential mode from analog inputs up to digital outputs.

The TS8388BF features a full-power input bandwidth of 1.5 GHz.

A control pin GORB is provided to select either Gray or Binary data output format.

A gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynchronous reset (DRRB) is available on TS8388BF.

The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysil-

icon resisto rs, which allow enhanced rad iation tolerance (no perfor mance drift measured at

150 kRad total dose).

MASTER/SLAVE TRACK & HOLD AMPLIFIER

VIN, VINB

CLOCK

BUFFER

GAIN

GORB DATA, DATAB OR, ORB

DRRB DR, DRB

CLK, CLKB

G=2 T/H G=1 T/H G=1 RESISTOR

CHAIN ANALOG

ENCODING

BLOCK

INTERPOLATION

STAGES

REGENERATION

LATCHES

ERROR CORRECTION &

DECODE LOGIC

OUTPUT LATCHES &

BUFFERS

TS8388BF

2144A–BDC–04/02

Specifications

Absolute

Maximum Ratings

Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are

within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat

sink is manda tory. See “The board set c omes fully a ssemble d and te sted, w ith th e TS8388 BF in CQFP6 8 pack age in stalle d.” o n

page 37.

Recommended

Operating

Conditions

Table 1. Absolute Maximum Ratings

Parameter Symbol Comments Value Unit

Positive supply voltage VCC GND to 6 V

Digital negative supply voltage DVEE GND to -5.7 V

Digital positive s upply voltage VPLUSD GND -0.3 to 2.8 V

Negative supply voltage VEE GND to -6 V

Maximum difference between negative supply voltage DVEE to VEE 0.3 V

Analog input voltages VIN or VINB -1 to +1 V

Maximum difference between VIN and VINB VIN - VINB -2 to +2 V

Digital input voltage VDGORB -0.3 to VCC +0.3 V

Digital input voltage VDDRRB VEE -0.3 to +0.9 V

Digital output voltage VOVPLUSD -3 to VPLUSD -0.5 V

Clock input voltage VCLK or VCLKB -3 to +1.5 V

Maximum difference between VCLK and VCLKB VCLK - VCLKB -2 to +2 V

Maximum jun ction tempera ture Tj+135 °C

Storage temperature Tstg -65 to +150 °C

Lead temperature (soldering 10s) Tleads +300 °C

Table 2. Recommended Operating Conditions

Parameter Symbol Comments

Recommended Value

UnitMin Typ Max

Positive supply voltage VCC 4.5 +5 5.25 V

Positive digital supply voltage VPLUSD ECL output compatibility – GND – V

Positive digital supply voltage VPLUSD LVDS output compatibility +1.4 +2.4 +2.6 V

Negative supply voltage VEE, DVEE -5.25 -5 -4.75 V

4TS8388BF 2144A–BDC–04/02

Electrical

Operating

Characteristics

VEE = DVEE = -5V; VCC = +5V; VIN -VINB = 500 mVpp Full Scale differential input;

Digital outputs 75 or 50Ω differentially terminated;

Tj (typical) = 70°C. Full Temperature Range: up to -55°C < Tc; Tj < +125°C.

Differential analog input voltage

(Full Scale ) VIN, VINB

VIN - VINB

50Ω different ial or single-e nded ±113

450 ±125

500 ±137

550 mV

mVpp

Clock input power level PCLK, PCLKB 50Ω single-ended clock input 3 4 10 dBm

Operating temperature range TJCommerci al grade: “C”

Industrial grade: “V ”

Military grade: “M”

0 < Tc; Tj < 90

-40 < Tc; Tj < 110

-55 < Tc; Tj < +125

°C

Table 2. Recommended Operating Conditions (Continued)

Parameter Symbol Comments

Recommended Value

UnitMin Typ Max

Table 3. Electrical Specifications

Parameter Symbol Test

Level

Value

Unit NoteMin Typ Max

Power Requireme nts

Positive supply voltage Analog

Digital (ECL)

Digital (LVDS)

VCC

VPLUSD

1, 2, 6

4.7

–

1.4

2.4

5.3

–

2.6

Positive supply current Analog

Digital

ICC

IPLUSD

1, 2

–

385

395

115

120

445

145

Negative supply voltage VEE 1, 2, 6 -5.3 -5 -4.7 V

Negative supply current Analog

Digital

AIEE

DIEE

1, 2

–

165

170

135

145

200

180

Nominal p ower dissipation PD 1, 2

6–

–3.4

3.6 4.1

4.3 W

Power supply rejection ratio PSRR 4 – 0.5 2 mW

Resolution –––8–bits

(2)

TS8388BF

2144A–BDC–04/02

Analog Inputs

Full Scale Input Voltage range (differential mode)

(0V common mode voltage) VIN

VINB

–-125

-125 –

–125

125 mV

Full Scal e Input Voltag e range (single -ended inp ut

option) (See Application Notes) VIN

VINB

–-250

––

0250

–mV

Analog input capacitance CIN 4– 33.5pF

Input bias current IIN 4 – 10 20 µA

Input Resistance RIN 40.5 1 – MΩ

Full Power input Bandwidth FPBW 4 1.3 1.5 – GHz

Small signal input Bandwidth (10% full scale) SSBW 4 1.5 1.7 – GHz

Clock Inputs

Logic compatibility for clock inputs

(See Application Notes) ––

ECL or specifi ed clock input

power level in dBm –(10)

ECL Clock inp uts voltages (VCLK or VCLKB): – 4 – – – –

Logic “0” voltage VIL –– –-1.5V

Logic “1” voltage VIH –-1.1 – – V

Logic “0” current IIL –– 550µA

Logic “1” current IIH –– 550µA

Clock input power level into 50Ω termination – – dBm into 50Ω–

Clock input power level – 4 -2 4 10 dBm

Clock input capacitance CCLK 4– 33.5pF

Digital Outputs

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,

Tj (typical) = 70°C.

(1)(6)

Logic compatibility for digital outputs

(Depending on the value of VPLUSD)

(See Application Notes) – – ECL or LVDS –

Differential output voltage swings

(assuming VPLUSD = 0V): –4––––

75Ω open transmission lines (ECL levels) – – 1.5 1.620 – V

75Ω differentially termi nat ed – – 0.70 0.825 – V

50Ω differentially termi nat ed – – 0.54 0.660 – V

Output levels (assuming VPLUSD = 0V)

75Ω open transmission lines: –4––––

(6)

Logic “0” voltage VOL ––-1.62-1.54V

Logic “1” voltage VOH – -0.88 -0.8 – V

Table 3. Electrical Specifications (Continued)

Parameter Symbol Test

Level

Value

Unit NoteMin Typ Max

6TS8388BF 2144A–BDC–04/02
Output levels (assuming VPLUSD = 0V)
75Ω differentially  termi nat ed: –4––––
(6)
Logic “0” voltage VOL ––-1.41-1.34V
Logic “1” voltage VOH – -1.07 -1 – V
Output levels (assuming VPLUSD = 0V)
50Ω differentially  termi nat ed: ––––––
(6)
Logic “0” voltage VOL 1, 2
6–
–-1.40
-1.40 -1.32
-1.25 V
V
Logic “1” voltage VOH 1, 2
6-1.16
-1.25 -1.10
-1.10 –
–V
V
Differential Output Swing DOS 4 270 300 – mV
Output level drift with temperature – 4 – – 1.6 mV/°C
DC Accuracy
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70°C.
Differential non linearity DNL- 1, 2
6-0.5
-0.6 -0.25
-0.35 –
–lsb
lsb (2)(3)
Differential non linearity DNL+ 1, 2
6–
–0.3
0.4 0.6
0.7 lsb
lsb
Integr al non  linea rity INL- 1, 2
6-1.0
-1.2 0.7
0.9 –
–lsb
lsb (2)(3)
Integr al non  linea rity INL+ 1, 2
6–
–0.7
0.9 1.0
1.2 lsb
lsb
No missing code – Guaranteed over specified temperature range (3)
Gain error –1, 2
6-10
-11 -2
-2 10
11 % FS
% FS
Input offset voltage –1, 2
6-26
-30 -5
-5 26
30 mV
mV
Gain error drift
Offset error drift –
–4
4100
40 125
50 150
60 ppm/°C
ppm/°C
Transi ent Performance
Bit Error Rate
FS = 1 GSPS FIN = 62.5 MHz BER 4 – – 1E-12 Error/ 
sample (2)(4)
ADC settling time
VIN -VINB = 400 mVpp TS 4 – 0.5 1 ns (2)
Overvo ltage recove ry tim e TOR 4 – 0.5 1 ns (2)
Table 3.  Electrical Specifications (Continued)
Parameter Symbol Test 
Level
Value
Unit NoteMin Typ Max

7
TS8388BF
2144A–BDC–04/02
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj = 70°C, unless otherwise specified.
Signal to Noise and Distortion ratio
SINAD
–– – – –
(2)
FS = 1 GSPS, FIN = 20 MHz 4 42 44 – dB
FS = 1 GSPS, FIN = 500 MHz 4 41 43 – dB
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) 4 38 40 – dB
FS = 50 MSPS, FIN = 25 MHz 1, 2, 6 40 44 – dB
Effective Number Of Bits
ENOB
–– – – –
FS = 1 GSPS, FIN = 20 MHz 4 7.0 7.2 – Bits
FS = 1 GSPS, FIN = 500 MHz 4 6.6 6.8 – Bits
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) 4 6.2 6.4 – Bits
FS = 50 MSPS, FIN = 25 MHz 1, 2, 6 7.0 7.2 – Bits
Signal to Noise Ratio
SNR
–– – – –
(2)
FS = 1 GSPS, FIN = 20 MHz 4 42 45 – dB
FS = 1 GSPS, FIN = 500 MHz 4 41 44 – dB
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) 4 41 44 – dB
FS = 50 MSPS, FIN = 25 MHz 1, 2, 6 44 45 – dB
Total Harmonic Distortion
THD
–– – – –
(2)
FS = 1 GSPS, FIN = 20 MHz 4 50 54 – dB
FS = 1 GSPS, FIN = 500 MHz 4 46 50 – dB
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) 4 42 46 – dB
FS = 50 MSPS, FIN = 25 MHz 1, 2, 6 46 45 – dB
Spurious Free Dynamic Range
SFDR
–– – – –
(2)
FS = 1 GSPS, FIN = 20 MHz 4 52 57 – dBc
FS = 1 GSPS, FIN = 500 MHz 4 47 52 – dBc
FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) 4 42 47 – dBc
FS = 1 GSPS, FIN = 1000 MHz (-3 dBFs) 4 45 50 – dBc
FS = 50 MSPS, FIN = 25 MHz 1, 2, 6 40 54 – dBc
Two- tone Inter-modulation Distortion IMD 4– – – –
(2)
FIN1 = 489 MHz at FS = 1 GSPS,
FIN2 = 490 MHz at FS = 1 GSPS –-47-52 – dBc
Switching Performance and Charcteristics – See Figure 2 and Figure 3 on page 9
Maximum clock frequency FS– 1 – 1.4 GSPS (14)
Minimum clock frequency FS410–50MSPS
(15)
Minimu m C loc k pul se  widt h (high ) TC1 4 0.280 0.500 50 ns
Table 3.  Electrical Specifications (Continued)
Parameter Symbol Test 
Level
Value
Unit NoteMin Typ Max

8TS8388BF 2144A–BDC–04/02
Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA.
2. See “Definition of Terms” on page 41.
3. Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.
4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error).
5. Maximu m j itter va lue ob tained  for sing le-end ed clo ck input o n the J TS8388B d ie (chi p on boa rd): 200  fs. (500  fs expe cted o n
TS8388BG)
6. Digital output back termination options depicted in Application Notes.
7. With a typic al value of TD = 465  ps, at 1 GSPS, the timing sa fet y margin for the da ta storin g using  the ECLinPS 10E4 52 out-
put registers from Motorola® is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,
DRB).
8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level
in to t h e  50 Ω termination resistor of the inphase clock input. (4 dBm into 50Ω clock input correspond to 10 dBm power level
for the clock gene rato r.)
9. At 1 GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.
10. Specifiedloadingconditionsfordigitaloutputs:
-50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces.
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input
parasitic capacitance of 1.5 pF including package and ESD protections.)
11. Terminationloadparasiticcapacitancederatingvalues:
-50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load.
 - Unterminat ed (s ou rce term in ate d) 75Ω controll ed  im ped anc e l ine s: 100 ps /pF o r 150  ps  pe r add iti onnal ECLin PS term in a-
tion load.
12. Appl y pr oper  50/7 5Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388BF Evalua-
tion Board.
13.Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100°C temperature variation).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between
each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are
never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes
about “TOD-TDR Variation Over Temperature” on page 23).
14.Min value guarantees performance. Max value guarantees functionality.
15.Min value guarantees functionality. Max value guarantees performance.
Minimu m C loc k pul se  widt h (low ) TC2 4 0.350 0.500 50 ns
Aperture delay Ta 4 100 +250 400 ps (2)
Aperture uncertainty Jitter 4 – 0.4 0.6 ps (rms) (2)(5)
Data output delay TDO 4 1150 1360 1660 ps (2)(10) 
(11)(12)
Output rise/fall time for DATA (20% – 80%) TR/TF 4 250 350 550 ps (11)
Output rise/fall time for DATA READY (20% – 80%) TR/TF 4 250 350 550 ps (11)
Data ready output delay TDR 4 1110 1320 1620 ps (2)(10) 
(11)(12)
Data ready reset delay TRDR 4 – 720 1000 ps
Data to data ready – Clock low pulse width
(See “Timing Diagrams” on page 9.) TOD-TDR 4 0 40 80 ps (9)(13) 
(14)
Data to data ready output delay (50% duty cycle) 
at 1 GSPS (See “Timing Diagrams” on page 9.) TD1 4 420 460 500 ps (2)(15)
Data pipeline delay TPD 4 4 clock 
cycles
Table 3.  Electrical Specifications (Continued)
Parameter Symbol Test 
Level
Value
Unit NoteMin Typ Max

TS8388BF

2144A–BDC–04/02

Timing Diagrams

Figure 2. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level

Figure 3. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level

TC1 TC2

TA = 250 ps TBC

N+1

XN+2

XN+3

DIGITAL

OUTPUTS

(VIN, VINB)

Data Ready

(DR, DRB)

(CLK, CLKB)

XN+5

N-4 N-3 N

N-2 N-1

TC = 1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB 1 ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

1000 ps

TRDR = 720 ps

N-1

TD2 = TC2+TOD-TDR

= TC2+40 ps = 540 ps

TDR = 1320 ps

DATA DATA DATA DATA DATADATA

N-5 N+1

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

TC1 TC2

TA = 250 ps TBC

N+1 N+2

DIGITAL

OUTPUTS

(VIN, VINB)

Data Ready

(DR, DRB)

(CLK, CLKB)

N+5

N-4 N-3 N

N-1N-2

TC = 1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB

1 ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

TRDR = 720 ps

N-1

TD2 = TC2+TOD-TDR

= TC2+40 ps = 540 ps

TDR = 1320 ps

DATA DATA DATA DATA DATADATA DATA

N-5 N+1

1000 ps

XXX

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

10 TS8388BF 2144A–BDC–04/02

Explanation of

Test Levels

Notes: 1. Unless otherwise specified, all tests are pulsed tests: therefore Tj = Tc = Ta, where Tj, Tc

and Ta are junction, case and ambient temperature respectively.

2. Refer to “Ordering Information” on page 43.

3. Only MIN and MAX values are guaranteed (typical values are issuing from characterization

results).

Functions

Description

Table 4. Explanation of Test Levels

Num Characteristics

1 100% production tested at +25°C(1) (for “C” Tempe ratu re range(2)).

2100% production tested at +25°C(1), and sample tested at specified temperatures

(for “V” and “M” Temperature range(2)).

3 Sample tested only at specified temperatures.

4Parameter is guaranteed by design and characterization testing (thermal steady-state

conditions at specified temperature).

5 Parameter is a typical value only.

6100% production tested over specified temperature range

(for “B/Q” Temperature range(2)).

Table 5. Fu nct ion s Des crip t io n

Name Function

VCC Positive power supply

VEE Analog negative power supply

VPLUSD Digital positive power supply

GND Ground

VIN, VINB Differential analog inputs

CLK, CLKB Differential clock inputs

<D0:D7>

<D0B:D7B> Differential output data port

DR, DRB Differential data ready outputs

OR, ORB Out of range outputs

GAIN ADC gain adjust

GORB Gray or Binary digital output select

DIOD/DRRB Die junction temperature measurement/

asynchronous data ready reset

VIN

VINB

CLK

CLKB D0 D7

D0B D7B

DVEE = -5V

VCC = +5V VPLUSD = +0V (ECL)

VPLUSD = +2.4V (LVDS)

TS8388BF

VEE = -5V GND

GAIN

GORG

DIOD/

DRRB

ORB

DRB

TS8388BF

2144A–BDC–04/02

Digital Output

Coding NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt-

age errors.

Table 6. Digit al Output Coding

Differential

Analog Input Voltage Level

Digital Output

Out of

Range

Binary

GORB = VCC or Floating Gray

GORB = GND

> +251 mV > Positive f ull scale + 1/2 lsb 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1

+251 mV

+249 mV Positive full scale + 1/2 lsb

Positive full scale - 1/2 lsb 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 1 0

+126 mV

+124 mV Positive 1/2 scale + 1/2 lsb

Positive 1/2 scale - 1/2 lsb 1 1 0 0 0 0 0 0

1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0

1 1 1 0 0 0 0 0 0

+1 mV

-1 mV Bipolar zero + 1/2 lsb

Bipolar zero - 1/2 lsb 1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0

-124 mV

-126 mV Negative 1/2 scale + 1/2 lsb

Negative 1/2 scale - 1/2 lsb 0 1 0 0 0 0 0 0

0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0

0 0 1 0 0 0 0 0 0

-249 mV

-251 mV Negative full scale + 1/2 lsb

Negative full scale - 1/2 lsb 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0

< -251 mV < Negative full scale - 1/2 lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

12 TS8388BF 2144A–BDC–04/02

Package

Description

Pin Description

Notes: 1. Following pin numbers 37 (CLK), 40 (CLKB), 54 (VIN) and 57 (VINB) have to be con ne cted to GND thro ugh a 50Ω resistor as

close as possible to the package (50Ω termination preferred option).

2. The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-

tive digital supply level in the same proportion in order to spare power dissipation.

Table 7. TS838 8B F Pi n Descr ipt ion

Symbol Pin number Function

GND 5, 13, 27, 28 , 34, 35, 3 6, 41, 42, 43, 50, 51 ,

52, 53, 58, 59 Ground pins.

To be connected t o external ground plane.

VPLUSD 1, 2, 16, 17, 18, 68 Digital positive supply (0V for ECL compatibility, 2.4V for

LVDS compatibility).(2)

VCC 26, 29, 32, 33, 46, 47, 61 +5V positive supply.

VEE 30, 31, 44, 45, 48 -5V analog negative supply.

DVEE 8, 9, 10 -5V digital negative supply.

VIN 54(1), 55 In phase (+) analog input signal of the Sample and Hold

differential preamplifier.

VINB 56, 57(1) Inverted phase (-) of anal og input signal (VIN).

CLK 37(1), 38 In phase (+) ECL clock input signal. The analog input is

sampled and held on the rising edge of the CLK signal.

CLK B 39, 40(1) Inverted phase (-) of ECL clock input signal (CLK).

D0, D1, D2, D3, D4,

D5, D6, D7 23, 21, 19, 14, 6, 3, 66, 64 In phase (+) digital outputs.

B0 is the LSB. B7 is the MSB.

D0B, D1B, D2B, D3B,

D4B, D5B, D6B, D7B 24, 22, 20, 15, 7, 4, 67, 65 Inverted phase (-) digital outputs.

B0B is the inverted LSB. B7B is the inverted MSB.

OR 62 In phase (+) Out of Range Bit. Out of Range is high on the

leading edge of code 0 and code 256.

ORB 63 Inverted phase (+) Out of Range Bit (OR).

DR 11 In phase (+) output of Data Ready Signal.

DRB 12 Inverted phase (-) output of Data Ready Signal (DR).

GORB 25 Gray or Binary select output format control pin.

- Binary output format if GORB is floating or VCC.

- Gray output format if GORB is connected at ground (0V).

GAIN 60 ADC gain adjust pin.

DIOD/DRRB 49 This pin has a double function (can be left open or grounded

if not used):

- DIOD: die junction temperature monitoring pin.

- DRRB: asynchronous data ready reset function.

TS8388BF

2144A–BDC–04/02

TS8388BF Pinout

Figure 4. TS838 8B F Pinou t

TOP VIEW

TS8388BF

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

VPLUSD

D3B

GND

DRB

DVEE

D4B

GND

D5B

GND

CLK

CLKb

GND

CLKb

GND

VEE

VCC

VEE

Diode

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

GND

VCC

D2B

D1B

VPLUSD

D0B

GORB

VCC

GND

VCC

VEE

VCC

GND

D7B

VPLUSD

Pin 1 index

D6B

ORB

VCC

Gain

GND

VINb

VIN

14 TS8388BF 2144A–BDC–04/02

Typical

Characterization

Results

Static Linearity FS = 50 MSPS/FIN = 10 MHz

Figure 5. Integral Non Linearity

Note: Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz;

Positive peak: 0.78 lsb; Negative peak: -0.73 lsb

Figure 6. Differenti al Non Linear it y

Note: Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz;

Positive peak: 0.3 lsb; Negative peak: -0.39 lsb

TS8388BF

2144A–BDC–04/02

Effective Num ber

of Bits Versus

Power Supplies

Variation

Figure 7. Effective Number of Bits = f (VEEA); FS = 500 MSPS; FIN = 100 MHz

Figure 8. Effective Number of Bits = f (VCC); FS = 500 MSPS; FIN = 100 MHz

Figure 9. Effective Number of Bits = f (VEED); FS = 500 MSPS; FIN = 100 MHz

-7 -6.5 -6 -5.5 -5 -4.5 -4

VEEA (V)

ENOB (bits)

3 3.5 4 4.5 5 5.5 6 6.5 7

VCC (V)

ENOB (bits)

-6 -5.5 -5 -4.5 -4 -3.5 -3

VEED (V)

ENOB (bits)

16 TS8388BF 2144A–BDC–04/02

Typical FFT Results

Figure 10. FS = 1 GSPS; FIN = 20 MHz

Figure 11. FS = 1 GSPS; FIN = 495 MHz

Figure 12. FS = 1 GSPS; FIN = 995 MHz (-3 dB Full Scale Input)

TS8388BF

2144A–BDC–04/02

Spurious Free

Dynamic Range

Versus Input

Amplitude

Figure 13. Sampling Frequency: FS = 1 GSPS; Input Frequency FIN = 995 MHz; Full Scale; ENOB = 6.4;

SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding

Figure 14. Sampling Frequency: FS = 1 GSPS; Input Frequency FIN = 995 MHz; -3 dB Full Scale; ENOB = 6.6;

SINAD = 40.8 dB; SNR = 44 dB; THD = -48 dBc; SFDR = -50 dBc; Gray or Binary Output Coding

18 TS8388BF 2144A–BDC–04/02

Dynamic

Performance

Versus Analog

Input Frequency

FS = 1 GSPS, FIN = 0 up to 1600 MHz, Full Scale input (FS), FS -3 dB

Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and

clock inputs.

Figure 15. ENOB (dB)

Figure 16. SNR (dB)

Figure 17. SFDR (dBc)

0 200 400 600 800 1000 1200 1400 1600 1800

ENOB (dB)

Input frequency (MHz)

-3 dB FS

0 200 400 600 800 1000 1200 1400 1600 1800

SNR (dB)

Input frequency (MHz)

-3 dB FS

-60

-55

-50

-45

-40

-35

-30

-25

-20

0 200 400 600 800 1000 1200 1400 1600 1800

SFDR (dBc)

Input frequency (MHz)

-3 dB FS

TS8388BF

2144A–BDC–04/02

Effective Num ber

of Bits (ENOB)

Versus Sampling

Frequency

Analog Input Frequency: FIN = 495 MHz and Nyquist conditions (FIN = FS/2)

Clock dut y cycle 50/50, Binary output codi ng

Figure 18. ENOB (dB)

SFDR Ve rsus

Sampling

Frequency

Analog Input Frequency: FIN = 495 MHz and Nyquist conditions (FIN = FS/2)

Clock dut y cycle 50/50, Binary output codi ng

Figure 19. SFDR (dBc)

0 200 400 600 800 1000 1200 1400 1600

ENOB (dB)

Sampling frequency (MSPS)

FIN = FS/2

FIN = 500 MHz

-60

-55

-50

-45

-40

-35

-30

-25

-20

0 200 400 600 800 1000 1200 1400 1600

SFDR (dBc)

Sampling frequency (MSPS)

FIN = FS/2

FIN = 500 MHz

20 TS8388BF 2144A–BDC–04/02

TS8388BF ADC

Performances

Versus Junction

Temperature

Figure 20. Effective Number of Bits Versus Junction Temperature

FS = 1 GSPS; FIN = 500 MHz; Duty Cycle = 50%

Figure 21. Signal to Noise Ratio Versus Junction Temperature

FS = 1 GSPS; FIN = 507 MHz; Differential Clock; Single-ended Analog Input (VIN = -1 dBF s )

Figure 22. Total Harmonic Distorsion Versus Junction Temperature

FS = 1 GSPS; FIN = 507 MHz; Differential Clock; Single-ended Analog Input (VIN = -1 dBF s )

-40 -20 0 20 40 60 80 100 120 140 160

Temperature (°C)

ENOB (bits)

Temperature (°C)

-60 -40 -20 0 20 40 60 80 100 120

SNR (dB)

Temperature (°C)

-60 -40 -20 0 20 40 60 80 100 120

THD (dB)

TS8388BF

2144A–BDC–04/02

Figure 23. Power Consumption Versus Junction Temperature

FS = 1 GSPS; FIN = 500 MHz; Duty Cycle = 50%

Typical Full Pow er

Input Bandwidth

Figure 24. 1.5 GHz at -3 dB (-2 dBm Full Power Input)

-40 -20 0 20 40 60 80 100 120 140 160

Power consumption (W)

Temperature (°C)

-6

-5

-4

-3

-2

-1

0100 300 500 700 900 1100 1300 1500 1700

Magnitude (dB)

Frequency (MHz)

22 TS8388BF 2144A–BDC–04/02

ADC Step

Response Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps.

Note: This step resp on se was obtain ed with the TSEV83 88B chip on-b oard (devi ce in die form).

Figure 25. Test Pulse Digitized with 20 GHz DSO

Figure 26. Same Test Pulse Digitized with TS8388BF ADC

Note: Ripples are due to the test setup (they are present on both measurements).

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00

Time

(

)

Tr ~ 240 ps

50 mV/div

Vpp ~ 260 mV

500 ps/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00

200

150

100

ADC code

Time (ns)

Tr ~ 280 ps

50 codes/div (Vpp ~ 260 mV)

500 ps/div

ADC calculated rise time: between 150 and 200 ps

TS8388BF

2144A–BDC–04/02

TS8388BF Main

Features

Timing

Information

Timing Value for

TS8388BF Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simula-

tions and first characterizations results fitted with measurements.

Timing values are given at CQFP68 package inputs/outputs, taki ng into account package

intern al cont rolled impeda nce trac es propag ation de lays, gullwin g pin m odel, and spec ified

termination loads.

Propagation delays in 50/75Ω impedance traces are NOT taken into account for TOD and

TDR.

Apply proper derating values corresponding to termination topology.

The min/max timing values are valid over the full temperature range in the following

conditions:

• Specified Termination Load (Differential output Data and Data Ready):

50Ω resistor in parallel with 1 standard ECLinPS register from Motorola (i.e.: 10E452)

Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package

and ESD prote ct ion s).

If addressing an output Dmux, take care if some Digital outputs do not have the same

termination load and apply corresponding derating value given below.

• Output Termination Load derating values for TOD and TDR:

~ 35 ps/pF or 50 ps per additional ECLinPS load.

• Propagation time delay derating values have also to be applied for TOD and TDR:

~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.

Apply proper time delay derating value if a different dielectric layer is used.

Propagation Time

Considerations TOD and TDR Timing values are given from pin to pin and DO NOT include the additional

propagation times between device pins and input/output termination loads. For the

TSEV8388B Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corre-

sponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board.

If a different dielectric layer is used (for instance Teflon), please use appropriate propagation

time values.

TD does NOT depend on propagation times because it is a differential data (TD is the time dif-

ference between Data Ready output delay and digital Data output delay).

TD is also the most straightforward data to measure, again because it is differential: TD can be

measured directly onto termination loads, with matched Oscilloscopes probes.

TOD-TDR Variation

Over Temperature Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per

100°C temperature variation).

Therefor e TOD-TDR v ariation ov er tempera ture is negli gible. Mor eover, the in ternal (on-c hip)

and package skews between each Data TODs and TDR effect can be considered as

negligible.

24 TS8388BF 2144A–BDC–04/02

Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The

same is true for the TOD and TDR maximum values.

In other terms :

– If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).

– If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR).

However, external TOD-TDR values may be dictated by total digital datas skews

between every TODs (each digital data) and TDR: MCM Board, bonding wires and

output lines lengths differences, and output termination impedance mismatches.

The ext ernal (on bo ard) ske w effect has NOT been taken into ac count for the specif ication of

the minimum and maximum values for TOD-TDR.

Principle of Operation The A nalog input is sampl ed on the rising edge of extern al cloc k input ( CLK, C LKB) af ter TA

(aperture delay) of typically 250 ps. The digitized data is available after 4 clock periods latency

(pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD.

The Data Ready differential output signal frequency (DR, DRB) is half the external clock fre-

quency, that is it switches at the same rate as the digital outputs.

The Data Rea dy outp ut sign al (DR, DRB) s witc he s on ex ter nal cl oc k f all in g edg e aft er a prop-

agation delay TDR of typically 1320 ps.

A Master Async hrono us Reset i nput co mmand D RRB (E CL comp atible sing le-ended input) is

availab le for ini tializing the differenti al Data Re ady outpu t signal (DR, DRB). T his feature is

mandat ory in cert ain appl icati ons using interlea ved ADCs or using a single ADC with demul ti-

plexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the

output digital datas in a defined order.

Principle of Data

Ready Signal

Control by DRRB

Input Command

Data Ready Output

Signal Reset The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low

level (-1.8V). DRRB may also be tied to VEE = -5V for Data Ready output signal Master Reset.

So long DRRB remains at logical low level, (or tied to VEE = -5V), the Data Ready output

remains at logical zero and is independant of the external free running encoding clock.

The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical.

TRDR is measured between the -1.3V point of the falling edge of DRRB input command and

the zero crossing point of the differential Data Ready output signal (DR, DRB).

The Data Ready Reset command may be a pulse of 1 ns minimum time width.

TS8388BF

2144A–BDC–04/02

Data Ready Output

Signal Restart The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels

(-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data

Ready output signal.

The Data Ready signal restart sequence depends on the logical level of the external encoding

clock, at DRRB rising edge instant:

• The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW:

The Data Ready output first rising edge occurs after half a clock period on the clock falling

edge, after a delay time TDR = 1320 ps already defined hereabove.

• The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH:

The Data Ready output first rising edge occurs after one clock period on the clock falling

edge, and a delay TDR = 1320 ps.

Conseque ntly , as the analog input is sa mp led on cloc k risi ng edge , the fi rst d igiti zed data co r-

responding to the first acquisition (N) after Data Ready signal restart (rising edge) is always

strobed by the third rising edge of the data ready signal.

The tim e delay (T D1) is spe cified be tween the l ast point of a change in the differ ential ou tput

data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,

DRB) (zero crossing point).

For normal initiali zation of Data Ready output signal , the external encoding clock signal fre-

quency and level must be controlled. It is reminded that the minimum encoding clock sampling

rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.

One s ingl e pin is used for bo th DRRB inpu t comm and a nd die junct ion t emper atu re moni tor-

ing. Pin denomination will be DRRB/DIO D. On the former version denomination was DIOD.

Temperature monitoring and Data Ready control by DRRB is not possible simultaneously.

Analog Inputs (VIN)

(VINB)The analog input Full Scale range is 0.5V peak to peak (Vpp), or -2 dBm into the 50Ω termina-

tion resistor.

In differential mode input configuration, that means 0.25V on each input, or ±125 mV around

0V. The input common mode is GROUND.

The typical input capacitance is 3 pF for TS8388B in CQFP package.

The input capacitance is mainly due to the package. The ESD protections are not connected

(but present) on the inputs.

Differential Inputs

Voltage Span Figure 27. Differiential Inputs Voltage Span

-125

125

[mV]

-250 mV

VIN

(VIN, VINB) = ±250 mV = 500 mV diff

500 mV

Full Scale

analog input

VINB

250 mV

26 TS8388BF 2144A–BDC–04/02

Differential Versus

Single-ended Analog

Input Operation

The TS8388BF can operate at full speed in either differential or single-ended configuration.

This is expl ained by the fac t the ADC uses a hi gh input impe dance diffe rential prea mplifier

stage, (preceeding the Sample and hold stage), which has been designed in order to be

entered either in differential mode or single-ended mode.

This is true so long as the out-of-phase analog input pin VINB is 50Ω terminated very closely to

one of the neighboring s hield ground pins (52, 53, 5 8, 59) which constitute the loca l ground

reference for the inphase analog input pin (VIN).

Thus the differential analog input preamplifier will fully reject the local ground noise (and any

capacitively and inductively coupled noise) as common mode effects.

In typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input

pin (VINB) grounded through the 50Ω termination resistor.

In single-ended in put configuration, the in-phas e input amplitude is 0.5V peak to peak, cen-

tered on 0V (or -2 dBm i nto 50Ω). T he in vert ed phase i nput i s at gro und pote ntial throug h the

50Ω terminati on resis tor .

However, dynamic performances can be somewhat improved by entering either analog or

clock inputs in differential mode.

Typical Single-ended

Analog Input

Configuration

Figure 28. Typical Single-ended Analog Input Configuration

Clock Inputs (CLK)

(CLKB) The TS 8388BF ca n be clocked at full speed with out noticeabl e performance degradation in

either differential or single-ended configuration.

This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,

which has been designed in order to be entered either in differential or single-ended mode.

Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor

spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.

Single-ended Clock

Input (Ground

Common Mode)

Althoug h the cl ock inpu ts were i ntended t o be dr iven diffe rentially w ith nomi nal -0.8V /-1.8V

ECL levels, the TS8388BF clock buffer can manage a single-ended sinewave clock signal

centered around 0V. This is the most convenient clock input configuration as it does not

require the use of a power splitter.

No performance degradation (i.e.: due to timing jitter) is observed in this particular single-

ended configuration up to 1.2 GSPS Nyquist conditions (FIN = 600 MHz).

50Ω

(external)

1 MΩ3 pF

-250

250

500 mV

[mV] VIN

VIN = ±250 mV = 500 mV diff

VIN or VINB double pad (pins 54, 55 or 56, 57)

VIN or VINB

50Ω reverse termination

500 mV

Full Scale

analog input VINB = 0V

VINB

TS8388BF

2144A–BDC–04/02

This is true so long as the inverted phase clock input pin is 50Ω terminated very closely to one

of the neighboring shield ground pins, which constitutes the local Ground reference for the

inphase clock input.

Thus the TS8388BF differential clock input buffer will fully reject the local ground noise (and

any capaciti vely and ind uctively coupled noise) as comm on mode effect s. Moreover, a very

low phase noise sinewave generator must be used for enhanced jitter performance.

The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) com-

mon mode. This corresponds to a typical clock input power level of 4 dBm into the 50Ω

termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input

transistors.

The inverted phase clock input is grounded through the 50Ω termination resistor.

Figure 29. Single-ended Clock Input (Ground common mode):

VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50Ω termination resistor)

Note: Do not exceed 10 dBm into the 50Ω termination resistor f or single clo c k input power leve l.

Differential ECL Clock

Input The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.

In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, fol-

lowed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase

sinewave si gnals. Biasi ng tees can be use d for offseting th e common mode v oltage to ECL

levels.

Note: As the biasing tees propagation times are not matching, a tunable delay line is required

in orde r to ensure the signals to be 18 0 degree s out of phase especiall y at fast clo ck rates in

the GSPS range.

Figure 30. Differential Clock Inputs (ECL Levels)

50Ω

(external)

1 MΩ0.4 pF

-0.5V

+0.5V

[V] VCLK

CLK or CLKB double pad (pins 37, 38 or 39, 40)

CLK or CLKB

50Ω reverse termination

VCLK = 0V

VCLK

50Ω

(external)

1 MΩ0.4 pF

CLK or CLKB double pad (pins 37, 38 or 39, 40)

CLK or CLKB

-2V

50Ω reverse termination

-1.8V

-0.8V

[mV]

VCLK

VCLKB

Common mode = -1.3V

28 TS8388BF 2144A–BDC–04/02

Single-ended ECL

Clock Input In single-ended configuration enter o n CLK (resp. CLKB) pin, with the inverted phase Clock

input pin CLKB (respectively CLK) connected to -1.3V through the 50Ω termi nati on resi st or.

The inphase input amplitude is 1V peak to peak, centered on -1.3V common mode.

Figure 31. Single-ended Clocl Input (ECL):

VCLK Common Mode = -1.3V; VCLKB = -1.3V

Noise Immunity

Information Circuit noise immunity performance begins at design level.

Efforts have been made on the design in order to make the device as insensitive as possible

to chi p envi ronment pertur bations r esulting from the ci rcuit i tself or induc ed by ex ternal c ir-

cuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip)

decoupling capacitors).

Furthermore, the fully differential operation from analog input up to the digital outputs provides

enhanced noise immunity by common mode noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be can-

celed out by these balanced differential amplifiers.

Moreover, proper active signals shielding has been provided on the chip to reduce the amount

of coupled noise on the active inputs.

The analog inputs and clock inputs of the TS8388BF device have been surrounded by ground

pins, which must be directly connected to the external ground plane.

Digital Outputs The T S8388BF different ial outpu t buffers a re intern ally 75Ω loaded. The 75Ω resistors are

connected to the digital ground pins through a -0.8V level s hift diode (see Figure 32, Figure

33, Figure 34 on page 30).

The TS838 8BF output buffers a re designed for drivin g 75Ω (default) or 50Ω pr operly termi -

nated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of

the 75Ω res i sto rs whe n s witching ensur es a 0.825 V vol tage drop ac ross the r esi s tor ( unte rm i-

nated outputs).

The V PLUSD positive supply voltage allows the adjus tment of the output common mode leve l

from -1.2V (VPLUSD = 0V fo r E C L ou tp ut c om p ati b il it y) t o +1. 2V (V PLUSD = 2.4V for LVD S outpu t

compatibility).

Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,

(outputs unterminated), around -1.2V common mode voltage.

-1.8V

-0.8V

[V] VCLK

VCLKB = -1.3V

TS8388BF

2144A–BDC–04/02

Three p ossi ble line d riving and bac k-term ination scena rios are p ropos ed (assu ming V PLUSD =

0V):

1. 75Ω impedance tran sm is si on lines , 75Ω differentially terminated (Figure 32):

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading

to ±0.41V = 0.8 25V i n d iff er enti al, a round - 1.2 1V ( re spec tiv el y +1 .21V ) c om mon mode for

VPLUSD = 0V (respe cti v ely 2. 4V).

2. 50Ω impedance tran sm is si on lines , 50Ω differentially termination (Figure 33):

Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V),

leading to ±0 .33V = 660 mV i n dif ferent ial, a round -1.18V (re specti vely +1.2 1V) co mmon

mode for VPLUSD = 0V (respectively 2.4V).

3. 75Ω impedance open transmission lines (Figure 34):

Each ou tput voltag e varies between -1.6V and -0.8 V (respecti vely +0.8V an d +1.6V),

which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V ( respec-

tively +1.2V) common mode for VPLUSD = 0V (respectively 2.4V). Therefore, it is possible

to drive directly high input impedance storing registers, without terminating the 75Ω trans-

missi on lines . In time do main, tha t means that the inci dent wave will reflect at the 75Ω

transmission line output and travel back to the generator (i.e.: the 75Ω data output buffer).

As the buffer output impedance is 75Ω, no back reflection will occur.

Note: This is no longer true if a 50Ω transmission line is used, as the latter is not matching the

buffer 75Ω output impedance.

Each differential output termination length must be kept identical. It is recommended to decou-

ple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode

perturbation in case of slight mismatch in the differential output line lengths.

Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching

currents flowin g into the decoup li ng cap ac ito r leadi ng to switc hing gr oun d nois e.

The differential output voltage levels (75Ω or 50Ω termination) are not ECL standard voltage

levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line

from Motorola®.

At sampling rates exceeding 1 GSPS, it may be difficult to trigger the HP16500 or any other

Acquisition System with digital outputs. It becomes necessary to regenerate digital data and

Data Ready by means o f external amplifiers, i n order to be able to test the TS8388BF at its

optimum performance conditions.

30 TS8388BF 2144A–BDC–04/02

Differential Output Loading Configurations (Levels for ECL Compatibility)

Figure 32. Differential Output: 75Ω Terminated

Figure 33. Differential Output: 50Ω Terminated

Figure 34. Differential Output: Open Loaded

-0.8V

75Ω75Ω

11 mA

DVEE

75Ω

impedance

Out

OutB

75Ω

-1V/-1.41V

10 nF

Differential output:

+0.41V = 0.825V

-1.41V/-1V

Common mode level: -1.2V

(-1.2V below VPLUSD level)

VPLUSD = 0V

-0.8V

75Ω75Ω

11 mA

DVEE

50Ω

impedance

Out

OutB

50Ω

-1.02V/-1.35V

10 nF

Differential output:

+0.33V = 0.660V

-1.35V/-1.02V

Common mode level: -1.2V

(-1.2V below VPLUSD level)

VPLUSD = 0V

-0.8V

75Ω75Ω

11 mA

DVEE

75Ω

impedance

Out

OutB

-0.8V/-1.6V

Differential output:

+0.8V = 1.6V

-1.6V/-0.8V

Common mode level: -1.2V

(-1.2V below VPLUSD level)

VPLUSD = 0V

TS8388BF

2144A–BDC–04/02

Differential Output Loading Configurations (Levels for LVDS Compatibility)

Figure 35. Differential Output: 75Ω Terminated

Figure 36. Differential Output: 50Ω Terminated

Figure 37. Differential Output: Open Loaded

1.6V

75Ω75Ω

11 mA

DVEE

75Ω

impedance

Out

OutB

75Ω

1.4V/0.99V

10 nF

Differential output:

+0.41V = 0.825V

0.99V/1.4V

Common mode level: -1.2V

(-1.2V below VPLUSD level)

VPLUSD = 2.4V

1.6V

75Ω75Ω

11 mA

DVEE

50Ω

impedance

Out

OutB

50Ω

1.38V/1.05V

10 nF

Differential output:

+0.33V = 0.660V

1.05V/1.38V

Common mode level: -1.2V

(-1.2V below VPLUSD level)

VPLUSD = 2.4V

1.6V

75Ω75Ω

11 mA

DVEE

75Ω

impedance

Out

OutB

1.6V/0.8V

Differential output:

+0.8V = 1.6V

0.8V/1.6V

Common mode level: -1.2V

(-1.2V below VPLUSD level)

VPLUSD = 2.4V

32 TS8388BF 2144A–BDC–04/02

Out of Range Bit An Out of Range (OR, ORB) bit is provided that goes to logical high state when the i nput

exceeds the positive full scale or falls below the negative full scale.

When the analog input exceeds the positive full scale, the digital output datas remain at high

logical state, with (OR, ORB) at logical one.

When the analog input falls below the negative full scale, the digital outputs remain at logical

low state, with (OR, ORB) at logical one again.

Gray or Binary

Output Data

Format Select

The TS8388BF internal regeneration latches indecision (for inputs very close to latches

threshold) m ay produce erro rs in the logic encoding circuitry and leading to lar ge amplitude

output erro rs.

This is due to the fact that the latches are regenerating the internal analog residues into logical

states with a finite voltage gain value (Av) within a given positive amount of time ∆(t):

Av = exp(∆(t)/τ), with τ the positive feedback regeneration time constant.

The TS8388BF has been designed for reducing the probability of occurrence of such errors to

approximately 10-13 (targeted for the TS8388BF at 1 GSPS).

A standard technique for reducing the amplitude of such errors down to ± 1 lsb consists of out-

putting the digital datas in Gray code format. Th ough the TS8388BF has been desig ned for

featuring a Bit Error Rate of 10-13 with a binary output format, it is possible for the user to

select between the Binary or Gray output data format, in order to reduce the amplitude of such

errors when occurring, by storing Gray output codes.

Digital Datas format selection:

• BINARY output format if GORB is floating or VCC.

• GRAY output format if GORB is connected to ground (0V).

Diode Pin 49 One singl e pin is used for bo th DRRB input c ommand and di e junction mon itoring. The pi n

denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is

not possible simultaneously.

(See “Principle of Data Ready S ignal Con trol by DRRB Inpu t Comma nd” on page 24 for Da ta

Ready Reset input command).

The operating die junction temperature must be kept below 145°C, therefore an adequate

cooling system has to be set up. The diode mou nted transistor measur ed Vbe value ver sus

junction temperature is given below.

Figure 38. Diode Pin 49

600

640

680

720

760

800

840

880

920

960

1000

-55 -35 -15 5 25 45 65 85 105 125

VBE (mV)

Junction temperature (°C)

TS8388BF

2144A–BDC–04/02

ADC Gain Control

Pin 60 The ADC gain is adjustable by the means of the pin 60 (input impedance is 1 MΩ in parallel

with 2 pF).

The gain adjust transfer function is given below.

Figure 39. ADC Gain Control Pin 60

Note: For more information, please refer to the document "DEMUX and ADCs Application Notes".

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

-500 -400 -300 -200 -100 0 100 200 300 400 500

ADC Gain

ain

(

command volta

)

(

)

34 TS8388BF 2144A–BDC–04/02

Equivalent

Input/Output

Schematics

Figure 40. Equivalent Analog Input Circuit and ESD Protections

Note: The ESD protection equivalent capacitance is 150 fF.

Figure 41. Equivalent Analog Clock Input Circuit and ESD Protections

Note: The ESD protection equivalent capacitance is 150 fF.

VEE VEE

5.8V

0.8V

200Ω200Ω

50Ω50Ω

E21V

E21G E21G

E21V

VIN

GND = 0V

VIN

Pad

capacitance

340 fF

Pad

capacitance

340 fF

VCC = +5V

-0.8V

-5.8V

5.8V

0.8V

-0.8V

-5.8V

VCLAMP = +2.4V

+1.65V

-1.55V

VEE = -5V

GND

VCC

VEE VEE

5.8V

0.8V

150Ω150Ω

E31V

E21GE21G

E31V

CLK CLKB

Pad

capacitance

340 fF

Pad

capacitance

340 fF

VCC = +5V

-5.8V

5.8V

0.8V

-0.8V

-5.8V

+0.8V

GND = 0V

380 µA

VEE = -5V

VCC

TS8388BF

2144A–BDC–04/02

Figure 42. Equivalent Data Output Buffer Circuit and ESD Protections

Note: The ESD protection equivalent capacitance is 150 fF.

Figure 43. ADC Gain Adjust Equivalent Analog Input Circuit and ESD Protections

Note: The ESD protection equivalent capacitance is 150 fF.

5.8V

0.8V

VEE VEE

-5.8V

E21GA

E01V E01V

-5.8V

OUT

Pad

capacitance

180 fF

DVEE = -5V

VPLUSD = 0V to 2.4V

VEE = -5V VEE = -5V

5.8V

0.8V

OUTB

Pad

capacitance

180 fF

VEE

1 kΩ

Pad

capacitance

180 fF 2 pF

NP1032C2 +0.8V

500 µA 500 µA

VEE = -5V

E22V

VCC = +5V

GND

-0.8V

-5.8V

0.8V

5.8V

E22GA

36 TS8388BF 2144A–BDC–04/02

Figure 44. GORB Equivalent Input Schematic and ESD Protections

GORB: Gray or Binary Select Input; Floating or Tied to VCC -> Binary

Note: The ESD protection equivalent capacitance is 150 fF.

Figure 45. DRRB Equivalent Input Schematic and ESD Protections

Actual Protection Range: 6.6V above VEE, in fact stress above GND are clipped by the CB diode used for Tj monitoring

Note: The ESD protection equivalent capacitance is 150 fF.

5.8V

VEE

E21VA

-0.8V

-5.8V

E31G

1 kΩ

5 kΩ

1 kΩ

GORB

Pad

capacitance

180 fF

VCC = +5V

250 µA 250 µA

GND = 0V

VEE = -5V

5.8V

-2.6V

-1.3V

0.8V

200Ω

10 kΩ

E21G

DRRB

VEE

GND=0V

VCC = +5V

VEE = -5V

Pad

capacitance

180 fF

NP1032C2

TS8388BF

2144A–BDC–04/02

TSEV8388BF:

Device

Evaluation

Board

For complete specification, see separate TSEV8388B document.

General

Description The TSEV8388BF Evaluation Board (EB) is a board which has been designed in order to facil-

itate the eval uation an d the cha racteriz ation of the TS8388B F device up to its 1.5 GHz ful l

power bandwidth at up to 1 GSPS in the military temperature range.

The high speed of the TS8388BF requires careful attention to circuit design and layout to

achieve optimal performance.

This four metal layer board with internal ground plane has the adequate functions in order to

allow a quick and simple evaluation of the TS8388BF ADC performances over the tempera-

ture range.

The TSEV8388BF Evaluation Board is very straightforward as it only implements the

TS8388BF ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector

compatible with HP16500C high frequency probes.

The board also implements a de-embedding fixture in order to facilitate the evaluation of the

high frequency insertion loss of the input microstrip lines, and a die junction temperature mea-

surement setting.

The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and

enhance d thermal cha ract eristics for opera tion in the high frequ ency domai n and exte nded

temperature range.

The board dim ensi ons are 130 mm x 130 mm.

The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package

installed.

38 TS8388BF 2144A–BDC–04/02

Nominal CQFP68

Thermal

Characteristics

Although the power dissipation is low for this performance, the use of a heat sink is

mandatory.

The user will find some advice on this topics below.

Thermal Resistance

from Junction to

Ambient: RTHJA

The following table lists the converter thermal performance parameters, with or without

heatsink.

For the following measurements, a 50 x 50 x 16 mm heatsink has been used (see Figure 47

on page 39).

Note: 1. Heatsink is glued to backside of package or screwed and pressed with thermal grease.

Figure 46. Thermal Resistance from Junction to Ambient: Rthja

Table 8. Thermal Resitance

Air Flow

(m/s)

ja Thermal Resistance (°C/W)

CQFP68 on Board

Estimated – Without Heatsink Targeted – With Heatsink(1)

050 10

0.5 40 8.9

135 7.9

1.5 32 7.3

230 6.8

2.5 28 6.5

326 6.2

424 5.8

523.5 5.6

RTHJA (°C/W)

Air flow (m/s)

123 45

Without heatsink

With heatsink

TS8388BF

2144A–BDC–04/02

Thermal Resistance

from Junction to

Case: RTHJC

Typical value for Rthjc is given to 4.75°C/W.

CQFP68 Board

Assembly

Figure 47. CQFP68 Board Assembly with a 50 x 50 x 16 mm External Heatsink

24.13

28.96

15.0

1.3 3.2

50.0

1.4 4.0

2.5

16.0

Printed circuit

Interface: Af-filled epoxy or thermal

conductive grease - 100 µm max.

Aluminum heatsink

40 TS8388BF 2144A–BDC–04/02

Enhanced CQFP68

Thermal

Characteristics

Enhanced CQFP68 The CQFP68 has been modified, in order to improve the thermal characteristics:

• A CuW heatspreader has been added at the bottom of the package.

• The die has been electrically isolated with the ALN substrate.

Thermal Resistance

from Junction to

Case: RTHJC

Typical value for Rthjc is given to 1.56°C/W.

This value does not include thermal contact resistance between package and external compo-

nent (heatsink or PCBoard).

As an example, 2.0°C/W can be taken for 50 µm of thermal grease.

Heatsink It is recommended to use an external heatsink, or PCBoard special design.

The stand off has been calculated to permit the simultaneous soldering of the leads and of the

heatspreader with the solder paste.

Figure 48. Enhanced CQFP68 Suggested Assembly

Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated

in the device.

Printed

circuit board

CuW heatspreader

28.78

Thermal via Solid ground plane

24.13

TS8388BF

2144A–BDC–04/02

Definitions

Definition of

Terms

(BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that dif-

fers by more than ± 4 lsb from the correct code.

(FPBW) Full Power

Input Bandwidth Analog input frequency at which the fundamental component in the digitally reconstructed out-

put has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for

input at Full Scal e.

(SINAD) Signal to Noise

and Distortion Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS

sum of all other spectral components, including the harmonics except DC.

(SNR) Signal to Noise

Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS

sum of all other spectral components excluding the five first harmonics.

(THD) Total Harmonic

Distorsion Ratio expressed in dBc of the RMS su m of the first fi ve har monic co mponents , to the RMS

value of the measured fundamental spectral component.

(SFDR) Spurious Free

Dynamic Range Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS

value of the next hig hest spectral component (peak spurious spec tral component). SFDR is

the key par ameter for selecting a converter to be used in a frequency domain application

(Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.:

degrades as si gnal levels is lowered), or in dBFS (i.e.: always related back to converter full

scale).

(ENOB) Effectiv e

Number Of Bits

Where A is the actual input amplitude and V is the full scale range of the ADC under test.

(DNL) Differential Non

Linearity The Differential Non Linearity for an output code i is the difference between the measured step

size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum

value of all DNL (i). DN L error sp ecificat ion of less th an 1 lsb gua rantees th at there are no

missing output codes and that the transfer function is monotonic.

(INL) Integral Non

Linearity The Integral Non Linearity for an output code i is the difference between the measured input

voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

(DG) Differential Gain The peak g ain vari ation (in percent) at fi ve diffe rent DC le vels for an AC signal of 20% Full

Scale peak to peak amplitude. FIN = 5 MHz (TBC).

(DP) Differential Phase Peak Phase variation ( in degrees) at five different DC levels for an AC signal of 20% Full

Scale peak to peak amplitude. FIN = 5 MHz (TBC).

(TA) Aperture Delay Delay between the rising edge of the differential clock inputs (C LK, CLKB) (zero crossing

point), and the tim e at which (VIN, VINB) is sampled.

SINAD - 1.76 + 20 log (A/V/2)

6.02

ENOB =

42 TS8388BF 2144A–BDC–04/02

(JITTER) Aperture

Uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the

slew rate of the signal at the sampling point.

(TS) Settling Time Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step

function is applied to the differential analog input.

(ORT) Overvoltage

Recove ry Time Time to r ecov er 0.2 % ac cur ac y at the outp ut, after a 15 0% f ull s cale s tep app li ed o n t he i np ut

is reduced to midscale.

(TOD) Digital Data

Output Delay Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to

the next point of change in the differential output data (zero crossing) with specified load.

(TD1) Time Delay from

Data to Data Ready Time delay from Data transition to Data ready.

(TD2) Time Delay from

Data Ready to Data General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock

period.

(TC) Encoding Clock

Period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output

data be ing ma de ava ilab le, (not takin g in acc ount th e TOD) . For the TS8388 BF th e TPD is 4

clock periods.

(TRDR) Data Ready

Reset Delay Delay bet ween the f allin g edge o f the Data Read y outpu t asyn chro nous R eset s ignal (DDRB)

and the reset to digital zero transition of the Data Ready output signal (DR).

(TR) Rise Time Time delay for the output DATA signals to rize from 20% to 80% of delta between low level

and high level.

(TF) Fall Time Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and

high level.

(PSRR) Power Supply

Rejection Ratio Ratio of input offset variation to a change in power supply voltage.

(NRZ) Non Return to

Zero When the i npu t s igna l is l arger tha n t he upp er b oun d o f the ADC inpu t r an ge, the o utpu t c od e

is iden tical to t he ma ximum c ode a nd the Out of Ra nge bit is set t o logic one. When t he inp ut

signal is smaller than the lower bound of the ADC input range, the output code is identical to

the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input sig-

nal amplitude remains within the absolute maximum ratings).

(IMD) InterModulation

Distortion The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the

worst third order intermodulation products. The input tones levels are at -7 dB Full Scale.

(NPR) Noise Power

Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under tes t, the Noise Power Ratio is defined as the ratio of the avera ge out-of-notc h to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

TS8388BF

2144A–BDC–04/02

Ordering

Information

Package Device

Evaluation Board

The evaluation board is delivered with an ADC and includes the heat sink.

TS 8388B M

Manufacturer prefix Screening Level

__: Standard

B/Q: Mil-PRF-38535, QML level Q

Space: according to ESA/scc 9000

Device or family

Temperature Range:

M: -55°C < Tc; Tj < 125°C

V: -40°C < Tc < 110°C

C: 0°C < Tc < 90°C

Package:

F: CQFP68 gullwing

FS: Enhanced CQFP68 with

heats

reader

FB/Q

TS EV 8388B

ZA2: with MC100EL16

digital recivers

__: No receivers

Evaluation board

refix CQFP68 package

FZA2

44 TS8388BF 2144A–BDC–04/02

Outline

Dimensions Figure 49. Package Dimension – 68-lead Ceramic Quad Flat Pack (CQFP)

CQFP 68

TOP VIEW

0.8 BCS

20.32 BSC

0.050 BCS

1.27 BSC

Pin N° 1 index

0.023 ± 0.002

0.58 ± 0.05

24.13 ± 0.152

0.950 ± 0.006

28.78 - 29.13

1.133 - 1.147

0.13 - 0.25

0.005 - 0.010

0.70 - 0.95

0° - 8°

0.027 - 0.037

0.950 ± 0.006

24.13 ± 0.152

1.133 - 1.147

28.78 - 29.13

0.075 ± 0.008

1.9 ± 0.20

0.135 Max

3.43 Max

0.018 - 0.035

0.46 - 0.88

M∅

0.005ZXY

0.004

TS8388BF

2144A–BDC–04/02

Figure 50. Package Dimension – 68-lead Enhanced CQFP with Heatspreder

CQFP 68

TOP VIEW

0.8 BCS

20.32 BSC

0.050 BCS

1.27 BSC

Pin N° 1 index

0.023 ± 0.002

0.58 ± 0.05

24.13 ± 0.152

0.950 ± 0.006

28.78 - 29.13

1.133 - 1.147

0.13 - 0.25

0.005 - 0.010

0.70 - 0.95

0° - 8°

0.027 - 0.037

0.950 ± 0.006

24.13 ± 0.152

1.133 - 1.147

28.78 - 29.13

0.0310

0.787 0.0385

0.978

0.007 ± 0.005

0.18 ± 0.13

M∅

0.005ZXY

0.020 ± 0.005

0.51 ± 0.13

46 TS8388BF 2144A–BDC–04/02

Datasheet

Status

Description

Life Support

Applications These pro ducts ar e not des ig ned for use in lif e su ppo rt appliances , devic es or sys tem s wh er e

malfunction of these products can reasonably be expected to result in personal injury. Atmel

custo mers us ing or se llin g these product s for use in such applica tions do so at th eir own r isk

and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

Table 9. Datasheet Status

Datasheet Status Validity

Objective specification This datasheet contains target and

goal sp ecifications f or discussion with

customer and application validation.

Before design phase

Target specification This datasheet contains target or

goal specifications for product

development.

Valid during the design phase

Preliminary specification

α-site This datasheet contains preliminary

data. Additional data may be

published later; could include

simulation results.

Valid before characterization

phase

Preliminary specification

β-site This datasheet contains also

characterization results. Valid before the

industrialization phase

Product specification This datasheet contains final product

specification. Valid for production purposes

Limiting Values

Limitin g value s give n are in accordanc e with th e Absolu te Maxi mum Rati ng Syste m (IEC 134). Stres s

above one or more of the limiting values may cause permanent damage to the device. These are

stress r atings on ly and ope ration of th e device at these o r at any oth er conditi ons abov e those gi ven in

the Char acteristics sectio ns of the specific ation is not im plied. Expos ure to limiting values for e xtended

periods m ay affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Printed on recycled paper.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Term s and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this docum ent, reserves the right to change devices or specifications detailed herein at any time w ithout notice, and does

not make any commitment to update t he information contained herein. No licenses to patents or other intellectual property of At mel are granted

by the Company in connec tion with the sale of Atmel p roducts, expres sly or by implication. At mel’s pr oduct s are not authorized f or use as crit ical

components in life s upport devic es or s ystems.

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