EL5420CLZ-T13 - Intersil Corporation

FN7186.7

EL5120, EL5220, EL5420

12MHz Rail-to-Rail Input-Output Op Amps

The EL5120, EL5220, and EL5420 are low power, high

voltage, rail-to-rail input-output amplifiers. The EL5120

contains a single amplifier, the EL5220 contains two

amplifiers, and the EL5420 contains four amplifiers.

Operating on supplies ranging from 5V to 15V, while

consuming only 500µA per amplifier, the EL5120, EL5220,

and EL5420 have a bandwidth of 12MHz (-3dB). They also

provide common mode input ability beyond the supply rails,

as well as rail-to-rail output capability. This enables these

amplifiers to offer maximum dynamic range at any supply

voltage.

The EL5120, EL5220, and EL5420 also feature fast slewing

and settling times, as well as a high output drive capability of

30mA (sink and source). These features ma ke thes e

amplifiers ideal for use as voltage reference buffers in Thin

Film T ransistor Liquid Crystal Displays (TFT-LCD). Other

applications include battery po wer, portab le devices, and

anywhere low power consumption is important.

The EL5420 is available in the space-saving 14 Ld TSSOP

package, the industry-standard 14 Ld SOIC package, as well

as the 16 Ld QFN package. The EL5220 is available in the

8 Ld MSOP package and the 8Ld DFN package. The

EL5120 is available in the 5 Ld TSOT package. All feature a

standard operational amplifier pin out. These amplifiers are

specified for operation with an ambient and junction

temperature range of -40°C to +125°C.

Features

• 12MHz -3dB Bandwidth

• Supply Voltage = 4.5V to 16.5V

• Low Supply Current (per Amplifier) = 500µA

• High Slew Rate = 10V/µs

• Unity-Gain Stable

• Beyond the Rails Input Capability

• Rail-to-Rail Output Swing

• Ultra-Small Package

• Pb-Free Available (RoHS Compliant)

Applications

• TFT-LCD Drive Circuit s

• Electronics Notebooks

• Electronics Games

• Touch-Screen Displays

• Personal Communicati on Devices

• Personal Digital Assistant s (PDA)

• Portable Instrumentation

• Sampling ADC Amplifiers

• Wireless LANs

• Office Automation

• Active Filters

• ADC/DAC Buffer

Data Sheet December 15, 2011

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN7186.7

December 15, 2011

Ordering Information

PART NUMBER

(Note 3) PART

MARKING TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

EL5120IWT-T7 (Notes 1, 4) K -40 to +125 5 Ld TSOT Tape and Reel MDP0049

EL5120IWT-T7A (Notes 1, 4) K -40 to +125 5 Ld TSOT Tape and Reel MDP0049

EL5120IWTZ-T7 (Notes 1, 2, 4) BKAA -40 to +125 5 Ld TSOT Tape and Reel (Pb-Free) MDP0049

EL5120IWTZ-T7A (Notes 1, 2, 4) BKAA -40 to +125 5 Ld TSOT Tape and Reel (Pb-Free) MDP0049

EL5220ILZ-T13 (Notes 1, 2, 4) 20Z -40 to +125 8 Ld DFN Tape and Reel (Pb-Free) L8.2x3

EL5220CY (Note 4) D -40 to +125 8 Ld MSOP MDP0043

EL5220CY-T7 (Note 4) D -40 to +125 8 Ld MSOP Tape and Reel MDP0043

EL5220CY-13 (Note 4) D -40 to +125 8 Ld MSOP Tape and Reel MDP0043

EL5220CYZ (Note 2) BBAAA -40 to +125 8 Ld MSOP (Pb-Free) MDP0043

EL5220CYZ-T7 (Notes 1, 2) BBAAA -40 to +125 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043

EL5220CYZ-T13 (Notes 1, 2) BBAAA -40 to +125 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043

EL5420CL (Note 4) 5420CL -40 to +125 16 Ld QFN MDP0046

EL5420CL-T7 (Notes 1, 4) 5420CL -40 to +125 16 Ld QFN Tape and Reel MDP0046

EL5420CL-T13 (Notes 1, 4) 5420CL -40 to +125 16 Ld QFN Tape and Reel MDP0046

EL5420CLZ (Note 2) 5420CLZ -40 to +125 16 Ld QFN (Pb-Free) MDP0046

EL5420CLZ-T7 (Notes 1, 2) 5420CLZ -40 to +125 16 Ld QFN Tape and Reel (Pb-Free) MDP0046

EL5420CLZ-T13 (Notes 1, 2) 5420CLZ -40 to +125 16 Ld QFN Tape and Reel (Pb-Free) MDP0046

EL5420CS (Note 4) 5420CS -40 to +125 14 Ld SOIC MDP0027

EL5420CS-T7 (Notes 1, 4) 5420CS -40 to +125 14 Ld SOIC Tape and Reel MDP0027

EL5420CS-T13 (Notes 1, 4) 5420CS -40 to +125 14 Ld SOIC Tape and Reel MDP0027

EL5420CSZ (Note 2) 5420CSZ -40 to +125 14 Ld SOIC (Pb-Free) MDP0027

EL5420CSZ-T7 (Notes 1, 2) 5420CSZ -40 to +125 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027

EL5420CSZ-T13 (Notes 1, 2) 5420CSZ -40 to +125 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027

EL5420CR (Note 4) 5420CR -40 to +125 14 Ld TSSOP MDP0044

EL5420CR-T7 (Notes 1, 4) 5420CR -40 to +125 14 Ld TSSOP Tape and Reel MDP0044

EL5420CR-T13 (Notes 1, 4) 5420CR -40 to +125 14 Ld TSSOP Tape and Reel MDP0044

EL5420CRZ (Note 2) 5420CRZ -40 to +125 14 Ld TSSOP (Pb-Free) M14.173

EL5420CRZ-T7 (Notes 1, 2) 5420CRZ -40 to +125 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173

EL5420CRZ-T13 (Notes 1, 2) 5420CRZ -40 to +125 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for EL5120, EL5220, EL5420. For more information on MSL please

see tech brief TB363.

4. Not recommended for new designs. Refer to EL5x20T for possible substitutions.

EL5120, EL5220, EL5420

3FN7186.7

December 15, 2011

Pinouts

EL5420

(16 LD QFN)

TOP VIEW

VINA-

VINA+

VS+

VINB+

VINB-

VOUTB

VOUTC

VINC-

VOUTA

VOUTD

VIND-

VIND+

VS-

VINC+

VS+

VIN-VIN+

VS-

VOUT

VS+

VOUTB

VINB-

VINB+VS-

VINA+

VINA-

VOUTA

THERMAL

PAD

EL5220

(8 LD MSOP)

TOP VIEW

EL5120

(5 LD TSOT)

TOP VIEW

-+ -+

VOUTD

VIND-

VIND+

VS-

VINC+

VINC-

VOUTCVOUTB

VINB-

VINB+

VS+

VINA+

VINA-

VOUTA

-+ -+

EL5420

(14 LD TSSOP, SOIC)

TOP VIEW

VOUTA

VINA-

VINA+

VS-

VS+

VOUTB

VINB-

VINB+

EL5220

(8 LD DFN)

TOP VIEW

THERMAL

PAD

THERMAL PAD

CONNECTS TO VS-

THERMAL PAD

CONNECTS TO VS-

EL5120, EL5220, EL5420

4FN7186.7

December 15, 2011

IMPORTANT NOTE: All parameters having Min/Max specificatio ns are guar anteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . .+18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Thermal Resistance (Typical) θJA (°C/W)

5 Ld TSOT (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 214

8 Ld DFN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8 Ld MSOP (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . 115

16 Ld QFN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . 44

14 Ld SOIC (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . 82

14 Ld TSSOP (Note 5). . . . . . . . . . . . . . . . . . . . . . . 93

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Junction Temperature Range . . . . . . . . . . -40°C to +125°

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and

result in failures not covered by warranty.

NOTES:

5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

Electrical Specifications VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

VOS Input Offset Voltage VCM = 0V 2 12 mV

TCVOS Average Offset Voltage Drift (Note 7) 5 µV/°C

IBInput Bias Current VCM = 0V 2 50 nA

RIN Input Impedance 1GΩ

CIN Input Capacitance 1.35 pF

CMIR Common-Mode Input Range -5.5 +5.5 V

CMRR Common-Mode Rejection Ratio for VIN from -5.5V to +5.5V 50 70 dB

AVOL Open Loop Gain -4.5V ≤ VOUT ≤ +4.5V 75 95 dB

OUTPUT CHARACTERISTICS

VOL Output Swing Low IL = -5mA -4.92 -4.85 V

VOH Output Swing High IL = 5mA 4.85 4.92 V

ISC Short Circuit Current ±120 mA

IOUT Output Current ±30 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V 60 80 dB

ISSupply Current (Per Amplifier) No load 500 750 µA

DYNAMIC PERFORMANCE

SR Slew Rate (Note 8) -4.0V ≤ VOUT ≤ +4.0V, 20% to 80% 10 V/µs

tSSettling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns

BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz

GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz

PM Phase Margin RL = 10kΩ, CL = 10pF 50 °

CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB

NOTES:

7. Measured over operating temperature range.

8. Slew rate is measured on rising and falling edges.

EL5120, EL5220, EL5420

5FN7186.7

December 15, 2011

Electrical Specifications VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

VOS Input Offset Voltage VCM = 2.5V 2 10 mV

TCVOS Average Offset Voltage Drift (Note 9) 5 µV/°C

IBInput Bias Current VCM = 2.5V 2 50 nA

RIN Input Impedance 1GΩ

CIN Input Capacitance 1.35 pF

CMIR Common-Mode Input Range -0.5 +5.5 V

CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +5.5V 45 66 dB

AVOL Open Loop Gain 0.5V ≤ VOUT ≤+ 4.5V 75 95 dB

OUTPUT CHARACTERISTICS

VOL Output Swing Low IL = -5mA 80 150 mV

VOH Output Swing High IL = +5mA 4.85 4.92 V

ISC Short Circuit Current ±120 mA

IOUT Output Current ±30 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 80 dB

ISSupply Current (Per Amplifier) No load 500 750 µA

DYNAMIC PERFORMANCE

SR Slew Rate (Note 10) 1V ≤ VOUT ≤ 4V, 20% to 80% 10 V/µs

tSSettling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns

BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz

GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz

PM Phase Margin RL = 10kΩ, CL = 10pF 50 °

CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB

NOTES:

9. Measured over operating temperature range.

10. Slew rate is measured on rising and falling edges.

EL5120, EL5220, EL5420

6FN7186.7

December 15, 2011

Electrical Specifications VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = +25°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

VOS Input Offset Voltage VCM = 7.5V 2 14 mV

TCVOS Average Offset Voltage Drift (Note 11) 5 µV/°C

IBInput Bias Current VCM = 7.5V 2 50 nA

RIN Input Impedance 1GΩ

CIN Input Capacitance 1.35 pF

CMIR Common-Mode Input Range -0.5 +15.5 V

CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +15.5V 53 72 dB

AVOL Open Loop Gain 0.5V ≤ VOUT ≤ 14.5V 75 95 dB

OUTPUT CHARACTERISTICS

VOL Output Swing Low IL = -5mA 80 150 mV

VOH Output Swing High IL = +5mA 14.85 14.92 V

ISC Short Circuit Current ±120 mA

IOUT Output Current ±30 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 80 dB

ISSupply Current (Per Amplifier) No load 500 750 µA

DYNAMIC PERFORMANCE

SR Slew Rate (Note 12) 1V ≤ VOUT ≤ 14V, 20% to 80% 10 V/µs

tSSettling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns

BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz

GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz

PM Phase Margin RL = 10kΩ, CL = 10pF 50 °

CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB

NOTES:

11. Measured over operating temperature range

12. Slew rate is measured on rising and falling edges

EL5120, EL5220, EL5420

7FN7186.7

December 15, 2011

Typical Performance Curves

FIGURE 1. EL5420 INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. EL5420 INPUT OFFSET VOLTAGE DRIFT

FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE

FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE

400

1200

QUANTITY (AMPLIFIERS)

INPUT OFFSET VOLTAGE (mV)

-12

1800

1600

800

200

1400

1000

600

-10

-8

-6

-4

-2

-0

VS = ±5V

TA = +25°C TYPICAL

PRODUCTION

DISTRIBUTION

INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)

QUANTITY (AMPLIFIERS)

VS = ±5V TYPICAL

PRODUCTION

DISTRIBUTION

0150

INPUT OFFSET VOLTAGE (mV)

TEMPERATURE (°C)

-5

50-50 100

10 VS = ±5V

0.0

INPUT BIAS CURRENT (nA)

TEMPERATUR E (°C)

-2.0

2.0

0 15050-50 100

VS = ±5V

4.94

4.95

OUTPUT HIGH VOLTAGE (V)

4.93

4.97

0 150

TEMPERATURE (°C)

50-50 100

4.96

VS = ±5V

IOUT = 5mA

-4.95

-4.93

OUTPUT LOW VOLTAGE (V)

-4.97

-4.91

0 150

TEMPERATURE (°C)

50-50 100

-4.92

-4.94

-4.96

VS = ±5V

IOUT = -5mA

EL5120, EL5220, EL5420

8FN7186.7

December 15, 2011

FIGURE 7. OPEN LOOP GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE

FIGURE 9. EL5420 SUPPLY CURRENT PER AMPLIFIER vs

TEMPERATURE FIGURE 10. EL5420 SUPPLY CURRENT PER AMPLIFIER vs

SUPPLY VOLTAGE

FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL

Typical Performance Curves (Continued)

OPEN LOOP GAIN (dB)

100

0150

TEMPERATURE (°C)

50-50 100

VS = ±5V

RL = 10kΩ

0 150

10.30

10.35

SLEW RATE (V/µs)

TEMPERATUR E (°C)

10.25

50-50 100

10.40 VS = ±5V

0.5

0.55

SUPPLY CURRENT (mA)

0.45

0 150

TEMPERATURE (°C)

50-50 100

VS = ±5V

520

400

600

SUPPLY CURRENT (µA)

SUPPLY VOLTAGE (V)

300 100

700

500

TA = +25°C

10 10k 100M

200

FREQUENCY (Hz)

-50

GAIN (dB)

PHASE (°)

-130

-230

100 1k 100k 1M 10M

150

100

-30

-80

-180

VS = ±5V, TA = +25°C

RL = 10kΩ to GND

CL = 12pF to GND

PHASE

GAIN

1M 100M

-5

MAGNITUDE (NORMALIZED) (dB)

FREQUENCY (Hz)

-15 10M

100k

-10 CL = 10pF

AV = 1

VS = ±5V

10kΩ

1kΩ

560Ω

150Ω

EL5120, EL5220, EL5420

9FN7186.7

December 15, 2011

FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CLFIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs

FREQUENCY

FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY FIGURE 16. CMRR vs FREQUENCY

FIGURE 17. PSRR vs FREQUENCY FIGURE 18. INPUT VOL TAGE NOISE SPECTRAL DENSITY vs

FREQUENCY

Typical Performance Curves (Continued)

1M 100M

FREQUENCY (Hz)

10M

100k

MAGNITUDE (NORMALIZED) (dB)

-30

-20

-10

RL = 10kΩ

AV = 1

VS = ±5V

12pF

50pF

100pF

1000pF

OUTPUT IMPEDANCE (Ω)

FREQUENCY (Hz)

10k 100k

120

200

160

10M

AV = 1

VS = ±5V

TA = +25°C

MAXIMUM OUTPUT SWING (VP-P)

FREQUENCY (Hz)

10k 100k

10M

VS = ±5V

TA = +25°C

AV = 1

RL = 10kΩ

CL = 12pF

Distortion <1%

100

CMRR (dB)

FREQUENCY (Hz)

1M 10M

10k 100k

VS = ±5V

TA = +25°C

100

PSRR (dB)

FREQUENCY (Hz)

1M 10M

10k 100k

VS = ±5V

TA = +25°C

PSRR+

PSRR-

100 100k 100M

100

VOLTAGE NOISE (nV/√Hz)

FREQUENCY (Hz)

110M1k 10k 1M

600

EL5120, EL5220, EL5420

10 FN7186.7

December 15, 2011

FIGURE 19. TOTAL HARMONIC DIST ORTION + NOISE vs

FREQUENCY FIGURE 20. CHANNEL SEP ARA TION vs FREQUENCY

RESPONSE

FIGURE 21. SMALL SIGNAL OVERSHOOT vs LOAD

CAPACITANCE FIGURE 22. SETTLING TIME vs STEP SIZE

FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE

Typical Performance Curves (Continued)

1k 10k 100k

0.005

0.008

FREQUENCY (Hz)

THD+ N (%)

0.010

0.001

0.003 VS = ±5V

RL = 10kΩ

AV = 1

VIN = 1VRMS

0.006

0.009

0.007

0.004

0.002

-60

X-TALK (dB)

FREQUENCY (Hz)

-140

-120

-100

-80

1M 6M10k 100k

VS = ±5V

RL = 10kΩ

AV = 1

VIN = 220mVRMS

DUAL MEASURED CHANNEL A TO B

QUAD MEASURED CHANNEL A TO D

OR B TO C

OTHER COMBINATION S YIELD

IMPROVED REJECTION

10 100 1k

LOAD CAPACITANCE (pF)

OVERSHOOT (%)

VS = ±5V

AV = 1

RL = 10kΩ

VIN = ±50mV

TA = +25°C

800

-2

STEP SIZE (V)

SETTLING TIME (ns)

6000

200 400

-3

-1

-4

VS = ±5V

AV = 1

RL = 10kΩ

CL = 12pF

TA = +25°C

0.1%

VS = ±5V

TA = +25°C

AV = 1

RL = 10kΩ

CL = 12pF

1V 1µs

VS = ±5V

TA = +25°C

AV = 1

RL = 10kΩ

CL = 12pF

50mV 200ns

EL5120, EL5220, EL5420

11 FN7186.7

December 15, 2011

Pin Descriptions

EL5120 EL5220 EL5420

PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT

5 LD

TSOT 8 LD MSOP,

8 LD DFN 14 LD TSSOP,

14 LD SOIC 16 LD

QFN

13, 16 NC No Connect

IN+ Amplifier Non-Inverting Input (Reference Circuit 1)

IN- Amplifier Inverting Input (Reference Circuit 1)

OUT Amplifier Output (Reference Circuit 2)

3 VIN+ Amplifier Non-Inverting Input (Reference Circuit 1)

4 VIN- Amplifier Inverting Input (Reference Circuit 1)

1 VOUT Amplifier Output (Reference Circuit 2)

1 1 15 VOUTA Amplifier A Output (Reference Circuit 2)

2 2 1 VINA- Amplifier A Inverting Input (Reference Circuit 1)

3 3 2 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 1)

5 8 4 3 VS+ Positive Power Supply

5 5 4 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 1)

6 6 5 VINB- Amplifier B Inverting Input (Reference Circuit 1)

7 7 6 VOUTB Amplifier B Output (Reference Circuit 2)

8 7 VOUTC Amplifier C Output (Reference Circuit 2)

9 8 VINC- Amplifier C Inverting Input (Reference Circuit 1)

10 9 VINC+ Amplifier C Non-Inverting Input (Reference Circuit 1)

2 4 11 10 VS- Negative Power Supply

12 11 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 1)

13 12 VIND- Amplifier D Inverting Input (Reference Circuit 1)

14 14 VOUTD Amplifier D Output (Reference Circuit 2)

VS+

VS-

VS+

GND VS-

CIRCUIT 1 CIRCUIT 2

EL5120, EL5220, EL5420

12 FN7186.7

December 15, 2011

Applications Information

Product Descr iption

The EL5120, EL5220, and EL5420 voltage feedback

amplifiers are fabricated using a high voltage CMOS

process. They exhibit rail-to-rail input and output capability,

they are unity gain stable, and have low power consumption

(500µA per amplifier). These features make the EL5120,

EL5220, and EL5420 ideal for a wide range of general-

purpose applications. Connected in voltage follower mode

and driving a load of 10kΩ and 12pF, the EL5120, EL5220,

and EL5420 have a -3dB bandwidth of 12MHz while

maint a i nin g a 1 0V/µs slew rate. The EL5120 is a single

amplifier , the EL5220 is a dual amplifier , and the EL5420 is a

quad amplifier.

Operating Voltage, Input, and Output

The EL5120, EL5220, and EL5420 are specified with a

single nominal supply voltage from 5V to 15V or a split

supply with its total range from 5V to 15V. Correct operation

is guaranteed for a supply range of 4.5V to 16.5V. Most

EL5120, EL5220, and EL5420 specifications are stable over

both the full supply range and operating junction

temperature range of -40°C to +125°C. Parameter variations

with operating voltage and/or temperature are shown in the

typical performance curves.

The input common-mode voltage range of the EL5120,

EL5220, and EL5420 extends 500mV beyond the supply

rails. The output swings of the EL5120, EL5220, and

EL5420 typically extend to within 80mV of po sitive and

negative supply rails with load currents of 5mA. Decreasing

load currents will extend the output voltage range even

closer to the supply rails. Figure 25 shows the input and

output waveforms for the device in the unity-gain

configuration. Operation is from ±5V supply with a 10kΩ load

connected to GND. The input is a 10VP-P sinusoid. The

output voltage is approximately 9.985VP-P.

FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND

OUTPUT

Short Circuit Current Limit

The EL5120, EL5220, and EL5420 will limit the short circuit

current to ±120mA if the output is directly shorted to the

positive or the negative supply. If an output is shorted

indefinitely, the power dissipation could easily increase such

that the device may be damaged. Maximum reliability is

maintained if the output continuous current never exceeds

±30mA. This limit is set by the design of the internal metal

interconnects.

Output Phase Reversal

The EL5120, EL5220, and EL5420 are immune to phase

reversal as long as the input voltage is limited from (VS-)

-0.5V to (VS+) +0.5V. Figure 26 shows a photo of the output

of the device with the input voltage driven beyond the supply

rails. Although the device's output will not change phase, the

input's overvoltage should be avoided. If an input voltage

exceeds supply voltage by more than 0.6V, electrostatic

protection diodes placed in the input stage of the device

begin to conduct and overvoltage damage coul d occur.

FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT

Power Dissipation

With the high-output drive capability of the EL5120, EL5220,

and EL5420 amplifiers, it is possible to exceed the +125°C

maximum operating junction temperature under certain load

current conditions. Therefore, it is important to calculate the

maximum junction temperature for the application to

determine if load conditions need to be modified for the

amplifier to remain in the safe operating area.

The maximum power dissipation allowed in a package is

determined according to Equation 1:

where:

•T

JMAX = Maximum junction temperature

•T

AMAX = Maximum ambient temper at ure

•θJA = Thermal resistance of the package

•P

DMAX = Maximum power dissipation in the package

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

VS = ±5V

TA = +25°C

AV = 1

VIN = 10VP-P

OUTPUT INPUT

VS = ±2.5V

TA = +25°C

AV = 1

VIN = 6VP-P

1V 100µs

PDMAX TJMAX TAMAX

–

ΘJA

---------------------------------------------

=(EQ. 1)

EL5120, EL5220, EL5420

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7186.7

December 15, 2011

supply voltage, plus the power in the IC due to the loads as

shown in Equation 2:

when sourcing, and:

when sinking.

where:

• i = 1 to 2 for dual and 1 to 4 for quad

•V

S = Total supply voltage

•I

SMAX = Maximum supply current per amplifier

•V

OUTi = Maximum output vo ltage of the appl ication

•I

LOADi = Load current

If we set the two PDMAX equations equal to each o ther, we

can solve for RLOADi to avoid device overheat. Fig ure 27

provide a convenient way to see if the device will overheat.

The maximum safe power dissipatio n can be found

graphically, based on the package type and the ambie nt

temperature. By using the previous equation, it is a simple

matter to see if PDMAX exceeds the device's power de rati ng

curves. To ensure prop er operation, it is important to observe

the recommended derating curves in Figu re 27.

Unused Amplifiers

It is recommended that any unused amplifiers in a dual and

a quad package be configured as a unity gain follower. The

inverting input should be directly connected to the output

and the non-inverting input tied to the ground plane.

Driving Capacitive Loads

The EL5120, EL5220, and EL5420 can drive a wide range of

capacitive loads. As load capacitance increases, however,

the -3dB bandwidth of the device will decrease and the

peaking will increase. The ampli fiers drive 10pF loads in

parallel with 10kΩ with just 1.5dB of peaking, and 100pF

with 6.4dB of peaking. If less peaking is desired in these

applications, a small series resistor (usually between 5Ω and

50Ω) can be placed in series with the output. However, this

will obviously reduce the gain sligh tl y. Another method of

reducing peaking is to add a “snubber” circuit at the output.

A snubber is a shunt load consisting of a resistor in series

with a capacitor. Values of 150Ω and 10nF are typical. The

advantage of a snubber is that it does not draw any DC load

current or reduce the gain

Power Supply Bypassing and Printed Circuit

Board Layout

The EL5120, EL5220, and EL5420 can provide gain at high

frequency. As with any high-frequency device, go od printed

circuit board layout is necessary for optimum performance.

Ground plane construction is highly recommended, lead

lengths should be as short as possible and the power supply

pins must be well bypassed to reduce the risk of oscillation.

For normal single supply operation, where the VS- pin is

connected to ground, a 0.1µF ce ramic capacitor should be

placed from VS+ to pin to VS- pin. A 4.7µF tantalum

capacitor should then be connected in parallel, placed in the

region of the amplifier . One 4.7µF cap acitor may be used for

multiple devices. This same capacitor combination should be

placed at each supply pin to ground if split supplies are to be

used.

PDMAX ΣiV

SISMAX VS+(VOUTi)ILOADi×–+×[]×=(EQ. 2)

PDMAX ΣiV

SISMAX VOUTi(VS-)ILOADi×–+×[]×=(EQ. 3)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 25 50 75 100 125 150

FIGURE 27. P ACKAGE POWER DISSIP ATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

POWER DISSIPATION (W)

AMBIENT TEMPERAT URE (°C)

θJA = 44°C/W

QFN16

2.27W θJA = 55°C/W

DFN8

1.80W

1.22W

θJA = 82°C/W

SOIC14

467mW

870mW θJA = 115°C/W

MSOP8

θJA = 93°C/W

TSSOP14

θJA = 214°C/W

TSOT5

EL5120, EL5220, EL5420

14 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

Package Outline Drawing

L8.2x3

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 3/10

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.25mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

Compies to JEDEC MO-229 VCED-2.

(4X) 0.15

INDEX AREA

PIN 1

PIN #1

SEATING PLAN E

BASE PLANE

0.08

SEE DETAIL "X"

0.90 ±0.10

0.05 MAX

0.20 REF

2.00

3.00

2X 1.50

8X 0.40 ±0.10 8X 0.25 +0.07/-0.05

INDEX AREA

6X 0.50

(1.65)

(1.50)

(8X 0.60)

(8X 0.25)

(1.80)

(2.80)

(6X 0.50)

0.10 AMC B

0.10 C

1.80 +0.10/-0.15

1.65 +0.10/-0.15

15 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4¬¨¬®Ð

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45¬

SEE DETAIL ‚Äö

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side ar e not included.

2. Plastic interlead protrusions of 0 .010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

16 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

Mini SO Package Family (MSOP)

1(N/2)

(N/2)+1

PLANE

SEATING

N LEADS

0.10 C

PIN #1

I.D.

E1E

DETAIL X

3¬¨¬®Ð

GAUGE

PLANE

SEE DETAIL "X"

0.25

A1 L

0.25 C A B

0.08 C A B

MDP0043

MINI SO PACKAGE FAMILY

SYMBOL

MILLIMETERS

TOLERANCE NOTESMSOP8 MSOP10

A1.101.10 Max. -

A1 0.10 0.10 ±0.05 -

A2 0.86 0.86 ±0.09 -

b 0.33 0.23 +0.07/-0.08 -

c0.180.18 ±0.05 -

D 3.00 3.00 ±0.10 1, 3

E4.904.90 ±0.15 -

E1 3.00 3.00 ±0.10 2, 3

e0.650.50 Basic -

L0.550.55 ±0.15 -

L1 0.95 0.95 Basic -

N 8 10 Reference -

Rev. D 2/07

NOTES:

1. Plastic or metal protrusions of 0.15mm maximum per side are not

included.

2. Plastic interlead protrusions of 0.25mm maximum per side are

not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

17 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

Thin Shrink Small Outline Package Family (TSSOP)

N(N/2)+1

(N/2)

TOP VIEW

0.20 C

2X B A

N/2 LEAD TIPS

0.25 CAB

PIN #1 I.D.

0.05

0.10 C

N LEADS SIDE VIEW

0.10 CABM

SEE DETAIL ‚Äö

END VIEW

DETAIL X

0¬¨¬®Ðê

GAUGE

PLANE

0.25

SEATING

PLANE

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL

MILLIMETERS

TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. F 2/07

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm per

side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

18 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

QFN (Quad Flat No-Lead) Package Family

PIN #1

I.D. MARK

(N-2)

(N-1)

(N/2)

0.075

TOP VI EW

(N/2)

PIN #1 I.D.

(N-2)

(N-1)

N LEADS

BOTTOM VIEW

DETAIL X

PLANE

SEATING

N LEADS

SEE DETAIL "X"

A1 (L)

N LEADS

& EXPOSED PAD

0.10

SIDE VIEW

0.10 BA

0.075 C

(E2)

(D2)

0.08 C

(c)

MDP0046

QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY

(COMPLIANT TO JEDEC MO-220)

SYMBOL

MILLIMETERS

TOLERANCE NOTESQFN44 QFN3 QFN32

A 0.90 0.90 0.90 0.90 ±0.10 -

A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -

b 0.25 0.25 0.23 0.22 ±0.02 -

c 0.20 0.20 0.20 0.20 Reference -

D 7.00 5.00 8.00 5.00 Basic -

D2 5.10 3.80 5.80 3.60/2.48 Reference 8

E 7.00 7.00 8.00 6.00 Basic -

E2 5.10 5.80 5.80 4.60/3.40 Reference 8

e 0.50 0.50 0.80 0.50 Basic -

L 0.55 0.40 0.53 0.50 ±0.05 -

N 44 38 32 32 Reference 4

ND 11 7 8 7 Reference 6

NE 11 12 8 9 Reference 5

SYMBOL

MILLIMETERS TOLER-

ANCE NOTESQFN28 QFN2 QFN20 QFN16

A 0.90 0.90 0.90 0.90 0.90 ±0.10 -

A1 0.02 0.02 0.02 0.02 0.02 +0.03/

-0.02 -

b 0.25 0.25 0.30 0.25 0.33 ±0.02 -

c 0.20 0.20 0.20 0.20 0.20 Reference -

D 4.00 4.00 5.00 4.00 4.00 Basic -

D2 2.65 2.80 3.70 2.70 2.40 Reference -

E 5.00 5.00 5.00 4.00 4.00 Basic -

E2 3.65 3.80 3.70 2.70 2.40 Reference -

e 0.50 0.50 0.65 0.50 0.65 Basic -

L 0.40 0.40 0.40 0.40 0.60 ±0.05 -

N 28 24 20 20 16 Reference 4

ND 6 5 5 5 4 Reference 6

NE 8 7 5 5 4 Reference 5

Rev 11 2/07

NOTES:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Tiebar view shown is a non-functional feature.

3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.

4. N is the total number of terminals on the device.

5. NE is the number of terminals on the “E” side of the package

(or Y-direction).

6. ND is the number of terminals on the “D” side of the package

(or X-direction). ND = (N/2)-NE.

7. Inward end of terminal may be square or circular in shape with radius

(b/2) as shown.

8. If two values are listed, multiple exposed pad options are available.

Refer to device-specific datasheet.

19 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

TSOT Package Family

(N/2)21

0.15 DC

2X 0.25 C

2X N/2 TIPS

Bddd MDC A-B

2 3

SEATING

PLANE

0.10 C

1 3

0.15 A-BC

(L1)

0.25

4¬¨¬®Ð

GAUGE

PLANE

MDP0049

TSOT PACKAGE FAMILY

SYMBOL

MILLIMETERS

TOLERANCETSOT5 TSOT6 TSOT8

A 1.00 1.00 1.00 Max

A1 0.05 0.05 0.05 ±0.05

A2 0.87 0.87 0.87 ±0.03

b 0.38 0.38 0.29 ±0.07

c 0.127 0.127 0.127 +0.07/-0.007

D 2.90 2.90 2.90 Basic

E 2.80 2.80 2.80 Basic

E1 1.60 1.60 1.60 Basic

e 0.95 0.95 0.65 Basic

e1 1.90 1.90 1.95 Basic

L 0.40 0.40 0.40 ±0.10

L1 0.60 0.60 0.60 Reference

ddd 0.20 0.20 0.13 -

N 5 6 8 Reference

Rev. B 2/07

NOTES:

1. Plastic or metal protrusions of 0.15mm maximum per side are

not included.

2. Plastic interlead protrusions of 0.15mm maximum per side are

not included.

3. This dimension is measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(TSOT6 AND TSOT8 only).

6. TSOT5 version has no center lead (shown as a dashed line).

20 FN7186.7

December 15, 2011

EL5120, EL5220, EL5420

Package Outline Drawing

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

PLANE

SEATING

0.10 C0.10 CBA

PIN #1

I.D. MARK

5.00 ±0.10

4.40 ±0.10

0.25 +0.05/-0.06

6.40

0.20 C B A

0.05

0°-8°

GAUGE

PLANE

SEE

0.90 +0.1 5/ - 0.10

0.60 ±0. 15

0.09-0.20

1.00 REF

0.65

1.20 MAX

0.25

0.05 MIN

0.15 MAX

(1.45)

(5.65)

(0.65 T YP) (0.35 TYP)

DETAIL "X"

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.80mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead is 0.07mm.

6. Dimension in ( ) are for reference only.

7. Conforms to JEDEC MO-153, variation AB-1.

NOTES:

END VIEW