LTC4370
1
4370f
Typical applicaTion
FeaTures DescripTion
Two-Supply Diode-OR
Current Balancing Controller
The LTC
®
4370 is a two-supply current sharing controller
which incorporates MOSFET ideal diodes. The diodes
block reverse and shoot-through currents during start-up
and fault conditions. Their forward voltage is adjusted to
share the load currents between supplies. Unlike other
sharing methods, neither a share bus nor trim pins on
the supply are required.
The maximum MOSFET voltage drop can be set with a
resistor. A fast gate turn-on reduces the load voltage
droop during supply switchover. If the input supply fails
or is shorted, a fast turn-off minimizes reverse current
transients.
The controller operates with supplies from 2.9V to 18V.
For lower rail voltages, an external supply is needed at
the VCC pin. Enable inputs can be used to turn off the
MOSFET and put the controller in a low current state.
Status outputs indicate whether the MOSFETs are on or
off. The load sharing function can be disabled to turn the
LTC4370 into a dual ideal diode controller.
12V, 10A Load Share Current Sharing Error vs Supply Difference
applicaTions
n Shares Load Between Two Supplies
n Eliminates Need for Active Control of
Input Supplies
n No Share Bus Required
n Blocks Reverse Current
n No Shoot-Through Current During Start-Up or Faults
n 0V to 18V High Side Operation
n Enable Inputs
n MOSFET On Status Outputs
n Dual Ideal Diode Mode
n 16-Lead DFN (4mm × 3mm) and MSOP Packages
n Redundant Power Supplies
n High Availability Systems and Servers
n Telecom and Network Infrastructure
L, LT, LTC , LT M, Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 7920013 and
8022679. Additional patent pending.
SUM85N03-06P
*OPTIONAL, FOR FAST TURN-ON
SUM85N03-06P
GATE1CPO1
CPO2
GND
EN1
EN2
RANGE
4370 TA01
VINA
12V
VINB
12V
0.1µF
NC
OUT
12V, 10A
39nF*
39nF*
VIN1
VCC FETON1
COMP
FETON2
OUT1
OUT2
GATE2
VIN2
LTC4370
2mΩ
2mΩ
0.18µF
VINA – VINB (mV)
–750
–20
SHARING ERROR (IVINA – IVINB)/IL (%)
–10
0
10
–500 –250 2500 500
20
–15
–5
5
15
750
4370 TA01b
LTC4370
2
4370f
absoluTe MaxiMuM raTings
VIN1, VIN2, OUT1, OUT2 Voltages ...................−2V to 24V
VCC Voltage ............................................... −0.3V to 6.5V
GATE1, GATE2 Voltages (Note 3) ............... −0.3V to 34V
CPO1, CPO2 Voltages (Note 3) ................... −0.3V to 34V
RANGE Voltage ................................−0.3V to VCC + 0.3V
COMP Voltage .............................................. −0.3V to 3V
EN1, EN2, FETON1, FETON2 Voltages .........−0.3V to 24V
CPO1, CPO2 Average Current .................................10mA
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
1
2
3
4
5
6
7
8
EN1
GND
VCC
VIN1
GATE1
CPO1
OUT1
FETON1
EN2
RANGE
COMP
VIN2
GATE2
CPO2
OUT2
FETON2
TOP VIEW
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 17) PCB GND CONNECTION IS OPTIONAL
1
2
3
4
5
6
7
8
EN2
RANGE
COMP
VIN2
GATE2
CPO2
OUT2
FETON2
16
15
14
13
12
11
10
9
EN1
GND
VCC
VIN1
GATE1
CPO1
OUT1
FETON1
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 125°C/W
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4370CDE#PBF LTC4370CDE#TRPBF 4370 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC4370IDE#PBF LTC4370IDE#TRPBF 4370 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC4370CMS#PBF LTC4370CMS#TRPBF 4370 16-Lead Plastic MSOP 0°C to 70°C
LTC4370IMS#PBF LTC4370IMS#TRPBF 4370 16-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
FETON1, FETON2 Currents .......................................5mA
Operating Ambient Temperature Range
LTC4370C ................................................ 0°C to 70°C
LTC4370I .............................................−40°C to 85°C
Storage Temperature Range .................. −65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package ......................................................300°C
LTC4370
3
4370f
elecTrical characTerisTics
The l denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, OUT = VIN, VCC open, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
VIN VIN1, VIN2 Operating Range
With External VCC Supply
l
l
2.9
0
18
VCC
V
V
VCC(EXT) VCC External Supply Operating Range VIN1, VIN2 ≤ VCC l2.9 6 V
VCC(REG) VCC Regulated Voltage l4.5 5 5.5 V
IIN VIN1, VIN2 Current
Enabled, Higher Supply
Enabled, Lower Supply
Pull-Up
Disabled
Other VIN = 11.7V, Both EN = 0V
Other VIN = 12.3V, Both EN = 0V
Both VIN = 0V, VCC = 5V, Both EN = 0V
Both EN = 1V
l
l
l
l
2.1
320
–110
80
3
450
–180
180
mA
µA
µA
µA
ICC VCC Current
Enabled
Disabled
VCC = 5V, Both VIN = 1.2V, Both EN = 0V
VCC = 5V, Both VIN = 1.2V, Both EN = 1V
l
l
2
105
2.8
220
mA
µA
VCC(UVLO) VCC Undervoltage Lockout Threshold VCC Rising l2.3 2.55 2.7 V
ΔVCC(HYST) VCC Undervoltage Lockout Hysteresis l40 120 300 mV
Load Share
VEA(OS) Error Amplifier Input Offset l0 ±2 mV
gm(EA) Error Amplifier Gain (–ΔICOMP /ΔVOUT) 150 µS
VFR(MIN) Minimum Forward Regulation Voltage
(VIN – OUT)
VIN = 1.2V, VCC = 5V
VIN = 12V
l
l
2
2
12
25
25
50
mV
mV
VFR(MAX) Maximum Forward Regulation Voltage
(VIN – OUT)
RRANGE = 4.99k, VIN = 1.2V, VCC = 5V
RRANGE = 4.99k, VIN = 12V
RRANGE = 49.9k, VIN = 1.2V, VCC = 5V
RRANGE = 49.9k, VIN = 12V
l
l
l
l
40
45
425
440
62
75
511
524
82
100
575
590
mV
mV
mV
mV
IRANGE RANGE Pull-Up Current RANGE = 0.2V l–8.8 –10 –11.2 µA
VRANGE(TH) RANGE Load Share Disable Threshold lVCC – 0.5 VCC – 0.3 VCC – 0.1 V
Gate Drive
ΔVGATE MOSFET Gate Drive (GATE – VIN) VFWD = 0.2V; I = 0, −1μA; Highest VIN = 12V
VFWD = 0.2V; I = 0, −1μA; Highest VIN = 2.9V
l
l
10
4.5
12
7
14
9
V
V
tON(GATE) GATE1, GATE2 Turn-On Propagation Delay VFWD (= VIN – OUT) Step: –0.3V 0.3V l0.4 1 µs
tOFF(GATE) GATE1, GATE2 Turn-Off Propagation Delay VFWD Step: 0.3V –0.3V l0.4 1 µs
IGATE(PK) GATE1, GATE2 Peak Pull-Up Current
GATE1, GATE2 Peak Pull-Down Current
VFWD = 0.4V, ΔVGATE = 0V, CPO = 17V
VFWD = −2V, ΔVGATE = 5V
l
l
–0.9
0.9
–1.4
1.4
–1.9
1.9
A
A
IGATE(OFF) GATE1, GATE2 Off Pull-Down Current Corresponding EN = 1V, ΔVGATE = 2.5V l65 110 160 µA
Input/Output Pins
VEN(TH) EN1, EN2 Threshold Voltage EN Falling l580 600 620 mV
ΔVEN(TH) EN1, EN2 Threshold Hysteresis l2 8 20 mV
IEN EN1, EN2 Current At 0.6V l0 ±1 µA
IOUT OUT1, OUT2 Current
Enabled
Disabled
OUT
n
= 0V, 12V; Both EN = 0V
Both EN = 1V
l
l
–70
16
260
40
µA
µA
ICPO(UP) CPO1, CPO2 Pull-Up Current CPO = VIN l–40 –70 –115 µA
VOL FETON1, FETON2 Output Low Voltage I = 1mA
I = 3mA
l
l
0.12
0.36
0.4
1.2
V
V
VOH FETON1, FETON2 Output High Voltage I = −1μA, VFWD = 1V lVCC – 1.4 VCC – 0.9 VCC – 0.5 V
LTC4370
4
4370f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IFETON FETON1, FETON2 Leakage Current At 12V l0 ±1 µA
ΔVGATE(ON) MOSFET On Detect Threshold
(GATE – VIN)
FETON Transitions High l0.28 0.7 1.1 V
Typical perForMance characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
elecTrical characTerisTics
TA = 25°C, VIN1 = VIN2 = 12V, OUT = VIN, VCC open,
unless otherwise noted.
Note 3: Internal clamps limit the GATE and CPO pins to a minimum of 10V
above, and a diode below the corresponding VIN pin. Driving these pins to
voltages beyond the clamp may damage the device.
VIN Current vs Voltage
OUT Current vs Voltage
VIN Current vs Voltage with
External VCC VCC Current vs Voltage
Minimum Forward Regulation
Voltage vs VIN Voltage with
External VCC
VIN (V)
0
–0.5
0
1.5
3 6 129 15
3
0.5
2
1
2.5
18
4370 G01
IIN (mA)
OTHER VIN = 0V
OTHER VIN = 12V
VIN (V)
0
–150
IIN (µA)
0
150
250
1 2 43 5
300
–100
50
–50
100
200
6
4370 G02
VCC = 6V
OTHER VIN = 0V
VCC (V)
0
0
1.5
1 2 43 5
0.5
2
1
2.5
6
4370 G03
ICC (mA)
BOTH VIN = 0V
VOUT (V)
0
–50
100
250
3 6 129 15
300
0
150
50
200
18
4370 G04
IOUT (µA)
VIN (V)
0
0
15
30
1 2 43
5
20
10
25
5
4370 G05
VCC = 5V
VFR(MIN) (mV)
VCC = 3.3V
LTC4370
5
4370f
Typical perForMance characTerisTics
Error Amplifier Transfer
Characteristic
FETON Output Low Voltage
vs Current
FETON Output High Voltage
vs Current
�VGATE Voltage vs Current
�VGATE and VCC Voltages
vs VIN Voltage
Maximum Forward Regulation
Voltage vs RANGE Resistor
TA = 25°C, VIN1 = VIN2 = 12V, OUT = VIN, VCC open,
unless otherwise noted.
IGATE (µA)
0
–3
6
–20 –40 –80–60 –100
15
0
9
3
12
–120
4370 G06
VIN = 2.9V
VGATE – VIN (V)
VIN = 18V
4
14
0
6
2
10
12
8
VIN (V)
0 63 9 1512 18
4370 G07
VCC
VGATE – VIN, VCC (V)
∆VGATE
RRANGE (kΩ)
0
0
300
600
20 40 8060
700
100
400
200
500
100
4370 G08
VFR(MAX) (mV)
–30
0
30
–20
10
–10
20
VOUT1 – VOUT2 (mV)
–300
ICOMP (µA)
–200 –100 1000 200 300
4370 G09
IFETON (mA)
0
0
300
600
1 2 43
700
100
400
200
500
5
4370 G10
VOL (mV)
IFETON (µA)
0
0
3
–2 –4 –8–6
5
1
4
2
–10
4370 G11
VOH (V)
LTC4370
6
4370f
COMP: Error Amplifier Compensation. Connect a capacitor
from this pin to GND. The value of this capacitor should be
approximately 10 to 50 times the gate capacitance (CISS)
of the MOSFET switch. Maintain low board leakage on this
pin for best load sharing accuracy. For example, 100nA
of leakage current (equal to 1V across 10MΩ) increases
the error amplifier offset by 0.7mV. Leave this pin open
if only using ideal diode mode.
CPO1, CPO2: Charge Pump Output. Connect a capacitor
from this pin to the corresponding VIN pin. The value of
this capacitor should be approximately 10× the gate ca-
pacitance (CISS) of the MOSFET switch. The charge stored
on this capacitor is used to pull up the gate during a fast
turn-on. Leave this pin open if fast turn-on is not needed.
EN1, EN2: Enable Input. Keep this pin below 0.6V to enable
sharing and diode control on the corresponding supply.
Driving this pin high shuts off the MOSFET gate (current
can still flow through its body diode). The comparator has
a built-in hysteresis of 8mV. Having both EN pins high
lowers the current consumption of the device.
Exposed Pad (DE Package Only): The exposed pad may
be left open or connected to device ground.
FETON1, FETON2: MOSFET Status Output. This pin is
pulled low by an internal switch when GATE is less than
0.7V above VIN to indicate an off MOSFET. Because of this,
it may also signal off if small currents are flowing through
a high-gm MOSFET with a large forward voltage across
it. An internal 500k resistor pulls this pin up to a diode
below VCC. It may be pulled above VCC using an external
pull-up. Tie to GND or leave open if unused.
GATE1, GATE2: MOSFET Gate Drive Output.Connect this
pin to the gate of the external N-channel MOSFET switch.
An internal clamp limits the gate voltage to 12V above,
and a diode below the input supply. During fast turn-on,
a 1.4A pull-up current charges GATE to CPO. During fast
turn-off, a 1.4A pull-down current discharges GATE to VIN.
GND: Device Ground.
OUT1, OUT2: Output Voltage and Current Sense Input.
Connect this pin to the input side of the supply’s current
sense resistor. A Kelvin connection is important for ac-
curate current sharing. The voltage sensed at this pin is
used to control the MOSFET gate.
RANGE: Supply Differential Voltage Load Sharing Range.
Connect a resistor (below 60k) from this pin to GND. A
10μA internal pull-up current source into this resistor
sets the pin voltage VRANGE. The two supplies will typi-
cally share the load current if their voltage difference is
within ±VRANGE. The maximum sharing range is ±0.6V,
obtained by leaving RANGE open. Connecting this pin to
VCC disables load share control and the device behaves
as a dual ideal diode controller.
VCC: Low Voltage Supply. Connect a 0.1μF capacitor from
this pin to ground. For VIN ≥ 2.9V this pin provides decou-
pling for an internal regulator that generates a 5V supply.
For applications where both VIN < 2.9V, also connect an
external supply in the 2.9V to 6V range to this pin.
VIN1, VIN2: Voltage Sense and Supply Input. Connect
this pin to the supply side of the MOSFET. The low volt-
age supply VCC is generated from the higher of VIN1 and
VIN2. The voltage sensed at this pin is used to control the
MOSFET gate.
pin FuncTions
LTC4370
7
4370f
FuncTional DiagraM
4370 BD
CHARGE
PUMP1
f = 3MHz
LDO
CHARGE
PUMP2
f = 3MHz
*DE PACKAGE ONLY
GATE1
OFF
GATE2
OFF
–+
SA1
–
+
–
+
–
+
–
+
11
CPO1
12
GATE1
13
VIN1 VCC
VCC
VCC LOW
VIN1
gm = 150µS
VIN2
VIN1
VFR1
VFR2
VCC
VSUPPLY1
10
9
OUT1
FETON1
500k
CP4
CP2
CP1
CP3
CP5
0.7V
0.6V
0.6V
2.55V
0.3V
COMP
GATE1
OUT1
OUT2
RANGE
CPO2GATE2
17
EXPOSED
PAD*
GND VIN2 OUT2
M1
VSUPPLY2
M2
–+
C1
C2
DISABLE
LOAD SHARE
DISABLE1
DISABLE2
–
+
–
+
–
+
VCC
VIN2 8
FETON2
1
EN2
14 VCC
16
EN1
500k
CP6
0.7V
GATE2
CC
10µA
TO
LOAD
R3
CVCC
Z
R1
R2
SERVO
ADJUST
3
2
6515 4 7
SA2
EA
+
–
+
–
+
–
+
–
+
–
LTC4370
8
4370f
operaTion
The LTC4370 controls N-channel MOSFETs, M1 and M2,
to share the load between two supplies. Error amplifier
EA compares OUT1 to OUT2 and sets the servo com-
mand voltages, VFR1 and VFR2, for servo amplifiers, SA1
and SA2. When enabled, each servo amplifier controls
the gate of the external MOSFET to regulate its forward
voltage drop (VFWD = VIN – OUT) to VFR. The combined
action of EA and SA forces OUT1 to equal OUT2. Having
the power path resistance from OUT1 to the load (R1)
equal that from OUT2 to the load (R2) forces each supply
to source half of the load current.
The lower limit of VFR adjustment is 25mV at higher supply
voltages (reducing to 12mV at lower voltages to conserve
power and voltage drop). The upper limit is VRANGE + 25mV
(or VRANGE + 12mV). VRANGE itself is set by the 10µA pull-
up current source into resistor R3. The servo adjust block
ensures that only the higher supply’s VFR is adjusted up
while the other is pinned to the minimum. Tying RANGE to
VCC (CP5) forces both VFR to the minimum, transforming
the device into a dual ideal diode controller.
The servo amplifier raises the gate voltage to enhance
the MOSFET whenever the load current causes the drop
to exceed VFR. For large output currents the MOSFET
gate is driven fully on and the voltage drop is equal to
IFET • RDS(ON).
In the case of an input supply short-circuit, when the
MOSFET is conducting, a large reverse current starts
flowing from the load towards the input. SA detects this
failure condition as soon as it appears and turns off the
MOSFET by rapidly pulling down its gate.
SA quickly pulls up the gate whenever it senses a large
forward voltage drop. An external capacitor (C1, C2)
between the CPO and VIN pins is needed for fast gate
pull-up. This capacitor is charged up, at device power-up,
by the internal charge-pump. The stored charge is used
for the fast gate pull-up.
The GATE pin sources current from the CPO pin and sinks
current to the VIN and GND pins. Clamps limit the GATE
and CPO voltages to 12V above and a diode below VIN.
Internal switches pull the FETON pins low when the GATE
to VIN voltage is below 0.7V to indicate that the external
MOSFET is off (body diode could still conduct).
LDO is a low dropout regulator that generates a 5V supply
at the VCC pin from the highest VIN input. When supplies
below 2.9V are being shared, an external supply in the
2.9V to 6V range is required at the VCC pin.
VCC and EN pin comparators, CP1 to CP3, control power
passage. The MOSFET is held off whenever the EN pin is
above 0.6V, or the VCC pin is below 2.55V. A high on both
EN pins lowers the current consumption of the device.
LTC4370
9
4370f
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the point
of load. System uptime improves further if these paralleled
supplies also share the load current.
applicaTions inForMaTion
Figure 1. 5V Diode-OR Load Share with Status Light
Current Sharing Characteristic
The LTC4370 load shares the two supplies by dropping
their voltage difference across the MOSFETs in series
with them (see Figure 1). The MOSFET on the lower sup-
ply drops the minimum servo voltage VFR(MIN) (12mV
or 25mV depending on supply voltage levels), while the
other MOSFET drops VFR(MIN) plus the supply voltage
difference. This equalizes both the OUT pin voltages, and
by Ohm’s law the current that flows through the sense
resistors. Figure2a illustrates this. It shows the higher
supply’s MOSFET forward voltage drop, VFWD, increasing
to compensate the supply difference up to ±500mV.
The upper limit of the servo command adjustment is the
minimum servo plus the RANGE pin voltage (500mV in
Figure 2). Hence, when the two supplies differ by a volt-
age equal to VRANGE, the higher supply’s VFWD is pinned
at the maximum servo voltage VFR(MAX). If the supplies
diverge by more than VRANGE, the OUT pin voltages start
Figure 2. Load Sharing Characteristics
4370 F02
(2b) High RDS(ON): Fully-On MOSFET
Drops 125mV at Half Load
–400mV 400mV0
525mV
25mV
MOSFET
FORWARD
DROP
VIN1 – VIN2
VFWD1
VFWD2
0.5IL • RDS(ON) 125mV
100mV + IL • RS
–400mV 400mV0
1
0
NORMALIZED
CURRENT
VIN1 – VIN2
I2I1
I1I2
0.5
SHARING CAPTURE RANGE
±∆VIN(SH)
DRAWING IS NOT TO SCALE!
VFR(MIN)
IL • RDS(ON)
2RS + RDS(ON)
(2a) Low RDS(ON): Can Servo 25mV Minimum
Forward Regulation Voltage at Half Load
–500mV 500mV0
525mV
25mV
MOSFET
FORWARD
DROP
MAXIMUM M2
MOSFET POWER
DISSIPATION
VIN1 – VIN2
VFWD1
VFWD2
VFR(MAX)
VFR(MIN)
IL • RS
–500mV 500mV0
1
0
NORMALIZED
CURRENT
VIN1 – VIN2
I2I1
I1I2
0.5
SHARING CAPTURE RANGE ±∆VIN(SH)
VRANGE = 500mV VRANGE = 500mV
= 2RS
1
SLOPE
= 2RS
1
SLOPE
MAXIMUM M1
MOSFET POWER
DISSIPATION
M2
SUM85N03-06P
D1: RED LED
LN1251C
SHARE
OFF
D1
M1
SUM85N03-06P
C2
39nF
GATE1CPO1
CPO2
GND
EN1
EN2
RANGE
4370 F01
VINA
5V
VINB
5V
CVCC
0.1µF
R3
30.1k
R4
820Ω
C1
39nF
VIN1
VCC
FETON1
COMP
FETON2
OUT1
OUT2
GATE2VIN2
LTC4370
R1
2.5mΩ
R2
2.5mΩ
OUT
10A
CC
0.18µF
LTC4370
10
4370f
diverging, and so too, the supply currents. As the supply
voltages separate, the entire load current is steered to the
higher supply. Now, the servo command across the higher
supply’s MOSFET is folded back from the maximum to
the minimum servo to minimize power dissipated in the
MOSFET. The sharing capture range, ΔVIN(SH), in Figure2a
is ±500mV, set by VRANGE. Figure 2b will be discussed
later in the MOSFET Selection section.
RANGE Pin Configuration
The RANGE pin resistor is decided by the design trade-off
between the sharing capture range and the power dissipated
in the MOSFET. A larger RRANGE increases the capture
range at the expense of enhanced power dissipation and
reduced load voltage. On the other hand, supplies with
tight tolerances can afford a smaller capture range and
therefore cooler operation of the MOSFETs.
As mentioned, the upper limit of the servo command ad-
justment is VRANGE plus the minimum forward regulation
voltage. Since an internal 10μA pull-up current flowing
through the external resistor sets VRANGE:
VFR(MAX) = 10µA • RRANGE + VFR(MIN) (1)
If RRANGE is larger than 60k (including the pin open
state), the internal limit for the first term on the right-
hand side of Equation 1 is 600mV, setting VFR(MAX) to
612mV or 625mV. Note that servo voltages nearing the
MOSFET’s body diode voltage may divert some or all cur-
rent to the diode especially at hot temperatures. This may
either cause FETON to go low if VGS falls below 0.7V, or
loss of sharing control. Also note that an open RANGE pin
biases itself to a voltage greater than 600mV.
Connecting the RANGE pin to VCC disables the load sharing
loop. The servo voltages for both MOSFETs are fixed at the
minimum with no adjustment. The device now behaves
as a dual ideal diode controller. This is handy for testing
purposes. Use the LTC4353 if only a dual ideal diode
controller is needed.
Power Supply Configuration
The LTC4370 can load share high side supplies down to
0V rail voltage. This requires powering the VCC pin with an
early external supply in the 2.9V to 6V range. In this range
of operation VIN should be lower than VCC. If VCC powers
up after VIN, and backfeeding of VCC by the internal 5V LDO
is a concern, then a series resistor (few 100Ω) or Schottky
diode limits device power dissipation and backfeeding of
a low VCC supply when any VIN is high. A 0.1µF bypass
capacitor should also be connected between the VCC and
GND pins, close to the device. Figure 3 illustrates this.
If either VIN operates above 2.9V, then the external supply
at VCC is not needed. The 0.1µF capacitor is still required
for bypassing.
Start of Sharing
When currents are not being shared either because the
load current or one of the supplies is off, the COMP volt-
age is railed towards 0V or 2V depending on the input
signal to the error amplifier and its offset. For example,
applicaTions inForMaTion
Figure 3. Power Supply Configurations
GATE1
4370 F03
0V TO VCC
0V TO VCC
VIN1
VCC
GATE2
VIN2
LTC4370
2.9V TO 6V GATE1
M1
M2
M1
M2
2.9V TO 18V
(0V TO 18V)
0V TO 18V
(2.9V TO 18V)
VIN1
VCC
GATE2
VIN2
LTC4370
CVCC
0.1µF
CVCC
0.1µF
OPTIONAL
OR HERE
LTC4370
11
4370f
in the absence of load current the differential input volt-
age to the error amplifier is zero and the COMP current is
gm(EA) • VEA(OS). Before sharing can start, the COMP
voltage has to slew towards its operating point of 0.7V
(when VIN1 < VIN2) or 1.24V (VIN1 > VIN2). This delay is
determined by the differential input signal to the error
amplifier (which is ΔVOUT = OUT1 – OUT2 = (I1 − I2) • RS),
its gm and the COMP capacitor value. Depending on how
the currents split before converging, the delay can vary
from 1 to 5 times:
CC•ΔVCOMP
gm(EA) •IL•RS
Figure 4a shows the case where a 5.1V VIN1 is turned
on while VIN2 is at 4.9V supplying 10A. Initially, COMP
is railed low to 0.1V since ΔVOUT (−I2 • RS) is negative,
and needs to rise to 1.24V as the final VIN1 is higher than
VIN2. With VIN1 off, ΔVIN is large and negative, causing the
forward regulation voltage of the second supply VFR2 to be
folded back to the minimum VFR(MIN) (travelling from left
to right in Figure 2a). As the ΔVIN magnitude decreases,
VFR2 rises to the maximum VFR(MAX), lowering I2 and the
load voltage. COMP is around 0.7V when VFR2 is being
adjusted. When COMP reaches 1.24V, VFR2 is kept at the
minimum and VFR1 is adjusted appropriately to compensate
for the 0.2V of ΔVIN. The sharing closure is smoother for
the case where VIN1 < VIN2 since COMP only has to slew
to 0.7V to lower VFR2 (Figure 4b).
MOSFET Selection
The LTC4370 drives N-channel MOSFETs to conduct the
load current. The important parameters of the MOSFET
are its maximum drain-source voltage BVDSS, maximum
gate-source voltage VGS(MAX), on-resistance RDS(ON), and
maximum power dissipation PD(MAX).
If an input is connected to ground, the full supply voltage
can appear across the MOSFET. To survive this, the BVDSS
must be higher than the supply voltages. The VGS(MAX)
rating of the MOSFET should exceed 14V since that is the
upper limit of the internal GATE to VIN clamp.
To obtain the maximum sharing capture range, the RDS(ON)
should be low enough for the servo amplifier to regulate the
minimum forward regulation voltage across the MOSFET
while it’s conducting half of the load current. If it cannot,
the gate voltage will be railed high. Hence, the RDS(ON) value
in the MOSFET data sheet should be looked up for 10V or
4.5V gate drive depending on the VIN voltage. Since the
OUT voltages are equal, the breakpoint for exact sharing
in the higher RDS(ON) case is:
ΔVIN(SH) = VFR(MAX) – 0.5IL • RDS(ON) (2)
applicaTions inForMaTion
Figure 4. Start of Sharing at VIN1 Turn-On
(4a) VIN1 > VIN2 (4b) VIN1 < VIN2
CURRENT
5A/DIV
VOLTAGE
2V/DIV
4370 F04a
25ms/DIV
VIN1 = 5.1V
VIN2 = 4.9V
IL = 10A
I2
I1
OUT
COMP
(1V/DIV)
VIN1
CURRENT
5A/DIV
VOLTAGE
2V/DIV
4370 F04b
25ms/DIV
I2
I1
OUT
VIN1
VIN1 = 4.9V
VIN2 = 5.1V
IL = 10A
COMP
(0.5V/DIV)
LTC4370
12
4370f
In Figure 2b, 0.5IL • RDS(ON) is 125mV. The higher RDS(ON)
rails the servo amplifier high as it cannot regulate the 25mV
VFR(MIN) across the lower supply’s MOSFET. Compared
to Figure 2a, the sharing capture range shrinks by 100mV
(125mV – 25mV) to ±400mV. However, the ΔVIN over
which currents are shared partially stays the same at
500mV + IL • RS. Even when not maximizing sharing range,
IL • RDS(ON) should be kept below 75mV for optimum
performance.
The peak power dissipation in the MOSFET occurs when
the entire load current is being sourced by one supply
with the maximum forward regulation voltage dropped
across the MOSFET (as shown in Figure 2a). Therefore,
the PD(MAX) rating of the MOSFET should satisfy:
PD(MAX) ≥ IL • VFR(MAX) (3)
Table 1 provides starting guidelines for the type of
MOSFET package and heat sink required at various levels
of power dissipation. These are typical ranges for a room
temperature ambient with no air flow.
Table 1. Guidelines for MOSFET Power Dissipation
MAXIMUM POWER
DISSIPATED MOSFET PACKAGE HEAT SINK
0.5W to 1W SO-8 PCB
1W to 2W SO-8 With Exposed Pad,
D-Pak (TO-252)
PCB
TO-220 Standing in Free Air
2W to 4W DD-Pak (TO-263), TO-220 PCB
4W to 10W TO-220 Stamping
10W to 20W TO-220 Casting, Extrusion
20W to 50W TO-247, TO-3P Extrusion
Sense Resistor Selection
The sense resistor voltage drop dictates the current sharing
accuracy. Sharing error, due to the error amplifier input
offset, decreases with increasing sense voltage as:
ΔI
IL
=|I1– I2|
IL
=| VEA(OS)|
IL•RS
=2mV
IL•RS
(4)
I1 and I2 are the two supply currents, IL is the load current
(I1 + I2 = IL), RS is the sense resistor value, and VEA(OS)
is the input offset of the internal error amplifier. A 25mV
sense resistor voltage drop with half of the load cur-
rent flowing through it (i.e., IL • RS = 50mV) gives a 4%
sharing error. A larger sense resistance may also be
needed if there is a connector in between the OUT pins
and the load to minimize the effect of its resistance. At
larger sense voltages the accuracy will be limited by the
sense resistor tolerance.
If sharing accuracy requirements can be relaxed, power
dissipated in the sense resistor can be reduced by selecting
a lower resistance. Worst-case power dissipation happens
at full load, i.e., when load current is not being shared.
While reducing the sense resistance, note that the sharing
loop does not close for load currents below VEA(OS)/RS.
The two sense resistors can have different values if the
application does not require the load current to be shared
equally between the supplies. In such a case:
RS1
RS2
=I2
I1
(5)
CPO Capacitor Selection
The recommended value of the capacitor between the CPO
and VIN pins is approximately 10× the input capacitance CISS
of the MOSFET. A larger capacitor takes a correspondingly
longer time to be charged by the internal charge pump. A
smaller capacitor suffers more voltage drop during a fast
gate turn-on event as it shares charge with the MOSFET
gate capacitance.
applicaTions inForMaTion
LTC4370
13
4370f
External CPO Supply
The internal charge pump takes milliseconds to charge
up the CPO capacitor especially during device power-up.
This time can be shortened by connecting an external
supply to the CPO pin. A series resistor is needed to limit
the current into the internal clamp between the CPO and
VIN pins. The CPO supply should also be higher than the
main input supply to meet the gate drive requirements
of the MOSFET. Figure 5 shows such a 3.3V load share
application, where a 12V supply is connected to the CPO
pins through a 1k resistor. The 1k limits the current into
the CPO pin when the VIN pin is grounded. For the 8.7V
of gate drive (12V – 3.3V), logic-level MOSFETs would be
an appropriate choice for M1 and M2.
Loop Stability
The servo amplifier loop is compensated by the gate
capacitance of the N-channel power MOSFET. No further
compensation components are normally required. In the
case when a MOSFET with less than 1nF gate capacitance
is chosen, a 1nF compensation capacitor connected across
the gate and source might be required.
The load sharing control loop is compensated by the
capacitor from the COMP pin to ground. This capacitor
should be at least 50× the input capacitance CISS of the
MOSFET. A larger capacitor improves stability at the ex-
pense of increased sharing closure delay, while a smaller
capacitor can cause the two supply currents to switch back
and forth before settling. The COMP capacitor can be just
10× CISS when a CPO capacitor is omitted, i.e., when fast
gate turn-on is not used (see Figure 6).
Input and Output Capacitance for Pulsed Loads
For pulsed loads, the load current will be shared every cycle
at frequencies below 100Hz. At higher frequencies, each
cycle’s current may not be shared but the time average of
the currents will be. Bypassing capacitance on the inputs
should be provided to minimize glitches and ripple. This
is important since the controller tries to compensate for
the supply voltage differences to achieve load sharing.
Sufficient load capacitance should also be provided to
enhance the DC component of the load current presented
to the load share circuit. It is also important to design
IL • RDS(ON) below 75mV, as mentioned earlier.
With very low duty cycle or very low frequency loads,
the COMP voltage will rail whenever the load current falls
below the sharing threshold of VEA(OS)/RS for hundreds of
milliseconds. At the start of the next load cycle there will
be a sharing closure delay as COMP slews to its operating
point around 0.7V or 1.24V. To avoid this delay, maintain
the load current above VEA(OS)/RS.
Figure 5. 3.3V Load Share with External 12V Supply
Powering CPO for Faster Start-Up and Refresh
GATE1
CPO1
CPO2
4370 F05
VINA
3.3V
VINB
3.3V
12V 1k
1k
TO SENSE
RESISTOR
TO SENSE
RESISTOR
M1
M2
C1
39nF
C2
39nF
VIN1
GATE2VIN2
LTC4370
applicaTions inForMaTion
Figure 6. Current Sharing 12V Supplies
M2
SUM85N03-06P D1: RED LED, LN1251C
NC
NC
D1
M1
SUM85N03-06P
GATE1CPO1
CPO2
GND
EN1
EN2
RANGE
4370 F06
VINA
12V
VINB
12V
OUT
10A
VIN1
VCC
FETON1
COMP
FETON2
OUT1
OUT2
GATE2
VIN2
LTC4370
R1
2.5mΩ
R2
2.5mΩ
CC
0.039µF
CVCC
0.1µF
R3
47.5k
R4
2.7k
LTC4370
14
4370f
Input Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current can cause transients that
exceed the 24V absolute maximum rating of the VIN and
OUT pins. In ORing applications, one surge suppressor
connected from OUT to ground clamps all the inputs. In
the absence of a surge suppressor, an output capacitance
of 10μF is sufficient in most applications to prevent the
transient from exceeding 24V.
12V Design Example
This design example demonstrates the selection of
components in a 12V system with a 10A maximum load
current and ±2% tolerance supplies (Figure 6). That is
followed by the recalculations involved for a similar 5V
system (Figure 1).
First, calculate the RDS(ON) of the MOSFET to achieve
the desired forward drop at full load. Assuming a VFWD
of 50mV:
RDS(ON) ≤
V
FWD
ILOAD
=
50mV
10A =5mΩ
The SUM85N03-06P offers a good solution in a DD-Pak
(TO-263) sized package with a 4.5mΩ RDS(ON), 30V
BVDSS and 20V VGS(MAX). Since 0.5IL • RDS(ON) is 22.5mV,
the servo amplifier will be able to regulate the 25mV mini-
mum forward regulation voltage leading to the maximum
possible sharing range set by VRANGE.
2% of 12V is 240mV. The sharing capture range, ΔVIN(SH),
needs to be about 2× 240mV (±480mV) to work for most
supply voltage differences. A 47.5k R3 sets VRANGE to
475mV. Equation 1 is used to calculate the maximum
forward regulation voltage:
VFR(MAX) = 10µA • 47.5k + 25mV = 500mV
Equation 3 gives the maximum power dissipation in the
MOSFET to be:
PD(MAX) = 10A • 500mV = 5W
Sufficient PCB area with air flow needs to be provided
around the MOSFET drain to keep its junction temperature
below the 175°C maximum.
A 2.5mΩ sense resistor drops 25mV at full load and
yields an error amplifier offset induced sharing error of
2mV/(10A • 2.5mΩ) or 8% (Equation 4). At full load, the
sense resistor dissipates 10A2 • 2.5mΩ or 250mW. Since
a 12V supply is large enough to tolerate a diode drop, fast
gate turn-on is not needed. Hence, the CPO capacitor is
omitted. The input capacitance, CISS, of the MOSFET is
about 3800pF. Since fast turn-on is not used, the COMP
capacitor CC can be just 10× CISS at 0.039µF.
Red LED, D1, turns on when any one of the MOSFETs is
off, indicating a break in sharing. It requires around 3mA
for good luminous intensity. Accounting for a 2V diode
drop and 0.6V VOL, R4 is set to 2.7k.
5V Design Example
For a 5V, 10A system with ±3% tolerance supplies and
fast gate turn-on (Figure 1), the following components
need to be recalculated: R3, C1, C2, CC, and R4. R3 is
set to 30.1k to account for possible supply differences
(2 • 3% • 5V yields ±300mV). C1 and C2 are set to 10×
CISS at 0.039µF. With fast turn-on, CC is selected closer
to 50× CISS at 0.18µF. With the 5V supply, R4 needs to
be 820Ω to allow 3mA into the LED.
applicaTions inForMaTion
LTC4370
15
4370f
PCB Layout Considerations
Kelvin connection of the OUT pins to the sense resis-
tors is important for accurate current sharing. Place the
MOSFET as close as possible to the sense resistor. Keep the
traces to the MOSFET wide and short to minimize resistive
losses. The PCB traces associated with the power path
through the MOSFET should have low resistance. Thermal
management techniques such as sufficient drain cop-
per area or heat sinks should be considered for optimal
MOSFET power dissipation. See Figure 7.
It is also important to put CVCC, the bypass capacitor, as
close as possible between VCC and GND. Place C1 and
C2 near the CPO and VIN pins. The COMP pin may need
a guard ring to maintain low board leakage.
Figure 7. Recommended PCB Layout for M1, M2, CVCC, R1, R2
applicaTions inForMaTion
4370 FO7
MSOP-16
R1
G
S
W
TO
LOAD
CURRENT FLOW
CURRENT FLOW
VIA TO
GROUND
PLANE
DM2
DD-PAK
FROM
SUPPLY
B
G
S
CVCC
W D M1
DD-PAK
FROM
SUPPLY
A
R2
TRACK WIDTH
W: 0.03 PER AMPERE
ON 1oz Cu FOIL
DRAWING IS NOT TO SCALE!
LTC4370
LTC4370
16
4370f
Typical applicaTions
Current Sharing 3.3V Supplies for 20A Output
C2
0.1µF
C1
0.1µF
GATE1CPO1
CPO2
GND
EN1
EN2
RANGE
4370 TA02
VINA
3.3V ±3%
VINB
3.3V ±3%
R3
20k
OUT
20A
VIN1
VCC
FETON1
COMP
FETON2
OUT1
OUT2
GATE2VIN2
LTC4370
R1
2mΩ
R2
2mΩ
CC
0.47µF
CVCC
0.1µF
M2
IRLS3034PBF
M1
IRLS3034PBF
LTC4370
17
4370f
Typical applicaTions
12V Ideal Diode-OR by Tying RANGE to VCC (to Compare Against Load Share).
Use LTC4353 if Load Share Is Not Desired
M2
SUM85N03-06P
M1
SUM85N03-06P
GATE1CPO1
NC
NC
CPO2
VCC
EN1
EN2
GND
4370 TA03
VINA
12V
VINB
12V
OUT
10A
VIN1
RANGE FETON1
COMP NC
FETON2
OUT1
OUT2
GATE2VIN2
LTC4370
CVCC
0.1µF
LTC4370
18
4370f
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ± 0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ± 0.05
0.45 BSC
LTC4370
19
4370f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
MSOP (MS16) 1107 REV Ø
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
0.1016 ± 0.0508
(.004 ± .002)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.280 ± 0.076
(.011 ± .003)
REF
4.90 ± 0.152
(.193 ± .006)
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
LTC4370
20
4370f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012
LT 0512 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC1473/
LTC1473L
Dual PowerPathTM Switch Driver N-Channel, 4.75V to 30V/3.3V to 10V, SSOP-16 Package
LTC1479 PowerPath Controller for Dual Battery Systems Three N-Channel Drivers, 6V to 28V, SSOP-36 Package
LTC4352 Low Voltage Ideal Diode Controller with Monitoring N-Channel, 0V to 18V, UV, OV, MSOP-12 and DFN-12 Packages
LTC4353 Dual Low Voltage Ideal Diode Controller Dual N-Channel, 0V to 18V, MSOP-16 and DFN-16 Packages
LTC4354 Negative Voltage Diode-OR Controller and Monitor Dual N-Channel, −4.5V to −80V, SO-8 and DFN-8 Packages
LTC4355 Positive High Voltage Ideal Diode-OR with Supply and
Fuse Monitors
Dual N-Channel, 9V to 80V, SO-16 and DFN-14 Packages
LTC4357 Positive High Voltage Ideal Diode Controller N-Channel, 9V to 80V, MSOP-8 and DFN-6 Packages
LTC4358 5A Ideal Diode Internal N-Channel, 9V to 26.5V, TSSOP-16 and DFN-14 Packages
LTC4411 2.6A Low Loss Ideal Diode in ThinSOTTM Internal P-Channel, 2.6V to 5.5V, 40μA IQ, SOT-23 Package
LTC4412/
LTC4412HV
Low Loss PowerPath Controller in ThinSOT P-Channel, 2.5V to 28V/36V, 11μA IQ, SOT-23 Package
LTC4413/
LTC4413-1
Dual 2.6A, 2.5V to 5.5V, Ideal Diodes in DFN-10 Dual Internal P-Channel, 2.5V to 5.5V, DFN-10 Package
LTC4414 36V Low Loss PowerPath Controller for Large
P-Channel MOSFETs
P-Channel, 3V to 36V, 30μA IQ, MSOP-8 Package
LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual P-Channel 50mΩ Ideal Diodes, 1.7V to 5.5V, 15mV Forward
Drop, MSOP-16 and DFN-16 Packages
LTC4416/
LTC4416-1
36V Low Loss Dual PowerPath Controller for Large
P-Channel MOSFETs
Dual P-Channel, 3.6V to 36V, 70μA IQ, MSOP-10 Package
1.2V Load Share
SUM85N03-06P
SUM85N03-06P
39nF
GATE1CPO1
CPO2
GND
EN1
EN2
RANGE
4370 TA04
VINA
1.2V
VINB
1.2V
0.1µF
7.5k
5V
OUT
39nF
VIN1
VCC
FETON1
COMP
FETON2
OUT1
OUT2
GATE2VIN2
LTC4370
2mΩ
2mΩ
0.18µF
