TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Low rDS(on) . . . 1.3 Ω Typ
•Avalanche Energy . . . 75 mJ
•Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
•1.5-A Pulsed Current Per Output
•Output Clamp Voltage up to 45 V
•Low Power Consumption
description
The TPIC6273 is a monolithic high-voltage
high-current power logic octal D-type latch with
DMOS transistor outputs designed for use in
systems that require relatively high load power.
The device contains a built-in voltage clamp on the
outputs for inductive transient protection. Power
driver applications include relays, solenoids, and
other medium-current or high-voltage loads.
The TPIC6273 contains eight positive-edge-
triggered D-type flip-flops with a direct clear input.
Each flip-flop features an open-drain power
DMOS transistor output.
When clear (CLR) is high, information at the D
inputs meeting the setup time requirements is
transferred to the DRAIN outputs on the positive-
going edge of the clock pulse. Clock triggering
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When the clock input (CLK)
is at either the high or low level, the D input signal
has no effect at the output. An asynchronous CLR
is provided to turn all eight DMOS-transistor
outputs off.
The TPIC6273 is characterized for operation over
the operating case temperature range of –40°C
to 125°C.
DRAIN1
4
DRAIN2
5
DRAIN3
6
DRAIN4
7
DRAIN5
14
DRAIN6
15
DRAIN7
16
DRAIN8
17
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
D1
D2
DRAIN1
DRAIN2
DRAIN3
DRAIN4
D3
D4
GND
VCC
D8
D7
DRAIN8
DRAIN7
DRAIN6
DRAIN5
D6
D5
CLK
DW OR N PACKAGE
(TOP VIEW)
logic symbol†
R
1
11
CLK C1
CLR
†This symbol is in accordance with ANSI/IEEE Standard 91-1984
and IEC Publication 617-12.
INPUTS OUTPUT
L
H
H
H
FUNCTION TABLE
(each channel)
CLK D
X
↑
↑
L
X
H
L
X
H
L
H
Latched
CLR DRAIN
H = high level, L = low level, X = irrelevant
1D
2
D1 3
D2 8
D3 9
D4 12
D5 13
D6 18
D7 19
D8
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CLK 11
CLR 1
C1
R
1D
D1 2
DRAIN1
4
C1
R
1D
D2 3
DRAIN2
5
C1
R
1D
D3 8
DRAIN3
6
C1
R
1D
9
DRAIN4
7
C1
R
1D
D5 12
DRAIN5
14
C1
R
1D
D6 13
DRAIN6
15
C1
R
1D
D7 18
DRAIN7
16
C1
R
1D
D8 19
DRAIN8
17
D4
10 GND
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
VCC
Input
GND GND
DRAIN
45 V
12 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)†
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 45 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-drain diode anode current 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, IDn, TA = 25°C (see Note 3) 750 mA. . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, IDn, TA = 25°C 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, IDM,TA = 25°C (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, EAS (see Figure 4) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, IAS (see Note 4) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 125°C
POWER RATING
DW 1125 mW 9.0 mW/°C 225 mW
N 1150 mW 9.2 mW/°C 230 mW
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions over recommended operating temperature range (unless
otherwise noted)
MIN MAX UNIT
Logic supply voltage, VCC 4.5 5.5 V
High-level input voltage, VIH 0.85 VCC V
Low-level input voltage, VIL 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) –1.8 1.5 A
Setup time, D high before CLK↑, tsu (see Figure 2) 10 ns
Hold time, D high after CLK↑, th (see Figure 2) 15 ns
Pulse duration, tw (see Figure 2) 25 ns
Operating case temperature, TC–40 125 °C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-source breakdown voltage ID = 1 mA 45 V
VSD Source-drain diode forward voltage IF = 250 mA, See Note 3 0.85 1 V
IIH High-level input current VCC = 5.5 V, VI = VCC 1µA
IIL Low-level input current VCC = 5.5 V, VI = 0 –1 µA
ICC Logic supply current IO = 0, All inputs low 15 100 µA
INNominal current VDS(on) = 0.5 V,
IN = ID,T
C
= 85°CSee Notes 5, 6, and 7 250 mA
IDSX
Off state drain current
VDS = 40 V 0.05 1
µA
I
DSX
Off
-
state
drain
c
u
rrent
VDS = 40 V, TC = 125°C 0.15 5 µ
A
ID = 250 mA, VCC = 4.5 V 1.3 2
rDS(on) Static drain-source on-state
resistance ID = 250 mA, TC = 125°C,
VCC = 4.5 V See Notes 5 and 6
and Figures 8 and 9 2 3.2 Ω
ID = 500 mA, VCC = 4.5 V 1.3 2
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from CLK 625 ns
tPHL Propagation delay time, high-to-low-level output from CLK C
L
= 30 pF, I
D
= 250 mA, 150 ns
trRise time, drain output
L,D,
See Figures 1, 2, and 10 675 ns
tfFall time, drain output 400 ns
taReverse-recovery-current rise time IF = 250 mA, di/dt = 20 A/µs, 100
ns
trr Reverse-recovery time
Fµ
See Notes 5 and 6 and Figure 3 300
ns
NOTES: 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produce s a
voltage drop of 0.5 V at TC = 85°C.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
RθJA
Thermal resistance junction to ambient
DW package
All 8 out
p
uts with equal
p
ower
111 °
C/W
R
θJA
Thermal
resistance
,
j
u
nction
-
to
-
ambient
N package
All
8
o
u
tp
u
ts
w
ith
eq
u
al
po
w
er
108
°C/W
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V 24 V
VCC
DRAIN
GND
CLR
RL = 95 Ω
VOLTAGE WAVEFORMS
Output
D
Word
Generator
(see Note A)
CLK
CLR
Output
D
CLK DUT
CL = 30 pF
(see Note B)
0 V
5 V
0 V
5 V
0 V
5 V
0.5 V
24 V
11
1
10
20
4–7,
14–17
ID
Figure 1. Resistive Load Normal Operation
5 V
DUT
VCC CLR
DRAIN
GND
D95 Ω
TEST CIRCUIT
SWITCHING TIMES
D
CLK
Word
Generator
(see Note A)
CLK
5 V
0 V
5 V
0 V
50%
Output 24 V
0.5 V
90%
10%
tPLH
tr
50%
90% 10%
tPHL
tf
CLK
5 V
0 V
50%
D5 V
0 V
50% 50%
tsu th
tw
INPUT SETUP AND HOLD WAVEFORMS
CL = 30 pF
(see Note B)
Output
Word
Generator
(see Note A)
20
10
1
11
24 V
4–7,
14–17
ID
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 KHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.25 A
IF
0
IRM
25% of IRM
ta
trr
di/dt = 20 A/µs
+
–
2500 µF
250 V
L = 1 mH
IF
(see Note B)
RG
VGG
(see Note A)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
25 V
t1t3
t2
TP K
TEST CIRCUIT CURRENT WAVEFORM
NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
5 V 15 V
Input
Word
Generator
(see Note A)
VCC
DRAIN
GND
D
0.11 Ω
100 mH
VDS
TEST CIRCUIT
CLR
DUT
CLK
1
11
20
10
twtav†
IAS = 1 A
V(BR)DSX = 45 V
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
5 V
0 V
ID
4–7,
14–17
MIN
†Non-JEDEC symbol for avalanche ftime.
NOTES: A. The word generator A has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 1 A.
Energy test is defined as EAS = IAS x V(BR)DSX x tav/2 = 75 mJ, where tav = avalanche time.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and W aveforms
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
2
1
10
4
0.1 0.2 10.4 2 104
0.2
0.1
0.4
I – Peak Avalanche Current – A
AS
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
tav – Time Duration of Avalanche – ms
TJS = 25°C
– Maximum Continuous Drain Current
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
400
200
100
0012 3 45
600
700
800
678
500
300
VCC = 5 V
TA = 25°C
TA = 100°C
TA = 125°C
N – Number of Outputs Conducting Simultaneously
of Each Output – mA
D
I
Figure 5 Figure 6
1
0.5
0012345
– Peak Drain Current – A
678
1.5
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
D
VCC = 5 V
TA = 25°C
d = tw/tperiod
= 1 ms/tperiod
d = 10%
d = 5%
d = 50%
d = 80%
N – Number of Outputs Conducting Simultaneously
I
2
Figure 7
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
DRAIN CURRENT
VCC – Logic Supply Voltage – V
0
0.5
1
1.5
2
2.5
3
34567
T
C
= 125 °CID = 250 mA
See Note A
ID – Drain Current – A
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
Ω
DS(on) – Static Drain-Source On-State Resistance –
2
1.5
0.5
0
0.25 0.5 0.75 1
2.5
3.5
4
1.25 1.5
1
3
TC = 25 °C
TC = 125 °C
VCC = 5 V
See Note A
r
TC = – 40 °C
Ω
DS(on) – Static Drain-Source On-State Resistance –r
TC = 25 °C
TC = –40 °C
Figure 8 Figure 9
500
300
200
100
700
400
– 50 0 50 100 150
600
SWITCHING TIME
vs
FREE-AIR TEMPERATURE
Switching Time – ns
tPHL
tPLH
tr
tf
ID = 250 mA
See Note A
TA – Free-Air Temperature – °C
Figure 10
NOTE A: Technique should limit TJ – TC to 10°C maximum.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPIC6273DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6273DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6273N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPIC6273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPIC6273DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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