©2012 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FSB50660SFS Rev. 1.1
FSB50660SFS Motion SPM® 5 SuperFET® Series
Aug 2015
FSB50660SFS
Motion SPM® 5 SuperFET® Series
Features
• UL Certified No. E209204 (UL1557)
• 600 V RDS(on) = 7 00 mMax Su perFET MOSFET 3-
Phase Inverter with Gate Drivers and Protection
• Built-in Bootstrap Diodes Simplify PCB Layout
• Separate Open-Source Pins from Low-Side MOS-
FETS for Three-Phase Current-Sensing
• Active-HIGH Interface, Works with 3.3 / 5 V Logic,
Schmitt-trigger Input
• Optimized for Low Electromagnetic Interference
• HVIC Temperature-Sensing Built-in for Temperature
Monitoring
• HVIC for Gate Driving and Under-Voltage Protection
• Isolation Rating: 1500 Vrms / 1 min.
• Moisture Sensitive Level (MSL) 3
• RoHS Compliant
Applications
• 3-Phase Inverter Driver for Small Power AC Motor
Drives
Related Source
•RD-402 - Reference Desi gn for Motion SPM
5 Super-
FET Series
• AN-9082 - Motion SPM5 Series Thermal Performance
by Contact Pressure
• AN-9080 - User’s Guide for Motion SPM 5 Series V2
General Description
The FSB50660SFS is an advanced Motion SPM® 5
module providing a fully-featured, high-performance
inverter output stage for AC Induction, BLD C and PMSM
motors such as refrigerators, fans and pumps. These
modules integrate optimized gate drive of the built-in
MOSFETs(SuperFET® technology) to mi nimize EMI and
losses, while also providing multiple on-module
protection features including under-voltag e lockouts and
thermal monitoring. The built-in high-speed
HVIC requires only a single supply voltage and
translates the incoming logic-level gate inputs to the
high-voltage, high-current drive signals required to
properly drive the module's internal MOSFETs.
Separate open-source MOSFET terminals are available
for each phase to support the widest variety of control
algorithms.
3D Package Drawing (Click to Activate 3D Content)
Package Marking & Ordering Information
Device Marking Device Package Reel Size Packing Type Quantity
50660SFS FSB50660SFS SPM5Q-023 330mm Tape-Reel 450
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 2www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Absolute Maximum Ratings
Inverter Part (each MOSFET unless otherwise specified.)
Control Part (each HVIC unless otherwise specified.)
Bootstrap Diode Part (each bootstrap diode unless otherwise specified.)
Thermal Resistance
Total System
1st Notes:
1. For the m easurement point of case temperatur e TC, please refer to Figure 4.
2. Marking “ * “ is calculation value or design factor.
Symbol Parameter Conditions Rating Unit
VDSS Drain-Source Voltage of Each MOSFET 600 V
*ID 25 Each MOSFET Drain Current, Continuous TC = 25°C 3.1 A
*ID 80 Each MOSFET Drain Current, Continuous TC = 80°C 2.3 A
*IDP Each MOSFET Drain Current, Peak TC = 25°C, PW < 100 s 8.1 A
*IDRMS Each MOSFET Drain Current, Rms TC = 80°C, FPWM < 20 kHz 1.6 Arms
*PDMaximum Power Dissipation TC = 25°C, For Each MOSFET 14.2 W
Symbol Parameter Conditions Rating Unit
VCC Control Supply Voltage Applied Between VCC and COM 20 V
VBS High-side Bias Voltage Applied Between VB and VS20 V
VIN Input Signal Voltage Applied Between IN and COM -0.3 ~ VCC + 0.3 V
Symbol Parameter Conditions Rating Unit
VRRMB Maximum Repetitive Reverse Voltage 600 V
* IFB Forward Current TC = 25°C 0.5 A
* IFPB Forward Current (Peak) TC = 25°C, Under 1ms Pulse Width 1.5 A
Symbol Parameter Conditions Rating Unit
RJC Junction to Case Thermal Resistance Each MOSFET under Inverter Oper-
ating Condition (1st Note 1) 8.8 °C/W
Symbol Parameter Conditions Rating Unit
TJOperating Junction Temperature -40 ~ 150 °C
TSTG Storage Temperature -40 ~ 125 °C
VISO Isolation Voltage 60 Hz, Sinusoidal, 1 Minute, Con-
nect Pins to Heat Sink Plate 1500 Vrms
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 3www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Pin descriptions
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
1st Notes:
3. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM® 5 product. External connections should be made as
indicated in Figure 3.
Pin Number Pin Name Pin Description
1 COM IC Common Supply Ground
2V
B(U) Bias Voltage for U-Phase High-Side MOSFET Driving
3V
CC(U) Bias Voltage for U-Phase IC and Low-Side MOSFET Driving
4IN
(UH) Signal Input for U-Phase High-Side
5IN
(UL) Signal Input for U-Phase Low-Side
6 N.C No Connection
7V
B(V) Bias Voltage for V-Phase High Side MOSFET Driving
8V
CC(V) Bias Voltage for V-Phase IC and Low Side MOSFET Driving
9IN
(VH) Signal Input for V-Phase High-Side
10 IN(VL) Signal Input for V-Phase Low-Side
11 VTS Output for HVIC Temperature Sensing
12 VB(W) Bias Voltage for W-Phase High-Side MOSFET Driving
13 VCC(W) Bias Voltage for W-Phase IC and Low-Side MOSFET Driving
14 IN(WH) Signal Input for W-Phase High-Side
15 IN(WL) Signal Input for W-Phase Low-Side
16 N.C No Connection
17 P Positive DC-Link Input
18 U, VS(U) Output for U-Phase & Bias Voltage Ground for High-Side MOSFET Driving
19 NUNegative DC-Link Input for U-Phase
20 NVNegative DC-Link Input for V-Phase
21 V, VS(V) Output for V-Phase & Bias Voltage Ground for High-Side MOSFET Driving
22 NWNegative DC-Link Input for W-Phase
23 W, VS(W) Output for W Phase & Bias Voltage Ground for High-Side MOSFET Driving
(1) COM
(2) VB(U)
(3) VCC(U)
(4) I N (UH)
(5) I N (UL)
(6) N.C
(7) VB(V)
(8) VCC(V)
(9) I N (VH)
(10) IN(VL)
(11) VTS
(12 ) V B(W)
(13) VCC(W)
(14) IN (WH)
(15) IN (WL)
(16)
(17) P
(18) U, VS(U)
(19) NU
(20) NV
(21) V, VS(V)
(22) NW
(23) W, VS(W)
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
VTS
COM
VCC
LIN
HIN
VB
HO
VS
LO
N.C
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 4www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Electrical Characteristics (TJ = 25°C, VCC = VBS = 15 V unless otherwise specified.)
Inverter Part (each MOSFET unless otherwise specified.)
Control Part (each HVIC unless otherwise specified.)
Bootstrap Diode Part (each bootstrap diode unless otherwise specified.)
2nd Notes:
1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM® 5 product. VPN shou ld be sufficiently less than this
value consideri ng the ef f ect of the str ay inductance so that VPN should not exceed BVDSS in any case.
2. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field
applications due to the effect of different printed circuit boards and wirings. Please see Figure 6 for the switching time definition with the switching test circuit of Figure 7.
3. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating Area (SOA). Please see Figure 7 for the RBSOA test
circuit that is same as the switching test circuit.
4. Vts is only for sensing-temperature of modu l e and can not shut down MOSFETs automatically.
5. Built-in bootstrap diode includes around 15Ωresistance characteristic. Please refer to Figure 2.
Symbol Parameter Conditions Min Typ Max Unit
BVDSS Drain - Source
Breakdown Voltage VIN = 0 V, ID = 1 mA (2nd Note 1) 600 - - V
IDSS Zero Gate Voltage
Drain Current VIN = 0 V, VDS = 600 V - - 1 mA
RDS(on) Static Drain - Source
Turn-On Resistance VCC = VBS = 15 V, VIN = 5 V, ID = 1.5 A - 600 700 m
VSD Drain - Source Diode
Forward Voltage VCC = VBS = 15 V, VIN = 0 V, ID = -1.5 A - - 1.1 V
tON
Switching Times
VPN = 300 V, VCC = VBS = 15 V, ID = 1.5 A
VIN = 0 V 5 V, Inductive Load L = 3 mH
High- and Low-Side MOSFET Switching
(2nd Note 2)
- 950 - ns
tOFF - 820 - ns
trr - 120 - ns
EON - 130 - J
EOFF -5- J
RBSOA Reverse Bias Safe Oper-
ating Area
VPN = 400 V, VCC = VBS = 15 V, ID = IDP, VDS = BVDSS,
TJ = 150°C
High- and Low-Side MOSFET Switching (2nd Note 3) Full Square
Symbol Parameter Conditions Min Typ Max Unit
IQCC Quiescent VCC Current VCC = 15 V,
VIN = 0 V Applied Between VCC and COM - - 200 A
IQBS Quiescent VBS Current VBS = 15 V,
VIN = 0 V Applied Between VB(U) - U,
VB(V) - V, VB(W) - W - - 100 A
UVCCD Low-Side Under-Voltage
Protection (Figure 8) VCC Under-Voltage Protection Detection Level 7.4 8.0 9.4 V
UVCCR VCC Under-Voltage Protection Reset Level 8.0 8.9 9.8 V
UVBSD High-Side Under-Voltage
Protection (Figure 9) VBS Under-Voltage Protection Detection Level 7.4 8.0 9.4 V
UVBSR VBS Under-Voltage Protection Reset Level 8.0 8.9 9.8 V
VTS HVIC Temperature Sens-
ing Voltage Output VCC = 15 V, THVIC = 25°C (2nd Note 4) 600 790 980 mV
VIH ON Threshold Voltage Logic HIGH Level Applied between IN and COM --2.9V
VIL OFF Threshold Voltage Logic LOW Level 0.8 - - V
Symbol Parameter Conditions Min Typ Max Unit
VFB Forward Voltage IF = 0.1 A, TC = 25°C (2nd Note 5) - 2.5 - V
trrB Reverse Recovery Time IF = 0.1 A, TC = 25°C - 80 - ns
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 5www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Recommended Operating Condition
Figure 2. Built-in Bootstrap Diode Characteristics (Typical)
Symbol Parameter Conditions Min. Typ. Max. Unit
VPN Supply Voltage Applied Between P and N - 300 450 V
VCC Control Supply Voltage Applied Between VCC and COM 13.5 15.0 16.5 V
VBS High-Side Bias Voltage Applied Between VB and VS13.5 15.0 16.5 V
VIN(ON) Input ON Threshold Voltage Applied Between IN and COM 3.0 -VCC V
VIN(OFF) Input OFF Threshold Voltage 0 -0.6 V
tdead Blanking Time for Preventing
Arm-Short VCC = VBS = 13.5 ~ 16.5 V, TJ 150°C 1.0 - - s
fPWM PWM Switching Frequency TJ 150°C - 20 - kHz
0123456789101112131415
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0 Built-in Bootstrap Diode VF-IF Characteristic
IF [A]
VF [V ]
Tc=25°C
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 6www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters
3rd Notes:
1. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
2. RC-coupli ng (R 5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise.
3. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge-voltage. Bypass cap acitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple-current.
Figure 4. Case Temperature Measurement
3rd Notes:
4. Attach the thermocouple on top of the heat-sink of SPM 5 package (between SPM 5 package and heatsink if applied) to get the correct temperature meas urement.
Figure 5. Temperature Profile of VTS (Typical)
HIN LIN Output Note
0 0 Z Both FRFET Off
0 1 0 Low side F RFET On
10 V
DC High side F RFE T On
1 1 Forbidden Shoot through
Open Open Z Same as (0,0)
COM
VCC
LIN
HIN
VB
HO
VS
LO
P
NR3
Inverter
Output
C3
C1
MCU
+15 V
10F
These values depend on PWM control algorithm
* Example of Bootstrap Paramters:
C1 = C2 = 1 F Ceramic Capacitor
R5
C5
VDC
C2
VTS
* Example Circ uit : V phase
C4
V
One Leg Diagram of Mot ion S P M® 5 Product
20 40 60 80 100 120 140 160
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VTS [V]
THVIC [oC]
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 7www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Figure 6. Switching Time Definitions
Figure 7. Switching and RBSOA (Single-pulse) Test Circuit (Low-side)
Figure 8. Under-Voltage Protection (Low-Side)
Figure 9. Under-Voltage Protection (High-Side)
tON trr
Irr
100% of ID120% of ID
(a) Turn -on
tOFF
(b) Tu rn -o ff
ID
VDS
VDS
ID
VIN VIN
10% of ID
COM
VCC
LIN
HIN
VB
HO
VS
LO
ID
VCC
CBS
LV
DC
+
VDS
-
VTS
One Leg Diagram of Motion SPM® 5 Product
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 8www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Figure 10. Example of Application Circuit
4th Notes:
1. About pin position, refer to Figure 1.
2. RC-coupling (R5 and C5, R4 and C6) and C4 at each input of Motion SPM® 5 product and MCU are useful to prevent improper input signal caused by surge-noise.
3. The voltage -drop acros s R3 affects the low-side switching performance and the bootstrap characteristics since it is placed between COM and the source terminal of the low-
side MOSFET. For this reason, the voltage-drop across R3 should be less than 1 V in the steady-state.
4. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC.
5. All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for rejecting high-frequency ripple current.
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN (UH)
(5) IN (UL)
(6) N.C
(7) VB(V)
(8) VCC(V)
(9) IN (VH)
(10) I N (VL)
(11) V TS
(12) V B(W)
(13) V CC(W)
(14) I N (WH)
(15) I N (WL)
(16) N .C
(17) P
(18) U, V S(U)
(19) N U
(22) N W
Micom
C1
15 V
Supply
C3VDC
C2
R3
R4
C6
R5
C5
For current-sensing and protection
VTS
(21) V, V S(V)
(20) N V
(23) W, VS(W)
C4
M
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 9www.fairchildsemi.com
FSB50660SFS Rev. 1.1
Detailed Package Outline Drawings (FSB50660SFS)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or data on the drawing and contact a FairchildSemiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide therm and conditions,
specifically the the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/MO/MOD23DG.pdf
FSB50660SFS Motion SPM® 5 SuperFET® Series
©2012 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com
FSB50660SFS Rev. 1.1
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