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FEATURES
All-silicon time delay
Two programmable outputs from a single
input produce output-to-output delays
between 9ns and 84ns depending on device
type
Programmable via four input pins
Programmable increments of 3ns to 5ns with
a minimum of 9ns and a maximum of 84ns
Output pulse is a reproduction of input pulse
after
Delay with both leading and trailing edge
accuracy
Standard 16-pin DIP or surface mount 16-pin
SOIC
Auto-insertable
Low-power CMOS design is TTL-compatible
PIN ASSIGNMENT
PIN DESCRIPTION
IN - Delay Li ne Input
OUTA, OUTB - Delay Line Outputs
A0-A3 - Parallel Program Inputs
for OUT1
B0-B3 - Parallel Program Inputs
for OUT2
EA , EB - Enable A and B Inputs
VCC - +5V Input
GND - Ground
DESCRIPTION
The DS1045 is a programmable silicon delay line having one input and two 4-bit programmable delay
outputs. Each 4-bit programmable output offers t he user 16 possible delay values to select from, s tarting
with a minimum inherent DS1045 dela y of 9ns and a max imum achiev able dela y in the standard DS1045
family of 84ns. The standard DS1045 product line provides the user with three devices having uniform
delay increments of 3ns, 4ns, and 5ns, depending on the device. Table 1 presents standard device family
and delay capability. Additionally, custom dela y increments are available for special order throu gh Dallas
Semiconductor.
The DS1045 is TTL and CMOS-compatible and capable of driving ten 74LS-type loads. The output
produced by the DS1045 is both rising and falling edge precise. The DS1045 programmable silicon dela y
line has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is
offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC package.
DS1045
4-Bit Dual Progr ammabl e Delay Lin e
www.maxim-ic.com
IN
VCC
EA
A0
A1
A2
A3
GND
VCC
EB
OUTB
B0
B1
B2
B3
OUTA
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN VCC
16
1
VCC
E
A
A0
A1
A2
A3
GND
EB
OUTB
B0
B1
B2
B3
OUTA
2
3
4
5
6
7
8
15
14
13
12
11
10
9
DS1045 16-Pin DIP
See Mech. Drawings
Section
DS1045S 16-Pi n SOIC (300-mil )
See Mech. Drawings
Section
DS1045
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PARALLEL PROGRAMMING
Parallel programming of the DS1045 is accomplished via the set of parallel inputs A0-A3 and B0-B3 as
shown in Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay
values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum
9ns delay and the maximum delay of the DS1045-x device version can be selected using the parallel
programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, the
DS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible delays between the
9ns (minimum) and the 54ns (maximum) in 3ns increment levels.
For applications that do not require frequent reprogramming, the parallel inputs can be set using fixed
logic levels, as would be produced by jumpers, DIP switches, or TTL levels as produced by computer
systems. Maximum flexibility in parallel programming can be achiev ed when inputs are set b y computer-
generated data. By using the enable input pins for each respective programmed output and observing the
input setup (tDSE) and hold time (tDHE) requirements, data can be latched on an 8-bit bus. If the enable
pins, EA and EB , are not used to latch data, the y should be set to a logic level 1. After each chan ge in the
programmed delay value, a settling time (tEDV) or (tPDV) is required before the delayed output signal is
reliably produced. Since the DS1045 is a CMOS design, undefined input pins should be connected to well
defined logic levels and not left floating.
PART NUMBER TABLE Table 1
PART NUMBER STEP ZERO DELAY MAX DELAY TIME MAX DELAY
TOLERANCE
DS1045-3 9 ±=1ns 54ns ±2.5ns
DS1045-4 9 ±=1ns 69ns ±3.3ns
DS1045-5 9 ±=1ns 84ns ±4.1ns
NOTE:
Additional delay step times are available from Dallas Semiconductor by special order. Consult factory for
availability.
BLOCK DIAGR AM Figure 1
DS1045
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DELAY VS. PROGRAMMED VALUE Table 2
PART NUMBER OUTPUT DELAY VALUE
DS1045-3 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54
DS1045-4 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69
DS1045-5 9 14 19 24 29 34 39 44 49 54 59 64 69 74 79 84
PROGRAM VALUES FOR EACH DELAY VALUE
A0 OR B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A1 OR B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A2 OR B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A3 OR B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DS1045 TEST CIRCUIT Figure 2
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1045.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1045 parallel
inputs are controlled by an interface to a central computer. All measurements are fully automated with
each instrument controlled by the computer over an IEEE 488 bus.
DS1045
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AB SOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature See J-STD-020A specification
Short Circuit Output Current 50mA for 1 second
* This is a stress rating onl y and functional operat ion of the device at these or an y other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMME NDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.75 5.0 5.25 V 1
Input Lo gic 1 VIH 2.2
VCC
+0.5 V 1
Input Lo gic 0 VIL -0.5 0.8
µA 1
Input Le aka ge II 0 ≤VI≤VCC -1.0 +1.0 µA
Active Current ICC VCC=5.25V
PERIOD=1 µs 35.0 mA
Logic 1 Output
Current IOH VCC= 4.75V VOH=
4.0V -1.0 mA
Logic 0 Output
Current IOL VCC= 4.75V VOL=
0.5V 8 mA
AC ELECTRICAL CH ARACTERISTICS (0°C to 70°C; VCC 5V ± 5%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Period tPERIOD 4 x tWI ns
Pulse Width tWI 100% of
output
delay ns
Input to Output Delay tPLH, tPHL Table 1 ns 2
Parallel Input Change to
Delay Invalid tPDX 0 ns
Parallel Input Valid to Delay
Valid tPDV 10 ns
Enable Width tEW 15 ns
Data Setup to Enable tDSE 10 ns
Data Hold from Enable tDHE 0 ns
Enable to Delay Invalid tEDX 5 ns
Enable to Delay Valid tEDV 15 ns
DS1045
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CAPACITANCE (TA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 10 pF
TEST CONDITIONS
TA=25°C ±=3°C
VCC= 5.0V ±=0.1V
Input Pulse = 3.0V high to 0.0V low ±=0.1V
Input Sourc e Impedance = 50Ω maximum
Rise and fall times = 3.0ns max. between 0.6V and 2.4V
Pulse Width = 250ns
Period = 500ns
Output Load = 74F04
Measurement Point = 1.5V on inputs and outputs
Output Load Capacitance = 15pF
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
TIMING DI AGR AM: NON-LATCHED PARALLEL M O DE, E
A
, EB = VIH
TIMING DI AGR AM: LATCHED PARALLEL M O DE
DS1045
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TIMING DIAGRAM: DS1045 INPUTS TO OUTPUTS
TERMINOLOGY
PERIOD: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V
point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V on the leading edge.
tRISE ( Input Rise Time): The elapsed time betwee n the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elaps ed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
NOTES:
1. All voltages are referenced to ground.
2. @ VCC = 5V and 25°C. Delay accurate on both rising and falling edges within tolerances given in
Table 1.
