CD74HC40103E - Texas Instruments - Datasheet.Directory

Data sheet acquired from Harris Semiconductor

SCHS221D

Features

• Synchronous or Asynchronous Preset

• Cascadable in Synchronous or Ripple Mode

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC40103 and CD74HCT40103 are manufactured with

high speed silicon gate technology and consist of an 8-stage

synchronous down counter with a single output which is

active when the internal count is zero. The 40103 contains a

single 8-bit binary counter. Each has control inputs for

enabling or disabling the clock, for clearing the counter to its

maximum count, and for presetting the counter either

synchronously or asynchronously. All control inputs and the

TC output are active-low logic.

In normal operation, the counter is decremented by one

count on each positive transition of the CLOCK (CP).

Counting is inhibited when the TE input is high. The TC

output goes low when the count reaches zero if the TE input

is low, and remains low for one full clock period.

When the PE input is low, data at the P0-P7 inputs are

clocked into the counter on the next positive clock transition

regardless of the state of the TE input. When the PL input is

low, data at the P0-P7 inputs are asynchronously forced into

the counter regardless of the state of the PE, TE, or CLOCK

inputs. Input P0-P7 represent a single 8-bit binary word for

the 40103. When the MR input is low, the counter is

asynchronously cleared to its maximum count of 25510,

regardless of the state of any other input. The precedence

relationship between control inputs is indicated in the truth

table.

If all control inputs except TE are high at the time of zero

count, the counters will jump to the maximum count, giving a

counting sequence of 10016 or 25610 clock pulses long.

The 40103 may be cascaded using the TE input and the TC

output, in either a synchronous or ripple mode. These

circuits possess the low power consumption usually

associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL circuits and can drive

up to 10 LSTTL loads.

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC40103F3A -55 to 125 16 Ld CERDIP

CD74HC40103E -55 to 125 16 Ld PDIP

CD74HC40103M -55 to 125 16 Ld SOIC

CD74HC40103MT -55 to 125 16 Ld SOIC

CD74HC40103M96 -55 to 125 16 Ld SOIC

CD74HCT40103E -55 to 125 16 Ld PDIP

CD74HCT40103M -55 to 125 16 Ld SOIC

CD74HCT40103MT -55 to 125 16 Ld SOIC

CD74HCT40103M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC40103, CD74HC40103,

CD74HCT40103

High-Speed CMOS Logic

8-Stage Synchronous Down Counters

[ /Title

(CD74H

C40103,

CD74H

CT4010

/Sub-

ject

(High

Speed

CMOS

Logic 8-

Pinout

CD54HC40103

(CERDIP)

CD74HC40103, CD74HCT40103

(PDIP, SOIC)

TOP VIEW

Functional Diagram

TRUTH TABLE

CONTROL INPUTS

PRESET MODE ACTIONMR PL PE TE

1111 Synchronous Inhibit Counter

1110 Count Down

1 1 0 X Preset On Next Positive Clock Transition

1 0 X X Asynchronously Preset Asychronously

0 X X X Clear to Maximum Count

1 = High Level.

0 = Low Level.

X = Don’t Care.

Clock connected to clock input.

Synchronous Operation: changes occur on negative-to-positive clock transitions.

Load Inputs: MSB = P7, LSB = P0.

GND

VCC

PL (ASYNC)

PE (SYNC)

GND

VCC

15 9 3 1 2 16 8

CD54HC40103, CD74HC40103, CD74HCT40103

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

CD54HC40103, CD74HC40103, CD74HCT40103

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC

(Note 2) VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS (NOTE)

P0-P7 0.20

TE, MR 0.40

CP 0.60

PE 0.80

PL 1.35

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Prerequisite for Switching Speciﬁcations

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

CP Pulse Width tW2 165 - - 205 - 250 - ns

4.5 33 - - 41 - 50 - ns

628- -35-43-ns

PL Pulse Width tW2 125 - - 155 - 190 - ns

4.5 25 - - 31 - 38 - ns

621- -26-32-ns

CD54HC40103, CD74HC40103, CD74HCT40103

MR Pulse Width tW2 125 - - 135 - 190 - ns

4.5 25 - - 31 - 38 - ns

621- -26-32-ns

CP Max. Frequency

(Note 3) fCP(MAX) 23--2-2-MHz

4.5 15 - - 12 - 10 - MHz

6 18 - - 14 - 12 - MHz

P to CP Set-up Time tSU 2 100 - - 125 - 150 - ns

4.5 20 - - 25 - 30 - ns

617- -21-26-ns

PE to CP Set-up Time tSU 275- -95-110-ns

4.5 15 - - 19 - 22 - ns

613- -16-19-ns

TE to CP Set-up Time tSU 2 150 - - 190 - 225 - ns

4.5 30 - - 38 - 45 - ns

626- -33-38-ns

P to CP Hold Time tH25--5-5-ns

4.55--5-5-ns

65--5-5-ns

TE to CP Hold Time tH20--0-0-ns

4.50--0-0-ns

60--0-0-ns

MR to CP Removal Time tREM 250- -65-75-ns

4.5 10 - - 13 - 15 - ns

6 9 - - 11 - 13 - ns

PE to CP Hold Time tH22--2-2-ns

4.52--2-2-ns

62--2-2-ns

HCT TYPES

CP Pulse Width tW4.5 35 - - 44 - 53 - ns

PL Pulse Width tW4.5 43 - - 54 - 65 - ns

MR Pulse Width tW4.5 35 - - 44 - 53 - ns

CP Max. Frequency

(Note 3) fCP(MAX) 4.5 14 - - 11 - 9 - MHz

P to CP Set-up Time tSU 4.5 24 - - 30 - 36 - ns

PE to CP Set-up Time tSU 4.5 20 - - 25 - 30 - ns

TE to CP Set-up Time tSU 4.5 40 - - 50 - 60 - ns

P to CP Hold Time tH4.55--5-5-ns

TE to CP Hold Time tH4.50--0-0-ns

MR to CP Removal Time tREM 4.5 10 - - 13 - 15 - ns

PE to CP Hold Time tH 4.5 2 - - 2 - 2 - ns

Prerequisite for Switching Speciﬁcations (Continued)

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD54HC40103, CD74HC40103, CD74HCT40103

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay tPLH,

tPHL CL = 50pF 2 - - 300 - 375 - 450 ns

CP to any TC (Async Preset) CL = 50pF 4.5 - - 60 - 75 - 90 ns

CL = 15pF 5 - 25 - - - ns

CL = 50pF 6 - - 51 - 64 - 77 ns

CP to TC (Sync Preset) tPLH,

tPHL CL = 50pF 2 - - 300 - 375 - 450 ns

CL = 50pF 4.5 - - 60 - 75 - 90 ns

CL = 15pF 5 - 25 - - - - - ns

CL = 50pF 6 - - 51 - 64 - 77 ns

TE to TC tPLH,

tPHL CL = 50pF 2 - - 200 - 250 - 300 ns

CL = 50pF 4.5 - - 40 - 50 - 60 ns

CL = 15pF 5 - 17 - - - - - ns

CL = 50pF 6 - - 34 - 43 - 51 ns

PL to TC tPLH,

tPHL CL = 50pF 2 - - 275 - 345 - 415 ns

CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

CL = 50pF 6 - - 47 - 59 - 71 ns

MR to TC tPLH,

tPHL CL = 50pF 2 - - 275 - 345 - 415 ns

CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

CL = 50pF 6 - - 47 - 59 - 71 ns

Output Transition Time tTLH,t

THL CL = 50pF 2 - - 75 - 95 - 110 ns

CL = 50pF 4.5 - - 15 - 19 - 22 ns

CL = 50pF 6 - - 13 - 16 - 19 ns

Input Capacitance CICL = 50pF - - - 10 - 10 - 10 pF

CP Maximum Frequency fMAX CL = 15pF 5 - 25 - - - - - MHz

Power Dissipation Capacitance

(Notes 4, 5) CPD -5-25-----pF

HCT TYPES

Propagation Delay

CP to TC (Async Preset) tPLH,

tPHL CL = 50pF 4.5 - - 60 - 75 - 90 ns

CL = 15pF 5 - 25 - - - - - ns

CE to TC (Sync Preset) tPLH,

tPHL CL = 50pF 4.5 - - 63 - 79 - 95 ns

CL = 15pF 5 - 26 - - - - - ns

TE to TC tPLH,

tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

PL to TC tPLH,

tPHL CL = 50pF 4.5 - - 68 - 85 - 102 ns

CL = 15pF 5 - 28 - - - - - ns

CD54HC40103, CD74HC40103, CD74HCT40103

MR to TC tPLH,

tPHL CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

Output Transition Time tTHL,t

TLH CL = 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF

CP Maximum Frequency fMAX CL = 15pF 5 - 25 - - - - - MHz

Power Dissipation Capacitance

(Notes 4, 5) CPD -5-27-----pF

NOTES:

3. Noncascadedoperationonly. Withcascadedcountersclock-to-terminalcountpropagation delays, countenables(PEorTE)-to-clockSET

UP TIMES, and count enables (PE or TE)-to-clock HOLD TIMES determine maximum clock frequency. For example, with these HC de-

vices:

4. CPD is used to determine the dynamic power consumption, per package.

5. PD = VCC2 fi+ CL VCC2 fo where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage, fo = Output Frequency.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CPfMAX 1

CP-to-TC prop delay + TE-to-CP Setup Time + TE-to-CP Hold Time

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

60 30 0++

-----------------------------11MHz≈==

Timing Diagrams

FIGURE 1.

HC/HCT40103 COUNT 255 254 3 2 1 0 255 254 254 253 8 7 6 5 4 255 254 253 252

CD54HC40103, CD74HC40103, CD74HCT40103

Test Circuits and Waveforms

FIGURE 2. FIGURE 3.

FIGURE 4. FIGURE 5.

FIGURE 6. FIGURE 7.

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 8. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 9. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tTHL

tPHL

90%

10%

VSGND

tPLH

tTLH

INPUT LEVEL

1/fMAX

90%

10%

INPUT LEVEL

GND

tREM

VSGND

INPUT LEVEL

10%

90%

TE tPHL

tTHL tTLH

tPLH

tfINPUT LEVEL

10%

90%

tSU

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUTS

P0 - P7

VALID

tSU th

tREC

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUT LEVEL

GND

tSU

INPUT LEVEL

GND

INPUT LEVEL

GND

CLOCK 90% 50%

10% GND

VCC

trCLtfCL

50% 50%

tWL tWH

10%

tWL + tWH =fCL

CLOCK 2.7V 1.3V

0.3V GND

trCL= 6ns tfCL= 6ns

1.3V 1.3V

tWL tWH

0.3V

tWL + tWH =fCL

CD54HC40103, CD74HC40103, CD74HCT40103

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

5962-9055301EA ACTIVE CDIP J 16 1 TBD Call TI Call TI

5HC40103F3AS228 OBSOLETE CDIP J 16 TBD Call TI Call TI

CD54HC40103F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD54HC40103F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD74HC40103E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC40103EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC40103M ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103M96 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103M96E4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103M96G4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103ME4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103MG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103MT ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103MTE4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC40103MTG4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT40103EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT40103M ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103M96 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103M96E4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

CD74HCT40103M96G4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103ME4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103MG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103MT ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103MTE4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT40103MTG4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 3

OTHER QUALIFIED VERSIONS OF CD54HC40103, CD74HC40103 :

•Catalog: CD74HC40103

•Automotive: CD74HC40103-Q1, CD74HC40103-Q1

•Enhanced Product: CD74HC40103-EP, CD74HC40103-EP

•Military: CD54HC40103

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC40103M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74HCT40103M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC40103M96 SOIC D 16 2500 333.2 345.9 28.6

CD74HCT40103M96 SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2008

Pack Materials-Page 2

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