TL16C2550-Q1
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SLWS232 –DECEMBER 2011
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
Check for Samples: TL16C2550-Q1
1FEATURES
•Qualified for Automotive Applications –Baud Generation (DC to 1 Mbit/s)
•Programmable Auto-RTS and Auto-CTS •False-Start Bit Detection
•In Auto-CTS Mode, CTS Controls Transmitter •Complete Status Reporting Capabilities
•In Auto-RTS Mode, RCV FIFO Contents, and •3-State Output TTL Drive Capabilities for
Threshold Control RTS Bidirectional Data Bus and Control Bus
•Serial and Modem Control Outputs Drive a •Line Break Generation and Detection Internal
RJ11 Cable Directly When Equipment Is on the Diagnostic Capabilities:
Same Power Drop –Loopback Controls for Communications
•Capable of Running With All Existing Link Fault Isolation
TL16C450 Software –Break, Parity, Overrun, and Framing Error
•After Reset, All Registers Are Identical to the Simulation
TL16C450 Register Set •Fully Prioritized Interrupt System Controls
•Up to 24-MHz Clock Rate for up to 1.5-Mbaud •Modem Control Functions (CTS, RTS, DSR,
Operation With VCC = 5 V DTR, RI, and DCD)
•Up to 20-MHz Clock Rate for up to 1.25-Mbaud •Available in 48-Pin TQFP (PFB) Package
Operation With VCC = 3.3 V •Pin Compatible with TL16C752B (48-Pin
•Up to 16-MHz Clock Rate for up to 1-Mbaud Package PFB)
Operation With VCC = 2.5 V
•Up to 10-MHz Clock Rate for up to 625-kbaud APPLICATIONS
Operation With VCC = 1.8 V •Automotive Applications
•In the TL16C450 Mode, Hold and Shift •Point-of-Sale Terminals
Registers Eliminate the Need for Precise •Gaming Terminals
Synchronization Between the CPU and Serial •Portable Applications
Data •Router Control
•Programmable Baud Rate Generator Allows •Cellular Data
Division of Any Input Reference Clock by 1 to
(2 16 -1) and Generates an Internal 16 ×Clock •Factory Automation
•Standard Asynchronous Communication Bits DESCRIPTION
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream The TL16C2550 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
•5-V, 3.3-V, 2.5-V, and 1.8-V Operation functionality of two TL16C550D UARTs, each UART
•Independent Receiver Clock Input having its own register set and FIFOs. The two
•Transmit, Receive, Line Status, and Data Set UARTs share only the data bus interface and clock
Interrupts Independently Controlled source, otherwise they operate independently.
Another name for the uart function is Asynchronous
•Fully Programmable Serial Interface Communications Element (ACE), and these terms will
Characteristics: be used interchangeably. The bulk of this document
–5-, 6-, 7-, or 8-Bit Characters describes the behavior of each ACE, with the
–Even-, Odd-, or No-Parity Bit Generation understanding that two such devices are incorporated
into the TL16C2550.
and Detection
–1-, 1 1/2-, or 2-Stop Bit Generation
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
14 15
RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
1 1
12
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
NC
17 18 19 20
PFB PACKAGE
(TOP VIEW)
RIA
CDA
DSRA
CTSA
47 46 45 44 4348 42
D4
D3
D2
D1
D0
TXRDYA
RTSB
CTSB
NC
IOW
CDB
GND
IOR
DSRB
RIB
40 39 3841
21 22 23 24
37
13
XTAL1
NC
VCC
XTAL2
RXRDYB
TL16C2550PFB
TL16C2550-Q1
SLWS232 –DECEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode),
each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by
buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their
respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can significantly reduce software overload and increase system
efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input,
thus eliminating overruns in the receive FIFO.
Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and
stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on
data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status
of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt
system that can be tailored to the application.
Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors from
1 to 65535, thus producing a 16×internal reference clock for the transmitter and receiver logic. Each ACE
accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would
generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at
24 MHz.
Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.
NC - No internal connection
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Crystal
OSC
Buffer
Data Bus
Interface
A2 − A0
D7 − D0
CSA
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
RESET
XTAL1
XTAL2
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel A
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel B
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
VCC
GND
TXA
RXA
TXB
RXB
UART Regs
UART Regs
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
TL16C2550 Block Diagram
DEVICE INFORMATION
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME PFB NO.
A0 28 I Address 0 select bit. Internal registers address selection
A1 27 I Address 1 select bit. Internal registers address selection
A2 26 I Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low
CDA, CDB 40, 16 I on these pins indicates that a carrier has been detected by the modem for that channel. The state of
these inputs is reflected in the modem status register (MSR).
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
CSA, CSB 10, 11 I TL16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing
a low on the respective CSA and CSB pins.
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
CTSA, CTSB 38, 23 I 2550. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for
hardware flow control operation.
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or
D0-D4 44 -48 I/O from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
D5-D7 1 -3 serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A and B. A
DSRA, DSRB 39, 20 I logic low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART. The state of these inputs is reflected in the modem status register (MSR).
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PIN FUNCTIONS (continued)
PIN I/O DESCRIPTION
NAME PFB NO.
Data terminal ready (active low). These outputs are associated with individual UART channels A and
B. A logic low on these pins indicates that theTLl16C2550 is powered on and ready. These pins can
DTRA, DTRB 34, 35 O be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low,
enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.
GND 17 Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A
and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt
INTA, INTB 30, 29 O enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space or when a modem status flag is detected. INTA-B are in the
high-impedance state after reset.
Read input (active low strobe). A high to low transition on IOR will load the contents of an internal
IOR 19 I register defined by address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for access by an
external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the data
IOW 15 I bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and
CSA and CSB
12, 24, 25,
NC No internal connection
37 User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
OPA, OPB 32, 9 O active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and
RESET 36 I the receiver input will be disabled during reset time. See TL16C2550 external reset conditions for
initialization details. RESET is an active-high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
RIA, RIB 41, 21 I low to high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR)
Request to send (active low). These outputs are associated with individual UART channels A and B. A
low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the
modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset,
RTSA, RTSB 33, 22 O these pins are set to high. These pins only affects the transmit and receive operation when auto RTS
function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control
operation.
Receive data input. These inputs are associated with individual serial channel data to the 2550. During
RXA, RXB 5, 4 I the local loopback mode, these RX input pins are disabled and TX data is internally connected to the
UART RX input internally.
RXRDYA, Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a
31, 18 O
RXRDYB timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data from the
TXA, TXB 7, 8 O 2550. During the local loopback mode, the TX input pin is disabled and TX data is internally connected
to the UART RX input.
TXRDYA, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of
43, 6 O
TXRDYB spaces available. They go high when the TX buffer is full.
VCC 42 I Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
XTAL1 13 I crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 14). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator
XTAL2 14 O output or buffered a clock output.
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RCV
FIFO
Serial to
Parallel
Flow
Control
XMT
FIFO
Parallel
to Serial
Flow
Control
Parallel
to Serial
Flow
Control
Serial to
Parallel
Flow
Control
XMT
FIFO
RCV
FIFO
ACE1 ACE2
D7−D0
RX TX
RTS CTS
TX RX
CTS RTS
D7−D0
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
DETAILED DESCRIPTION
Autoflow Control (see Figure 1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and
notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-CTS (See Figure 2)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 1). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
Auto-RTS (See Figure 3 and Figure 4)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 2), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it
may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 3), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.
Enabling Autoflow Control and Auto-CTS
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1.
Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control
register should be cleared (this assumes that a control signal is driving CTS).
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Start Bits 0−7 Start Bits 0−7 Start Bits 0−7
Stop Stop Stop
SOUT
CTS
Start Byte N Start Byte N+1 Start Byte
Stop Stop Stop
SIN
RTS
RD
(RD RBR) 1 2 N N+1
Byte 14 Byte 15
SIN
RTS
RD
(RD RBR)
Start Byte 18 StopStart Byte 16 Stop
RTS Released After the
First Data Bit of Byte 16
TL16C2550-Q1
SLWS232 –DECEMBER 2011
www.ti.com
Auto-CTS and Auto-RTS Functional Timing
Figure 2. CTS Functional Timing Waveforms
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
RXA, B
TXA, B
CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B
OPA, B
INTA, B
38, 23
34, 35
39, 20
40, 16
41, 21
32, 9
30, 29
7, 8
5,4
A0 28
D(7−0)
3 −1
48−44
Internal
Data Bus
27
26
10
11
14
36
19
15
13
43
31
A1
A2
CSA
CSB
XTAL2
RESET
IOR
IOW
XTAL1
TXRDYA
RXRDYA
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
42
17
VCC
GND
Power
Supply
RTSA, B
33, 22
Autoflow
Control
(AFE)
8
8
8
8
8
8
8
6
18
TXRDYB
RXRDYB
Crystal
OSC
Buffer
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
A. Pin numbers shows are for 48-pin TQFP PFB package.
Figure 5. Functional Block Diagram
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SLWS232 –DECEMBER 2011
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ORDERING INFORMATION
TAPACKAGE ORDERABLE PART NAME TOP-SIDE MARKING
–40°C to 85°C TQFP - PFB Reel of 1000 TL16C2550IPFBRQ1 TL2550RQ
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) UNIT
VCC Supply voltage range, (2) –0.5 V to 7 V
VIInput voltage range at any input –0.5 V to 7 V
VOOutput voltage range –0.5 V to 7 V
TAOperating free-air temperature, TL16C2550 0°C to 70°C
TAOperating free-air temperature, TL16C2550I –40°C to 85°C
Tstg Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
Human Body Model (HBM) 2000 V
ESD Charged Device Model (CDM) 1000 V
Machine Model (MM) 150 V
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
1.8 V ±10%
VCC Supply voltage 1.62 1.8 1.98 V
VIInput voltage 0 VCC V
VIH High-level input voltage 1.4 1.98 V
VIL Low-level input voltage –0.3 0.4 V
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 0.5 mA
IOL Low-level output current (all outputs) 1 mA
Oscillator/clock speed 10 MHz
2.5 V ±10%
VCC Supply voltage 2.25 2.5 2.75 V
VIInput voltage 0 VCC V
VIH High-level input voltage 1.8 2.75 V
VIL Low-level input voltage –0.3 0.6 V
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 1 mA
IOL Low-level output current (all outputs) 2 mA
Oscillator/clock speed 16 MHz
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
3.3 V ±10%
VCC Supply voltage 3 2.5 2.75 V
VIInput voltage 0 VCC V
VIH High-level input voltage 0.7VCC V
0.3V
VIL Low-level input voltage V
CC
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 1.8 mA
IOL Low-level output current (all outputs) 3.2 mA
Oscillator/clock speed 20 MHz
5 V ±10%
VCC Supply voltage 4.5 5 5.5 V
VIInput voltage 0 VCC V
All except XTAL1, XTAL2 2 V
VIH High-level input voltage XTAL1, XTAL2 0.7VCC
All except XTAL1, XTAL2 0.8 V
VIL Low-level input voltage 0.3V
XTAL1, XTAL2 CC
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 4 mA
IOL Low-level output current (all outputs) 4 mA
Oscillator/clock speed 24 MHz
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
1.8 V NOMINAL
High-level output
VOH IOH =–0.5 mA 1.3 V
voltage(1)
VOL Low-level output voltage(2) IOL = 1 mA 0.5 V
IIInput current(3) VCC = 1.98 V, VSS = 0, VI= 0 to 1.98 V, All other terminals floating 10 µA
High-impedance-state VCC = 1.98 V, VSS = 0, VI= 0 to 1.98 V, Chip slected in write mode
IOZ ±20 µA
output current(3) or chip deselcted
VCC = 1.98 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current(3) CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at 0.4 V, 1.5 mA
XTAL1 at 10 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 1.8 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
2.5 V NOMINAL
High-level output
VOH IOH =–1 mA 1.8 V
voltage(2)(3)
Low-level output
VOL IOL = 2 mA 0.5 V
voltage(2)(3)
IIInput current VCC = 5.5 V, VSS = 0, VI= 0 to 2.75 V, All other terminals floating 10 µA
High-impedance-state VCC = 2.75 V, VSS = 0, VI= 0 to 2.75 V, Chip slected in write mode
IOZ ±20 µA
output current or chip deselcted
VCC = 2.75 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current(3) CTSA, CTSB, RIA, and RIB at 1.8 V, All other inputs at 0.6 V, 2.5 mA
XTAL1 at 16 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 2.5 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
3.3 V NOMINAL
High-level output
VOH IOH =–1.8 mA 2.4 V
voltage(2)
VOL Low-level output voltage(2) IOL = 3.2 mA 0.5 V
IIInput current VCC = 3.6 V, VSS = 0, VI= 0 to 3.6 V, All other terminals floating 10 µA
High-impedance-state VCC = 3.6 V, VSS = 0, VI= 0 to 3.6 V, Chip slected in write mode or
IOZ ±20 µA
output current chip deselcted
VCC = 3.6 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current(3) CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, 4 mA
XTAL1 at 20 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 3.3 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
5 V NOMINAL
High-level output
VOH IOH =–4 mA 4 V
voltage(2)
VOL Low-level output voltage(2) IOL = 4 mA 0.4 V
IIInput current VCC = 5.5 V, VSS = 0, VI= 0 to 5.5 V, All other terminals floating 10 µA
High-impedance-state VCC = 5.5 V, VSS = 0, VI= 0 to 5.5 V, Chip slected in write mode
IOZ ±20 µA
output current or chip deselcted
VCC = 5.5 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, 7.5 mA
XTAL1 at 24 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 5 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
1.8 V 2.5 V 3.3 V 5 V
ALT. TEST
PARAMETER FIGURE UNIT
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
tw8 Pulse duration, RESET tRESET 1 1 1 1 µs
tw1 Pulse duration, clock high tXH 6 40 25 20 18 ns
tw2 Pulse duration, clock low tXL 8 115 80 62 57 ns
tcR Cycle time, read (tw7 + td8 + th7) RC 8 115 80 62 57 ns
tcW Cycle time, write (tw6 + td5 + th4) WC 7 115 80 62 57 ns
tw6 Pulse duration, IOW tIOW 7 80 55 45 40 ns
tw7 Pulse duration, IOR tIOR 8 80 55 45 40 ns
tSU3 Setup time, data valid before IOW↑tDS 7 25 20 15 15 ns
th3 Hold time, CS valid after IOW↑tWCS 7 0 0 0 0 ns
th4 Hold time, address valid after IOW↑tWA 7 20 15 10 10 ns
th5 Hold time, data valid after IOW↑tDH 7 15 10 5 5 ns
th6 Hold time, chip select valid after IOR↑tRCS 8 0 0 0 0 ns
th7 Hold time, address valid after IOR↑tRA 8 20 15 10 10 ns
td4 Delay time, CS valid before IOW↓tCSW 7 0 0 0 0 ns
td5 Delay time, address valid before IOW↓tAW 7 15 10 7 7 ns
td7 Delay time, CS valid to IOR↓tCSR 8 0 0 0 0 ns
td8 Delay time, address valid to IOR↓tAR 8 15 10 7 7 ns
td10 Delay time, IOR↓to data valid tRVD 8 CL= 30 pF 55 35 25 20 ns
td11 Delay time, IOR↓to floating data tHZ 8 CL= 30 pF 40 30 20 20 ns
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RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
td12 Delay time, RCLK to sample tSCD 9 20 15 10 10 ns
Delay time, stop to set INT or read RBR to 8, 9, 10, RCLK
td13 tSINT 1 1 1 1
LSI interrupt or stop to RXRDY↓11, 12 cycle
8, 9, 10,
td14 Delay time, read RBR/LSR to reset INT tRINT CL= 30 pF 100 90 80 70 ns
11, 12
baudout
td26 Delay time, RCV threshold byte to RTS↑19 CL= 30 pF 2 cycles
Delay time, read of last byte in receive FIFO baudout
td27 19 CL= 30 pF 2
to RTS↓cycles
Delay time, first data bit of 16th character to baudout
td28 20 CL= 30 pF 2
RTS↑cycles
baudout
td29 Delay time, RBRRD low to RTS↓20 CL= 30 pF 2 cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
(2) Not production tested.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
baudout
td15 Delay time, initial write to transmit start tIRS 14 8 24 8 24 8 24 8 24 cycles
baudout
td16 Delay time, start to INT tSTI 14 8 10 8 10 8 10 10 cycles
td17 Delay time, IOW (WR THR) to reset INT tHR 14 CL= 30 pF 70 60 50 8 50 ns
baudout
td18 Delay time, initial write to INT (THRE(3)) tSI 14 16 34 16 34 16 34 16 34 cycles
Delay time, read IOR↑to reset INT
td19 tIR 14 CL= 30 pF 70 50 35 35 ns
(THRE(3))
td20 Delay time, write to TXRDY inactive tWXI 15, 16 CL= 30 pF 60 45 35 35 ns
baudout
td21 Delay time, start to TXRDY active tSXA 15, 16 CL= 30 pF 9 9 9 9 cycles
tSU4 Setup time, CTS↑before midpoint of stop bit 18 30 20 10 10 ns
baudout
td25 Delay time, CTS low to TX↓18 CL= 30 pF 24 24 24 24 cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
(2) Not production tested.
(3) THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (1)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT(2)
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
td22 Delay time, WR MCR to output tMDO 17 CL= 30 pF 90 70 60 50 ns
td23 Delay time, modem interrupt to set INT tSIM 17 CL= 30 pF 60 50 40 35 ns
td24 Delay time, RD MSR to reset INT tRIM 17 CL= 30 pF 80 60 50 40 ns
(1) Not production tested.
(2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
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f − Frequency − MHz
0.0
0.1
0.2
0.3
0.4
0.5
0 1 2 3 4 5 6 7 8 9 10
VCC = 1.8 V
TA= 22°C
ICC − Supply Current − mA
G001
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
f − Frequency − MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 2 4 6 8 10 12 14 16 18 20
VCC = 3.3 V
TA= 22°C
ICC − Supply Current − mA
G003
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
f − Frequency − MHz
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0 4 8 12 16 20 24
VCC = 5 V
TA= 22°C
ICC − Supply Current − mA
G004
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
tw1
XTALI
tw2
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SPACER TYPICAL CHARACTERISTICS
Figure 6. Figure 7.
Figure 8. Figure 9.
Figure 10. Clock Input
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tsu3 th5
Valid Data
Valid
A2−A0
D7−D0
50%50%
50% 50%
50%50%
IOW
CSA, CSB
td5
td4
tw6
th3
th4
td10 td11
Valid Data
Valid
A2−A0
D7−D0
50%50%
50% 50%
50%50%
IOR
CSA, CSB
td8
td7
th7
th6
tw7
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TYPICAL CHARACTERISTICS (continued)
Figure 11. Write Cycle Timing Waveforms
Figure 12. Read Cycle Timing Waveforms
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td13
Active
Active
IOR
(read RBR)
RCLK
(Internal)
td14
td14
td12
Parity StopStart Data Bits 5−8
Sample Clock
(Internal)
TL16C450 Mode:
Sample Clock
RXA, RXB
INT
(data ready)
INT
(RCV error)
IOR
(read LSR)
50%50%
50%
50% 50%
50%
8 CLKs
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TYPICAL CHARACTERISTICS (continued)
Figure 13. Receiver Timing Waveforms
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td13
(see Note A)
td14
Stop
Data Bits 5−8
Sample Clock
(Internal)
RXA, RXB
Trigger Level
INT
(FCR6, 7 = 0, 0)
INT
Line Status
Interrupt (LSI)
td14
IOR
(RD LSR)
IOR
(RD RBR)
Active
Active
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50%50%
50%
50%
50% 50%
td13
(see Note A) td14
Stop
Top Byte of FIFO
Sample Clock
(Internal)
RXA, RXB
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
td13
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOP
(RD LSR)
IOR
(RD RBR) Active Active
td14
Previous Byte
Read From FIFO
50%
50%
50%50%
50%
50% 50%
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TYPICAL CHARACTERISTICS (continued)
Figure 14. Receive First Byte (Sets DR Bit) Waveforms
Figure 15. Receive FIFO Bytes Other than the First Byte (DR Internal BIt already set) Waveforms
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