TL16C2550-Q1
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SLWS232 –DECEMBER 2011
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
Check for Samples: TL16C2550-Q1
1FEATURES
•Qualified for Automotive Applications –Baud Generation (DC to 1 Mbit/s)
•Programmable Auto-RTS and Auto-CTS •False-Start Bit Detection
•In Auto-CTS Mode, CTS Controls Transmitter •Complete Status Reporting Capabilities
•In Auto-RTS Mode, RCV FIFO Contents, and •3-State Output TTL Drive Capabilities for
Threshold Control RTS Bidirectional Data Bus and Control Bus
•Serial and Modem Control Outputs Drive a •Line Break Generation and Detection Internal
RJ11 Cable Directly When Equipment Is on the Diagnostic Capabilities:
Same Power Drop –Loopback Controls for Communications
•Capable of Running With All Existing Link Fault Isolation
TL16C450 Software –Break, Parity, Overrun, and Framing Error
•After Reset, All Registers Are Identical to the Simulation
TL16C450 Register Set •Fully Prioritized Interrupt System Controls
•Up to 24-MHz Clock Rate for up to 1.5-Mbaud •Modem Control Functions (CTS, RTS, DSR,
Operation With VCC = 5 V DTR, RI, and DCD)
•Up to 20-MHz Clock Rate for up to 1.25-Mbaud •Available in 48-Pin TQFP (PFB) Package
Operation With VCC = 3.3 V •Pin Compatible with TL16C752B (48-Pin
•Up to 16-MHz Clock Rate for up to 1-Mbaud Package PFB)
Operation With VCC = 2.5 V
•Up to 10-MHz Clock Rate for up to 625-kbaud APPLICATIONS
Operation With VCC = 1.8 V •Automotive Applications
•In the TL16C450 Mode, Hold and Shift •Point-of-Sale Terminals
Registers Eliminate the Need for Precise •Gaming Terminals
Synchronization Between the CPU and Serial •Portable Applications
Data •Router Control
•Programmable Baud Rate Generator Allows •Cellular Data
Division of Any Input Reference Clock by 1 to
(2 16 -1) and Generates an Internal 16 ×Clock •Factory Automation
•Standard Asynchronous Communication Bits DESCRIPTION
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream The TL16C2550 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
•5-V, 3.3-V, 2.5-V, and 1.8-V Operation functionality of two TL16C550D UARTs, each UART
•Independent Receiver Clock Input having its own register set and FIFOs. The two
•Transmit, Receive, Line Status, and Data Set UARTs share only the data bus interface and clock
Interrupts Independently Controlled source, otherwise they operate independently.
Another name for the uart function is Asynchronous
•Fully Programmable Serial Interface Communications Element (ACE), and these terms will
Characteristics: be used interchangeably. The bulk of this document
–5-, 6-, 7-, or 8-Bit Characters describes the behavior of each ACE, with the
–Even-, Odd-, or No-Parity Bit Generation understanding that two such devices are incorporated
into the TL16C2550.
and Detection
–1-, 1 1/2-, or 2-Stop Bit Generation
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
14 15
RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
1 1
12
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
NC
17 18 19 20
PFB PACKAGE
(TOP VIEW)
RIA
CDA
DSRA
CTSA
47 46 45 44 4348 42
D4
D3
D2
D1
D0
TXRDYA
RTSB
CTSB
NC
IOW
CDB
GND
IOR
DSRB
RIB
40 39 3841
21 22 23 24
37
13
XTAL1
NC
VCC
XTAL2
RXRDYB
TL16C2550PFB
TL16C2550-Q1
SLWS232 –DECEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode),
each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by
buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their
respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can significantly reduce software overload and increase system
efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input,
thus eliminating overruns in the receive FIFO.
Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and
stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on
data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status
of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt
system that can be tailored to the application.
Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors from
1 to 65535, thus producing a 16×internal reference clock for the transmitter and receiver logic. Each ACE
accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would
generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at
24 MHz.
Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.
NC - No internal connection
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Crystal
OSC
Buffer
Data Bus
Interface
A2 − A0
D7 − D0
CSA
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
RESET
XTAL1
XTAL2
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel A
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel B
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
VCC
GND
TXA
RXA
TXB
RXB
UART Regs
UART Regs
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
TL16C2550 Block Diagram
DEVICE INFORMATION
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME PFB NO.
A0 28 I Address 0 select bit. Internal registers address selection
A1 27 I Address 1 select bit. Internal registers address selection
A2 26 I Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low
CDA, CDB 40, 16 I on these pins indicates that a carrier has been detected by the modem for that channel. The state of
these inputs is reflected in the modem status register (MSR).
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
CSA, CSB 10, 11 I TL16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing
a low on the respective CSA and CSB pins.
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
CTSA, CTSB 38, 23 I 2550. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for
hardware flow control operation.
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or
D0-D4 44 -48 I/O from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
D5-D7 1 -3 serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A and B. A
DSRA, DSRB 39, 20 I logic low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART. The state of these inputs is reflected in the modem status register (MSR).
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PIN FUNCTIONS (continued)
PIN I/O DESCRIPTION
NAME PFB NO.
Data terminal ready (active low). These outputs are associated with individual UART channels A and
B. A logic low on these pins indicates that theTLl16C2550 is powered on and ready. These pins can
DTRA, DTRB 34, 35 O be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low,
enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.
GND 17 Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A
and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt
INTA, INTB 30, 29 O enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space or when a modem status flag is detected. INTA-B are in the
high-impedance state after reset.
Read input (active low strobe). A high to low transition on IOR will load the contents of an internal
IOR 19 I register defined by address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for access by an
external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the data
IOW 15 I bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and
CSA and CSB
12, 24, 25,
NC No internal connection
37 User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
OPA, OPB 32, 9 O active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and
RESET 36 I the receiver input will be disabled during reset time. See TL16C2550 external reset conditions for
initialization details. RESET is an active-high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
RIA, RIB 41, 21 I low to high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR)
Request to send (active low). These outputs are associated with individual UART channels A and B. A
low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the
modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset,
RTSA, RTSB 33, 22 O these pins are set to high. These pins only affects the transmit and receive operation when auto RTS
function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control
operation.
Receive data input. These inputs are associated with individual serial channel data to the 2550. During
RXA, RXB 5, 4 I the local loopback mode, these RX input pins are disabled and TX data is internally connected to the
UART RX input internally.
RXRDYA, Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a
31, 18 O
RXRDYB timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data from the
TXA, TXB 7, 8 O 2550. During the local loopback mode, the TX input pin is disabled and TX data is internally connected
to the UART RX input.
TXRDYA, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of
43, 6 O
TXRDYB spaces available. They go high when the TX buffer is full.
VCC 42 I Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
XTAL1 13 I crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 14). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator
XTAL2 14 O output or buffered a clock output.
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RCV
FIFO
Serial to
Parallel
Flow
Control
XMT
FIFO
Parallel
to Serial
Flow
Control
Parallel
to Serial
Flow
Control
Serial to
Parallel
Flow
Control
XMT
FIFO
RCV
FIFO
ACE1 ACE2
D7−D0
RX TX
RTS CTS
TX RX
CTS RTS
D7−D0
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
DETAILED DESCRIPTION
Autoflow Control (see Figure 1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and
notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-CTS (See Figure 2)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 1). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
Auto-RTS (See Figure 3 and Figure 4)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 2), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it
may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 3), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.
Enabling Autoflow Control and Auto-CTS
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1.
Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control
register should be cleared (this assumes that a control signal is driving CTS).
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Start Bits 0−7 Start Bits 0−7 Start Bits 0−7
Stop Stop Stop
SOUT
CTS
Start Byte N Start Byte N+1 Start Byte
Stop Stop Stop
SIN
RTS
RD
(RD RBR) 1 2 N N+1
Byte 14 Byte 15
SIN
RTS
RD
(RD RBR)
Start Byte 18 StopStart Byte 16 Stop
RTS Released After the
First Data Bit of Byte 16
TL16C2550-Q1
SLWS232 –DECEMBER 2011
www.ti.com
Auto-CTS and Auto-RTS Functional Timing
Figure 2. CTS Functional Timing Waveforms
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
RXA, B
TXA, B
CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B
OPA, B
INTA, B
38, 23
34, 35
39, 20
40, 16
41, 21
32, 9
30, 29
7, 8
5,4
A0 28
D(7−0)
3 −1
48−44
Internal
Data Bus
27
26
10
11
14
36
19
15
13
43
31
A1
A2
CSA
CSB
XTAL2
RESET
IOR
IOW
XTAL1
TXRDYA
RXRDYA
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
42
17
VCC
GND
Power
Supply
RTSA, B
33, 22
Autoflow
Control
(AFE)
8
8
8
8
8
8
8
6
18
TXRDYB
RXRDYB
Crystal
OSC
Buffer
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
A. Pin numbers shows are for 48-pin TQFP PFB package.
Figure 5. Functional Block Diagram
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SLWS232 –DECEMBER 2011
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ORDERING INFORMATION
TAPACKAGE ORDERABLE PART NAME TOP-SIDE MARKING
–40°C to 85°C TQFP - PFB Reel of 1000 TL16C2550IPFBRQ1 TL2550RQ
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) UNIT
VCC Supply voltage range, (2) –0.5 V to 7 V
VIInput voltage range at any input –0.5 V to 7 V
VOOutput voltage range –0.5 V to 7 V
TAOperating free-air temperature, TL16C2550 0°C to 70°C
TAOperating free-air temperature, TL16C2550I –40°C to 85°C
Tstg Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
Human Body Model (HBM) 2000 V
ESD Charged Device Model (CDM) 1000 V
Machine Model (MM) 150 V
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
1.8 V ±10%
VCC Supply voltage 1.62 1.8 1.98 V
VIInput voltage 0 VCC V
VIH High-level input voltage 1.4 1.98 V
VIL Low-level input voltage –0.3 0.4 V
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 0.5 mA
IOL Low-level output current (all outputs) 1 mA
Oscillator/clock speed 10 MHz
2.5 V ±10%
VCC Supply voltage 2.25 2.5 2.75 V
VIInput voltage 0 VCC V
VIH High-level input voltage 1.8 2.75 V
VIL Low-level input voltage –0.3 0.6 V
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 1 mA
IOL Low-level output current (all outputs) 2 mA
Oscillator/clock speed 16 MHz
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
3.3 V ±10%
VCC Supply voltage 3 2.5 2.75 V
VIInput voltage 0 VCC V
VIH High-level input voltage 0.7VCC V
0.3V
VIL Low-level input voltage V
CC
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 1.8 mA
IOL Low-level output current (all outputs) 3.2 mA
Oscillator/clock speed 20 MHz
5 V ±10%
VCC Supply voltage 4.5 5 5.5 V
VIInput voltage 0 VCC V
All except XTAL1, XTAL2 2 V
VIH High-level input voltage XTAL1, XTAL2 0.7VCC
All except XTAL1, XTAL2 0.8 V
VIL Low-level input voltage 0.3V
XTAL1, XTAL2 CC
VOOutput voltage 0 VCC V
IOH High-level output current (all outputs) 4 mA
IOL Low-level output current (all outputs) 4 mA
Oscillator/clock speed 24 MHz
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
1.8 V NOMINAL
High-level output
VOH IOH =–0.5 mA 1.3 V
voltage(1)
VOL Low-level output voltage(2) IOL = 1 mA 0.5 V
IIInput current(3) VCC = 1.98 V, VSS = 0, VI= 0 to 1.98 V, All other terminals floating 10 µA
High-impedance-state VCC = 1.98 V, VSS = 0, VI= 0 to 1.98 V, Chip slected in write mode
IOZ ±20 µA
output current(3) or chip deselcted
VCC = 1.98 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current(3) CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at 0.4 V, 1.5 mA
XTAL1 at 10 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 1.8 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
2.5 V NOMINAL
High-level output
VOH IOH =–1 mA 1.8 V
voltage(2)(3)
Low-level output
VOL IOL = 2 mA 0.5 V
voltage(2)(3)
IIInput current VCC = 5.5 V, VSS = 0, VI= 0 to 2.75 V, All other terminals floating 10 µA
High-impedance-state VCC = 2.75 V, VSS = 0, VI= 0 to 2.75 V, Chip slected in write mode
IOZ ±20 µA
output current or chip deselcted
VCC = 2.75 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current(3) CTSA, CTSB, RIA, and RIB at 1.8 V, All other inputs at 0.6 V, 2.5 mA
XTAL1 at 16 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 2.5 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
3.3 V NOMINAL
High-level output
VOH IOH =–1.8 mA 2.4 V
voltage(2)
VOL Low-level output voltage(2) IOL = 3.2 mA 0.5 V
IIInput current VCC = 3.6 V, VSS = 0, VI= 0 to 3.6 V, All other terminals floating 10 µA
High-impedance-state VCC = 3.6 V, VSS = 0, VI= 0 to 3.6 V, Chip slected in write mode or
IOZ ±20 µA
output current chip deselcted
VCC = 3.6 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current(3) CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, 4 mA
XTAL1 at 20 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 3.3 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
5 V NOMINAL
High-level output
VOH IOH =–4 mA 4 V
voltage(2)
VOL Low-level output voltage(2) IOL = 4 mA 0.4 V
IIInput current VCC = 5.5 V, VSS = 0, VI= 0 to 5.5 V, All other terminals floating 10 µA
High-impedance-state VCC = 5.5 V, VSS = 0, VI= 0 to 5.5 V, Chip slected in write mode
IOZ ±20 µA
output current or chip deselcted
VCC = 5.5 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
ICC Supply current CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, 7.5 mA
XTAL1 at 24 MHz, No load on outputs
Ci(CLK) Clock input impedance(3) 15 20 pF
CO(CLK) Clock output impedance(3) 20 30 pF
VCC = 0, VSS = 0, f = 1 MHz, TA= 25°C, All other terminals
grounded
CIInput impedance(3) 6 10 pF
COOutput impedance(3) 10 20 pF
(1) All typical values are at VCC = 5 V and TA= 25°C.
(2) These parameters apply for all outputs except XTAL2.
(3) Not production tested.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
1.8 V 2.5 V 3.3 V 5 V
ALT. TEST
PARAMETER FIGURE UNIT
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
tw8 Pulse duration, RESET tRESET 1 1 1 1 µs
tw1 Pulse duration, clock high tXH 6 40 25 20 18 ns
tw2 Pulse duration, clock low tXL 8 115 80 62 57 ns
tcR Cycle time, read (tw7 + td8 + th7) RC 8 115 80 62 57 ns
tcW Cycle time, write (tw6 + td5 + th4) WC 7 115 80 62 57 ns
tw6 Pulse duration, IOW tIOW 7 80 55 45 40 ns
tw7 Pulse duration, IOR tIOR 8 80 55 45 40 ns
tSU3 Setup time, data valid before IOW↑tDS 7 25 20 15 15 ns
th3 Hold time, CS valid after IOW↑tWCS 7 0 0 0 0 ns
th4 Hold time, address valid after IOW↑tWA 7 20 15 10 10 ns
th5 Hold time, data valid after IOW↑tDH 7 15 10 5 5 ns
th6 Hold time, chip select valid after IOR↑tRCS 8 0 0 0 0 ns
th7 Hold time, address valid after IOR↑tRA 8 20 15 10 10 ns
td4 Delay time, CS valid before IOW↓tCSW 7 0 0 0 0 ns
td5 Delay time, address valid before IOW↓tAW 7 15 10 7 7 ns
td7 Delay time, CS valid to IOR↓tCSR 8 0 0 0 0 ns
td8 Delay time, address valid to IOR↓tAR 8 15 10 7 7 ns
td10 Delay time, IOR↓to data valid tRVD 8 CL= 30 pF 55 35 25 20 ns
td11 Delay time, IOR↓to floating data tHZ 8 CL= 30 pF 40 30 20 20 ns
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RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
td12 Delay time, RCLK to sample tSCD 9 20 15 10 10 ns
Delay time, stop to set INT or read RBR to 8, 9, 10, RCLK
td13 tSINT 1 1 1 1
LSI interrupt or stop to RXRDY↓11, 12 cycle
8, 9, 10,
td14 Delay time, read RBR/LSR to reset INT tRINT CL= 30 pF 100 90 80 70 ns
11, 12
baudout
td26 Delay time, RCV threshold byte to RTS↑19 CL= 30 pF 2 cycles
Delay time, read of last byte in receive FIFO baudout
td27 19 CL= 30 pF 2
to RTS↓cycles
Delay time, first data bit of 16th character to baudout
td28 20 CL= 30 pF 2
RTS↑cycles
baudout
td29 Delay time, RBRRD low to RTS↓20 CL= 30 pF 2 cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
(2) Not production tested.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
baudout
td15 Delay time, initial write to transmit start tIRS 14 8 24 8 24 8 24 8 24 cycles
baudout
td16 Delay time, start to INT tSTI 14 8 10 8 10 8 10 10 cycles
td17 Delay time, IOW (WR THR) to reset INT tHR 14 CL= 30 pF 70 60 50 8 50 ns
baudout
td18 Delay time, initial write to INT (THRE(3)) tSI 14 16 34 16 34 16 34 16 34 cycles
Delay time, read IOR↑to reset INT
td19 tIR 14 CL= 30 pF 70 50 35 35 ns
(THRE(3))
td20 Delay time, write to TXRDY inactive tWXI 15, 16 CL= 30 pF 60 45 35 35 ns
baudout
td21 Delay time, start to TXRDY active tSXA 15, 16 CL= 30 pF 9 9 9 9 cycles
tSU4 Setup time, CTS↑before midpoint of stop bit 18 30 20 10 10 ns
baudout
td25 Delay time, CTS low to TX↓18 CL= 30 pF 24 24 24 24 cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
(2) Not production tested.
(3) THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (1)
LIMITS
ALT. TEST
PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT(2)
SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX
td22 Delay time, WR MCR to output tMDO 17 CL= 30 pF 90 70 60 50 ns
td23 Delay time, modem interrupt to set INT tSIM 17 CL= 30 pF 60 50 40 35 ns
td24 Delay time, RD MSR to reset INT tRIM 17 CL= 30 pF 80 60 50 40 ns
(1) Not production tested.
(2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
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f − Frequency − MHz
0.0
0.1
0.2
0.3
0.4
0.5
0 1 2 3 4 5 6 7 8 9 10
VCC = 1.8 V
TA= 22°C
ICC − Supply Current − mA
G001
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
f − Frequency − MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 2 4 6 8 10 12 14 16 18 20
VCC = 3.3 V
TA= 22°C
ICC − Supply Current − mA
G003
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
f − Frequency − MHz
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0 4 8 12 16 20 24
VCC = 5 V
TA= 22°C
ICC − Supply Current − mA
G004
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
tw1
XTALI
tw2
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
SPACER TYPICAL CHARACTERISTICS
Figure 6. Figure 7.
Figure 8. Figure 9.
Figure 10. Clock Input
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tsu3 th5
Valid Data
Valid
A2−A0
D7−D0
50%50%
50% 50%
50%50%
IOW
CSA, CSB
td5
td4
tw6
th3
th4
td10 td11
Valid Data
Valid
A2−A0
D7−D0
50%50%
50% 50%
50%50%
IOR
CSA, CSB
td8
td7
th7
th6
tw7
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TYPICAL CHARACTERISTICS (continued)
Figure 11. Write Cycle Timing Waveforms
Figure 12. Read Cycle Timing Waveforms
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td13
Active
Active
IOR
(read RBR)
RCLK
(Internal)
td14
td14
td12
Parity StopStart Data Bits 5−8
Sample Clock
(Internal)
TL16C450 Mode:
Sample Clock
RXA, RXB
INT
(data ready)
INT
(RCV error)
IOR
(read LSR)
50%50%
50%
50% 50%
50%
8 CLKs
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SLWS232 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
Figure 13. Receiver Timing Waveforms
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td13
(see Note A)
td14
Stop
Data Bits 5−8
Sample Clock
(Internal)
RXA, RXB
Trigger Level
INT
(FCR6, 7 = 0, 0)
INT
Line Status
Interrupt (LSI)
td14
IOR
(RD LSR)
IOR
(RD RBR)
Active
Active
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50%50%
50%
50%
50% 50%
td13
(see Note A) td14
Stop
Top Byte of FIFO
Sample Clock
(Internal)
RXA, RXB
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
td13
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOP
(RD LSR)
IOR
(RD RBR) Active Active
td14
Previous Byte
Read From FIFO
50%
50%
50%50%
50%
50% 50%
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TYPICAL CHARACTERISTICS (continued)
Figure 14. Receive First Byte (Sets DR Bit) Waveforms
Figure 15. Receive FIFO Bytes Other than the First Byte (DR Internal BIt already set) Waveforms
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td13
(see Note B) td14
Stop
Sample Clock
(Internal)
RXA, RXB
(first byte)
Active
IOR
(RD RBR)
RXRDYA, RXRDYB
See Note A
50%
50%
50%
td13
(see Note B) td14
Sample Clock
(Internal)
RXA, RXB
(first byte that reaches
the trigger level)
Active
IOR
(RD RBR)
RXRDYA, RXRDYB
See Note A
50%
50%50%
td16
Parity Stop
Start
Data Bits
TXA, TXB
Start
td15
td17 td17
td18
td19
INT
(THRE)
IOW
(WR THR)
IOR
50% 50% 50% 50% 50%
50%
50%
50%
50%
50%
50%
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SLWS232 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
Figure 16. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 17. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 and FCR3 = 1 (Mode 1)
Figure 18. Transmitter Timing Waveforms
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td20
IOW
(WR THR)
td21
Parity Stop
Data
Start
Byte 1
TXA, TXB
TXRDYA, TXRDYB
50%
50%
50%
50%
IOW
(WR THR)
Parity Stop
Data
Start
Byte 16
TXA, TXB
TXRDYA, TXRDYB FIFO Full
td20 td21
50%
50%
50%
50%
IOW
(WR MCR)
RTSA, RTSB, DTRA,
DTRB, OPA, OPB
CTSA, CTSB, DSRA,
DSRB, CDA, CDB
td23
td24
td23
INT
(modem)
IOR
(RD MSR)
RI
50% 50%
50% 50%
50%
50% 50%
50%
50%
50%
td22
td22
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SLWS232 –DECEMBER 2011
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TYPICAL CHARACTERISTICS (continued)
Figure 19. Tranceiver Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 20. Tranceiver Ready (TXRDY) Waveforms, FCR0 = 0 and FCR3 = 1 (Mode 1)
Figure 21. Modem Control Timing Waveforms
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Midpoint of Stop Bit
td25
tsu4
CTSA, CTSB
TXA, TXB
50% 50%
50%
td27
RXA, RXB
50%
td26
50%
50%
Midpoint of Stop Bit
RTSA,
RTSB
IOR
RXA,
RXB
50%
td28
50%
50%
Midpoint of Data Bit 0
RTSA,
RTSB
IOR
15th Character 16th Character
td29
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SLWS232 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
Figure 22. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Figure 23. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Figure 24. Auto-RTS Timing for RCV Threshold of 14 Waveforms
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D7−D0
MEMR or I/OR
MEMW or I/OW
INTR
RESET
A0
A1
A2
CS
EIA-232-D
Drivers
and Receivers
XTAL2
XTAL1
RIA, B
CTSA, B
CDA, B
DSRA, B
DTRA, B
RTSA, B
TXA, B
RXA, B
INTA, B
D7−D0
IOR
IOW
RESET
A0
A1
A2
CSA, B
TL16C2550
3.072 MHz
C
P
U
B
u
s
(Optional)
33 pF
33 pF
TL16C2550-Q1
SLWS232 –DECEMBER 2011
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APPLICATION INFORMATION
Figure 25. Basic TL16C2550 Configuration
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Buffer
(Optional)
Address
Decoder
A0−A23
D0−D15
RSI/ABT
PHI1 PHI2
PHI1 PHI2
CPU
RSTO
A0−A2
CSA
CSB
RESET
D0−D7
D0−D7
IOR
IOW
XTAL1
XTAL2
DTRA, B
RTSA, B
RIA, B
CDA, B
DSRA, B
CTSA, B
RXA, B
TXA, B
INTA, B
GND
(VSS)VCC
17 42
TL16C2550
EIA-232-D
Connector
20
1
8
6
5
2
3
7
1
14
15
34, 35
33, 22
41, 21
40, 16
39, 20
38, 23
5, 4
30, 29
7, 8
15
19
36
10
11
TCU
WR
RD
(Optional)
33 pF
33 pF
TL16C2550-Q1
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SLWS232 –DECEMBER 2011
Figure 26. Typical TL16C2550 Connection
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PRINCIPLES OF OPERATION
REGISTER SELECTION
Table 1. Register Selection
DLAB (1) A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
(1) The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 2).
Table 2. ACE Reset Functions
REGISTER/SIGNAL RESET CONTROL RESET STATE
All bits cleared (0–3 forced and 4–7
Interrupt enable register Master reset permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Interrupt identification register Master reset and bits 4–5 are permanently cleared
FIFO control register Master reset All bits cleared
Line control register Master reset All bits cleared
Modem control register Master reset All bits cleared (6 -7 permanent)
Line status register Master reset Bits 5 and 6 are set; all other bits are cleared
Bits 0–3 are cleared; bits 4–7 are input
Modem status register Master reset signals
TX Master reset High
INT Master reset, MCR3 Output buffer tristated
Interrupt condition (receiver error flag) Read LSR/MR Low
Interrupt condition (received data available) Read RBR/MR Low
Interrupt condition (transmitter holding Read IIR/write THR/MR Low
register empty)
Interrupt condition (modem status changes) Read MSR/MR Low
OP Master reset High
RTS Master reset High
DTR Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) registers Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect
RCVR FIFO MR/FCR1 –FCR0/DFCR0 All bits cleared
XMIT FIFO MR/FCR2 –FCR0/DFCR0 All bits cleared
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Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
DLAB = 0 DLAB = 1
0 0 1 2 2 3 4 5 6 7 0 1
BIT Transmitter Interrupt FIFO
Receiver
NO. Holding Interrupt Ident Control Line Modem Line Divisor Divisor
Buffer Modem Status Scratch
Register Enable Register Register Control Control Status Latch Latch
Register Register Register
(Write Register (Read (WriteOnl Register Register Register (LSB) (MSB)
(Read Only) Only) Only) y)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
Enable Word
0 if Data
Received Data FIFO Length Data Terminal Delta Clear to
0 Data Bit 0(1) Data Bit 0 Interrupt Ready Bit 0 Bit 0 Bit 8
Available Enable Select Bit 0 Ready (DTR) Send (ΔCTS)
Pending (DR)
Interrupt (ERBI) (WLS0)
Enable
Transmitter Word
Receiver
Holding Interrupt Length Request to Overrun Delta Data Set
1 Data Bit 1 Data Bit 1 FIFO Bit 1 Bit 1 Bit 9
Register Empty ID Bit 1 Select Bit 1 Send (RTS) Error (OE) Ready (ΔDSR)
Reset
Interrupt (WLS1)
(ETBEI)
Enable Transmitte Number of Trailing Edge
Receiver Line Interrupt Parity
2 Data Bit 2 Data Bit 2 r FIFO Stop Bits OUT1 Ring Indicator Bit 2 Bit 2 Bit 10
Status Interrupt ID Bit 2 Error (PE)
Reset (STB) (TERI)
(ELSI)
Enable Modem DMA Parity OUT2,
Interrupt Framing Delta Data Carrier
3 Data Bit 3 Data Bit 3 Status Interrupt Mode Enable OPcontrol, INT Bit 3 Bit 3 Bit 11
ID Bit 3(2) Error (FE) Detect (ΔDCD)
(EDSSI) Select (PEN) Enable
Even Parity Break Clear to Send
4 Data Bit 4 Data Bit 4 0 0 Reserved Select Loop Interrupt Bit 4 Bit 4 Bit 12
(CTS)
(EPS) (BI)
Transmitte
Autoflow r Holding Data Set Ready
5 Data Bit 5 Data Bit 5 0 0 Reserved Stick Parity Control Enable Bit 5 Bit 5 Bit 13
Register (DSR)
(AFE) (THRE)
Receiver Transmitte
FIFOs Break Ring Indicator
6 Data Bit 6 Data Bit 6 0 Trigger 0 r Empty Bit 6 Bit 6 Bit 14
Enabled(2) Control (RI)
(LSB) (TEMT)
Divisor
Receiver Error in
FIFOs Latch Data Carrier
7 Data Bit 7 Data Bit 7 0 Trigger 0 RCVR Bit 7 Bit 7 Bit 15
Enabled(2) Access Bit Detect (DCD)
(MSB) FIFO(2)
(DLAB)
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
•Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
•Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
•Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
•Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
•Bits 4 and 5: These two bits are reserved for future use.
•Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).
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Table 4. Receiver FIFO Trigger Level
BIT 7 BIT 6 RECEIVER FIFO TRIGGER LEVEL (BYTES)
0 0 01
0 1 04
1 0 08
1 1 14
FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It
is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. FIFO time-out interrupt occurs if the following conditions exist:
(a) At least one character is in the FIFO.
(b) The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).
(c) The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of 160
ms at a 300-baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to
the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register empty interrupt [IIR (3 -0) = 2] occurs when the transmit FIFO is empty. It is
cleared [IIR (3 -0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that
the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
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FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Because the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
•LSR0 is set as long as one byte is in the receiver FIFO.
•LSR1 -LSR 4 specify which error(s) have occurred. Character error status is handled the same way as when
in the interrupt mode; the IIR is not affected since IER2 = 0.
•LSR5 indicates when the THR is empty.
•LSR6 indicates that both the THR and TSR are empty.
•LSR7 indicates whether any errors are in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the
receiver and transmitter FIFOs are still fully capable of holding characters.
Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of
this register are summarized in Table 3 and are described in the following bullets.
•Bit 0: When set, this bit enables the received data available interrupt.
•Bit 1: When set, this bit enables the THRE interrupt.
•Bit 2: When set, this bit enables the receiver line status interrupt.
•Bit 3: When set, this bit enables the modem status interrupt.
•Bits 4 through 7: These bits are not used (always cleared).
Interrupt Identification Register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with the
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
•Priority 1 -Receiver line status (highest priority)
•Priority 2 -Receiver data ready or receiver character time-out
•Priority 3 -Transmitter holding register empty
–Priority 4 -Modem status (lowest priority)
–When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of
interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in
Table 3 and described in Table 5. Detail on each bit is as follows:
•Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending. If bit 0 is set, no interrupt is pending.
•Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3.
•Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
•Bits 4 and 5: These two bits are not used (always cleared).
•Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
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Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION PRIORITY INTERRUPT
REGISTER INTERRUPT SOURCE INTERRUPT RESET METHOD
LEVEL TYPE
BIT BIT BIT 1 BIT 0
3 2
0 0 0 1 None None None None
Receiver line Overrun error, parity error, framing
0 1 1 0 1 Read the line status register
status error, or break interrupt
Receiver data available in the
Received data
0 1 0 0 2 TL16C450 mode or trigger level Read the receiver buffer register
available reached in the FIFO mode
No characters have been removed
Character from or input to the receiver FIFO
1 1 0 0 2 time-out during the last four character times, Read the receiver buffer register
indication and there is at least one character
in it during this time Read the interrupt identification
Transmitter register (if source of interrupt) or
0 0 1 0 3 holding register Transmitter holding register empty writing into the transmitter holding
empty register
Clear to send, data set ready, ring
0 0 0 0 4 Modem status Read the modem status register
indicator, or data carrier detect
Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
•Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
BIT 1 BIT 0 WORD LENGTH
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
•Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7.
Table 7. Number of Stop Bits Generated
BIT 2 Word Length Selectedby Bits 1 and 2 Number of Stop Bits Generated
0 Any word length 1
1 5 bits 1 1/2
1 6 bits 2
1 7 bits 2
1 8 bits 2
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•Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
•Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.
•Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5
is cleared, stick parity is disabled.
•Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where TX is
forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effect
on the transmitter logic; it only effects TX.
•Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer,
the THR, or the IER.
NOTE
The line status register is intended for read operations only; writing to this register is not
recommended outside of a factory testing environment.
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and described in the following bulleted list.
•Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
NOTE
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
•Bit 1: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time
the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger
level, an overrun error occurs only after the FIFO is full, and the next character has been completely received
in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift
register is overwritten, but it is not transferred to the FIFO.
•Bit 2: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data
character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the
contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
•Bit 3: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character did
not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO
mode, this error is associated with the particular character in the FIFO to which it applies. This error is
revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize
after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The
ACE samples this start bit twice and then accepts the input data.
•Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was
held low for longer than a full-word transmission time. A full-word transmission time is defined as the total
time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of
the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a
break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after RX
goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
•Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to
accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE
is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading
of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when
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at least one byte is written to the transmit FIFO.
•Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.
•Bit 7: In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least
one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there
are no subsequent errors in the FIFO.
Modem Control Register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
•Bit 0: This bit (DTR) controls the DTR output.
•Bit 1: This bit (RTS) controls the RTS output.
•Bit 2: This bit (OUT1) is reserved for output and can also be used for loopback mode.
•Bit 3: This bit (OUT2) controls the high-impedance state output buffer for the INT signal and the OP output.
When low, the INT signal is in a high-impedance state and OP is high. When high, the INT signal is enabled
and OP is low.
•Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,
the following occurs:
–The transmitter TX is set high.
–The receiver RX is disconnected.
–The output of the TSR is looped back into the receiver shift register input.
–The four modem control inputs (CTS, DSR, CD, and RI) are disconnected.
–The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
–The four modem control outputs are forced to the inactive (high) levels.
•Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed
description is enabled. In the diagnostic mode, data that is transmitted is immediately received. This allows
the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts
are fully operational. The modem control interrupts are also operational, but the modem control interrupt's
sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are
still controlled by the IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
Table 8. ACE Flow Configuration
MCR BIT 5 (AFE) MCR BIT 1 (RTS) ACE FLOW CONFIGURATION
1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled)
1 0 Auto-CTS only enabled
0 X Auto-RTS and auto-CTS disabled
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Modem Status Register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
•Bit 0: This bit is the change in clear-to-send (ΔCTS) indicator. ΔCTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When ΔCTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled (ΔCTS is cleared), no interrupt is generated.
•Bit 1: This bit is the change in data set ready (ΔDSR) indicator. ΔDSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When ΔDSR is set and the modem status interrupt
is enabled, a modem status interrupt is generated.
•Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the
chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
•Bit 3: This bit is the change in data carrier detect (ΔDCD) indicator. ΔDCD indicates that the DCD input to the
chip has changed state since the last time it was read by the CPU. When ΔDCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
•Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
•Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
•Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
•Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
Programmable Baud Generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (216 -1). The output frequency of the baud generator is
sixteen times (16 ×) the baud rate. The formula for the divisor is:
divisor = XIN frequency input P (desired baud rate ×16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072
MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clock
circuits).
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Table 9. Baud Rates Using a 1.8432-MHz Crystal
PERCENT ERROR
DIVISOR USED TO GENERATE
DESIRED BAUD RATE DIFFERENCE BETWEEN
16×CLOCK DESIRED AND ACTUAL
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 10. Baud Rates Using a 3.072-MHz Crystal
PERCENT ERROR
DIVISOR USED TO GENERATE
DESIRED BAUD RATE DIFFERENCE BETWEEN
16×CLOCK DESIRED AND ACTUAL
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
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Figure 27. Typical Clock Circuits
Table 11. Typical Crystal Oscillator Network
Crystal R PRX2 (Optional) C1 C2
3.072 MHz 1 MΩ1.5 kΩ10–30 pF 40–60 pF
1.8432 MHz 1 MΩ1.5 kΩ10–30 pF 40–60 pF
16 MHz 1 MΩ0 kΩ33 pF 33 pF
Receiver Buffer Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is derived from the input clock divided by the programmed devisor. Receiver section control is a
function of the ACE line control register.
The ACE RSR receives serial data from RX. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
Scratch Register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.
Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is derived from the input clock divided by the programmed devisor. Transmitter section
control is a function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at TX. In the TL16C450 mode, if the THR is empty and the transmitter
holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared
when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control
setup in the FIFO control register.
Table 12. Typical Package Thermal Resistance Data
PACKAGE WEIGHT IN GRAMS
48-Pin TQFP PFB θJA = 50.1°C/W θJC = 21.1°C/W 0.2
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PACKAGE OPTION ADDENDUM
www.ti.com 30-Dec-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TL16C2550IPFB ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IPFBRQ1 ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IRHB ACTIVE QFN RHB 32 73 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IRHBG4 ACTIVE QFN RHB 32 73 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550PFB ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550PFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550PFBR ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550PFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550RHB ACTIVE QFN RHB 32 73 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550RHBG4 ACTIVE QFN RHB 32 73 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550RHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C2550RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 30-Dec-2011
Addendum-Page 2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL16C2550, TL16C2550-Q1 :
•Catalog: TL16C2550
•Automotive: TL16C2550-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL16C2550IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TL16C2550IPFBRQ1 TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TL16C2550IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TL16C2550PFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TL16C2550RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL16C2550IPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TL16C2550IPFBRQ1 TQFP PFB 48 1000 367.0 367.0 38.0
TL16C2550IRHBR QFN RHB 32 3000 338.1 338.1 20.6
TL16C2550PFBR TQFP PFB 48 1000 367.0 367.0 38.0
TL16C2550RHBR QFN RHB 32 3000 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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