317
TM 82C86H
CMOS Octal Bus Transceiver
FN2977.1
March 1997
Features
• Full Eight Bit Bi-Di rectional Bus Interface
• Industr y Standard 8286 Compatibl e Pinout
• High Drive Capability
-B Side I
OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
-A Side I
OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
• Three-State Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max .
• Gated Inputs
- Redu ce Op erating Power
- Eliminate the Need for Pull -Up Resistors
• Single 5V Power Supply
• L o w Power O per a tio n . . . . . . . . . . . . . . . ICC SB = 10µA
• Operating Temperature Range
- C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- I82C86H. . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C8 6H. . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
CMO S pro ces s ( S caled SAJI IV). The 82C86H pro vides a f ull
eight-bit bi-directional bus interface in a 20 lead package. The
Transmit (T) control determines the data direction. The active
lo w outp ut enab l e (OE ) perm its sim pl e inte rface to the 80C86,
80C88 and other microprocessors. The 82C86H has gated
inputs, eliminating the need for pull-up/pull-down resistors and
redu cin g ov era ll system o per at ing power di ssipati on.
Ordering Information
PART NUM BER PACK-
AGE TEMP. RANGE PKG.
NO.5MHz 8MHz
CP 82C86H-5 CP 82C86H 20 Ld
PDIP 0oC to +70oCE20.3
IP82C86H-5 IP82C86H -40oC to +85oCE20.3
CS 82C86H-5 CS 82C86H 20 Ld
PLCC 0oC to +70oCN20.35
IS82C86H-5 IS82C86H -40oC to +85oCN20.35
CD82C86H-5 CD82C86H 20 Ld
CERDIP 0oC to +70oCF20.3
ID82C86H-5 ID82C86H -40oC to +85oCF20.3
MD82C86H-5/B - -55oC to
+125oCF20.3
5962-
8757701RA - SMD # F20.3
MR82C86H-5/B - 20 Pad
CLCC -55oC to
+125oCJ20.A
5962-
87577012A -SMD # J20.A
CA UTION: The se devices are s ensi tiv e to elec trost atic dis char ge; follow proper IC Handling Procedur es.
1-888-INTERSIL or 321-724-7143 |Intersil (and de sign) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
318
Pinouts
82C86H (PDIP, CERDIP)
TOP VIEW 82C86H (PLCC, CLCC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
A0
A1
A2
A3
A4
A5
A7
A6
OE
GND
VCC
B1
B2
B3
B0
B4
B5
B6
B7
T
193 2 201
15
16
17
18
14
910 11 12 13
4
5
6
7
8
A4
A5
A6
A7
A3
OE
GND
T
B7
B6
B2
B3
B4
B5
B1
A2
A1
A0
VCC
B0
TRUTH TABLE
TOEAB
X H Hi-Z Hi-Z
HL IO
LLOI
H = Logic One
L = Logic Ze ro
I = Input Mode
O = Output Mode
X = Don’t Care
Hi- Z = Hig h I m pe da nc e
PIN NAMES
PIN DESCRIPTION
A0-A7Local Bus Data I/O Pins
B0-B7System Bus Data I /O Pins
T Transmit Control Input
OE Active Low O utput En able
82C86H82C86H
319
82C86H
Functional Diag ram
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input switch-
ing threshol d. Additionally, i f t he driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operati on.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the dev ice is
disabled (OE = logic one for the 82C86H/87H). These gated
input s disco nnect the input c ircui try f rom the VCC and gro und
power supply pins by turning off the upper P-channel and
lower N-cha nnel (See Figures 1 and 2). No cur rent flow from
VCC to GND occurs during input transitions and invalid logic
states from floating inputs are not transmitted. The next
stage is held to a valid logic level inter nal to the devic e.
D.C. input voltage levels can also cause an increase in ICC
if these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion w ill occ ur onl y durin g the tim e the de vic e is in the tra ns-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipat ion of the 82C8X ser ies devices.
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C86H/87H data
sheet is determi ned by:
Assum ing that al l outputs change state at the same ti m e and
that dv/dt is constant;
where tR = 20n s, VCC = 5.0V, CL = 300pF on eac h eight out-
puts.
This current spike may cause a large negative voltage spike
on VCC which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1µF
ceramic disc capaci tor be placed between VCC and GND at
each device, with placement being as near to the device as
possible.
T
B7
B6
B5
B4
B3
B2
B1
B0
A0
A1
A2
A3
A4
A5
A6
A7
OE
IC
Ldv dt⁄()=(EQ. 1)
IC
LVCC 80%×()
tR tF⁄
-------------------------------------= (EQ. 2)
I 80 300 10 12–
××()5.0V 0.8×()20 10 9–
×()⁄×=480mA=(EQ. 3)
STB
DATA IN
VCC
P
N
VCC
INTERNAL
DATA
P
P
N
N
FIGURE 1. 82C82/83H
DATA IN INTERNAL
DATA
VCC
VCC
N
N
P
P
P
N
OE
FIGURE 2. 82C8 6H/87H GATED INPUTS
82C86H
320
Absolute Maximum Ratin gs Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Ope rat i ng Conditio ns
Operating Volta ge Ra nge. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82 C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
I82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 70 16
CLCC Package . . . . . . . . . . . . . . . . . . 80 20
PDIP Package. . . . . . . . . . . . . . . . . . . 75 N/A
PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A
Maximum Storage Temperature Range . . . . . . . . . -65oC to +150oC
Maximum Junction Temperature Hermetic Package . . . . . . +175oC
Maximum Junction Tempe rature Plastic Package . . . . . . . . +150oC
Maximum Le ad Temperature (Soldering 10s). . . . . . . . . . . . +300oC
(PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied.
DC Electrical Specifications VCC = 5.0V ± 10 %; TA = 0oC to +70oC (C82C86H);
TA = -40oC to +85oC (I82C86H);
TA = -55oC to +125oC (M82C86H)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
VIH Logical One 2.0 - V C82C8 6H, I82C86H
Input Voltage 2.2 V M82C86H (Note 1)
VIL Logical Zero Input Voltage - 0.8 V
VOH Logical One Output Voltage
B Outp uts 3.0 V IOH = -8mA
A Outp uts 3.0 V IOH = -4mA
A or B Outputs VCC -0.4 V IOH = -100µA
VOL Logical Zero Ou tput Voltage
B Outp uts 0.45 V IOL = 20m A
A Outp uts 0.45 V IOL = 12m A
IIInput Leakage Current -10 .0 10.0 µAV
IN = GND or VCC DIP Pins 9, 11
IO Ou tput Le ak ag e Current -1 0. 0 10.0 µA VO = GND or VCC, OE Š Š≥ VCC -0.5V
DIP Pin s 1 - 8, 12 - 19
ICCSB Sta ndby Powe r Supply
Current -10µAV
IN = VCC or GND, V CC = 5.5V, Outputs Open
ICCOP Operating Power Su pply
Current -1mA/MHzT
A = +25oC, Typical (See Note 2 )
NOTES:
1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data in put at a time and che cking the co rr esponding device output
for a valid logical “1” during valid input high time. Control pins (T, OE) are tested sep arately with all device data input pins at VCC -0.4
2. Typical ICCOP = 1mA/ MHz of read/ cycle time. (Exa mple: 1.0µs read/write cycle time = 1mA).
Capacitance TA = +25oC
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance
B Inputs 18 pF Freq = 1MHz, all measurem ents are
referenced to device GND
A Inputs 14 pF
82C86H82C86H
321
Timing Waveform
AC Electrical Specifications VCC = 5.0V ± 10%; TA = 0oC to +70oC (C82C86H);
Freq = 1MH z TA = -40oC to +85oC (I82C86H);
TA = -55oC to +125oC (M82C86H)
SYMBOL PARAMETER MIN
NOTE 4
UNITS TEST CONDITIONS
82C86H
MAX 82C86H-5
MAX
(1) TIVOV Input to Output Delay Notes 1, 2
Inverting 5 30 35 ns
Non-Inverting 5 32 35 ns
(2) TEHTV Transmit/Receive Hold Time 5 - - ns Notes 1, 2
(3) TTVEL Transmit/Receive Setup Time 10 - - ns Notes 1, 2
(4) TEHOZ Output Disable Time 5 30 35 ns Notes 1, 2
(5) TELOV Output Enable Time 10 50 65 ns Notes 1, 2
(6) TR, TF Input Rise/Fall Times - 20 20 ns Notes 1, 2
(7) TEHEL Mi nimum Output Enable High Time Note 3
82C86H 30 - - ns
82C86H-5 35 - - ns
NOTES:
1. All AC parameters tested as per test circuits and de finitions in timing waveforms and test load circuits. Input rise and fall times are driven
at 1ns/V.
2. Input tes t si gnal s mu st sw itc h be t ween VIL - 0.4V and VIH +0 .4V.
3. A system limitation only when changing direction. Not a measured parameter.
4. 82C86H is available in commercial and industrial temperature ranges only. 82C86H-5 is available in commercial, industrial and military
temperature ranges.
NOTE: All timing measurements are mad e at 1.5V un less otherw ise no ted.
INPUTS
TR, TF (6)
2.0V
0.8V
VOH -0.1V
TELOV (5)
VOL +0.1V
TTVEL (3)
3.0V
0.45V
OUTPUTS
T
TEHEL (7)
TIVOV
(1) TEHOZ
(4)
TEHTV (2)
OE
82C86H82C86H
322
Test Lo ad Circu its
A SIDE OUTPUTS
TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH
ENABLE LOAD CIRCUIT TELOV OUTPUT LOW
ENABLE LOAD CIRCUIT TEHOZ OUTPUT LOW/HIGH
DISABLE LOAD CIRCUIT
B SIDE OUTPUTS
TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH
ENABLE LOAD CIRCUIT TELOV OUTPUT LOW
ENABLE LOAD CIRCUIT TEHOZ OUTPUT LOW/HIGH
DISABLE LOAD CIRCUIT
NOTE: Includes jig and stray capacitance.
Burn-In Circuits
MD82C86H CERDIP
OUTPUT TEST
POINT
2.36V
100pF
160Ω
(SEE NOTE)
OUTPUT TEST
POINT
1.5V
100pF
375Ω
(SEE NOTE)
OUTPUT TEST
POINT
1.5V
100pF
91Ω
(SEE NOTE)
OUTPUT TEST
POINT
2.36V
50pF
160Ω
(SEE NOTE)
OUTPUT TEST
POINT
2.27V
300pF
91Ω
(SEE NOTE)
OUTPUT TEST
POINT
1.5V
300pF
180Ω
(SEE NOTE)
OUTPUT TEST
POINT
1.5V
300pF
51Ω
(SEE NOTE)
OUTPUT TEST
POINT
2.27V
50pF
91Ω
(SEE NOTE)
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
VCC
F2 R1
F2
F2
F2
F2
F2
F2
F2
A
A
A
A
A
A
A
A
R1 VCC
C1
R2
VCC
A
R1
R1
R1
R1
R1
R1
R1
R1
R3
82C86H82C86H
323
MR82C86H CLCC
NOTES:
1. VCC = 5.5V ± 0. 5V, GND = 0V
2. VIH = 4.5V ± 10%
3. VIL = -0.2V to 0.4V
4. R1 = 47kΩ ± 5%
5. R2 = 2.4kΩ ± 5%
6. R3 = 1.5kΩ ± 5%
7. R4 = 1kΩ ± 5%
8. R5 = 5kΩ ± 5%
9. C1 = 0.01µF minimum
10. F0 = 100kHz ± 10%
11. F1 = F0/2, F2 = F1/2, F3 = F2/2
Burn-In Circuits (C ont inu ed)
4
5
6
7
8
910111213
15
14
18
17
16
VCC C1
F2 F2
R5
F2
R5 R5
F3
R5
F1F0 F3
F2
F2
F2
F2
F2
R5
R5
R5
R5
R5
F3
F3
F3
F3
F3
R5
R5
R5
R5
R5
R4R4 R5R5
F3
3212019
82C86H82C86H
324
All Intersil U.S. pro ducts are manufactured, assembled and test ed utilizing ISO9000 quali ty systems.
Intersil Corporati on’s quali ty certifi cations can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For informat ion regarding Inter sil Corporati on and its produc ts, see www.i ntersil.com
Die Charact eris tics
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
1.47 x 10 5 A/cm2
Metallization Mask Layout
82C86H
A2 A1 A0 VCC B0 B1
B2
B3
B4
B5
B6B7TGNDOEA7
A6
A5
A4
A3
82C86H82C86H
