MCIMX537CVV8CR2 - NXP SEMICONDUCTORS

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: IMX53IEC

Rev. 7, 05/2015

MCIMX53xC

Package Information

Plastic Package

Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch

Ordering Information

See Table 1 on page 2

1 Introduction

The i.MX53 processor features ARM Cortex™-A8

core, which operates at clock speeds as high as

800 MHz. It provides DDR2/LVDDR2-800,

LPDDR2-800, or DDR3-800 DRAM memories.

The flexibility of the i.MX53 architecture allows for its

use in a wide variety of applications. As the heart of the

application chipset, the i.MX53 processor provides all

the interfaces for connecting peripherals, such as

WLAN, Bluetooth™, GPS, hard drive, camera sensors,

and dual displays.

Features of the i.MX53 processor include the following:

• Applications processor—The i.MX53xD

processors boost the capabilities of high-tier

portable applications by satisfying the ever

increasing MIPS needs of operating systems and

games. Freescale’s Dynamic Voltage and

Frequency Scaling (DVFS) provides significant

power reduction, allowing the device to run at

lower voltage and frequency with sufficient

MIPS for tasks such as audio decode.

i.MX53 Applications

Processors for Industrial

Products

Silicon Version 2.1

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Functional Part Differences and Ordering

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1. Special Signal Considerations . . . . . . . . . . . . . . . 16

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16

4.2. Power Supply Requirements and Restrictions . . . 23

4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4. Output Buffer Impedance Characteristics . . . . . . 32

4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 43

4.7. External Peripheral Interfaces Parameters . . . . . 65

4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 141

5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 142

5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 142

5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 143

5.3. Power Setup During Boot . . . . . . . . . . . . . . . . . . 144

6. Package Information and Contact Assignments . . . . . 145

6.1. 19x19 mm Package Information . . . . . . . . . . . . . 145

7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

i.MX53 Applications Processors for Industrial Products, Rev. 7

2Freescale Semiconductor

Introduction

• Multilevel memory system—The multilevel memory system of the i.MX53 is based on the L1

instruction and data caches, L2 cache, internal and external memory. The i.MX53 supports many

types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3, NOR

Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND

including eMMC up to rev 4.4.

• Smart speed technology—The i.MX53 device has power management throughout the IC that

enables the rich suite of multimedia features and peripherals to consume minimum power in both

active and various low power modes. Smart speed technology enables the designer to deliver a

feature-rich product requiring levels of power far lower than industry expectations.

• Multimedia powerhouse—The multimedia performance of the i.MX53 processor ARM core is

boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision

floating point support) and vector floating point coprocessors. The system is further enhanced by

a multi-standard hardware video codec, autonomous image processing unit (IPU), and a

programmable smart DMA (SDMA) controller.

• Powerful graphics acceleration— The i.MX53 processors provide two independent, integrated

graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s,

and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator

(200 Mpix/s).

• Interface flexibility—The i.MX53 processor supports connection to a variety of interfaces,

including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go

with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed

MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces

(PATA, UART, I2C, and I2S serial audio, among others).

• Advanced security—The i.MX53 processors deliver hardware-enabled security features that

enable secure e-commerce, digital rights management (DRM), information encryption, secure

boot, and secure software downloads. For detailed information about the i.MX53 security features

contact a Freescale representative.

The i.MX53 application processor is a follow-on to the i.MX51, with improved performance, power

efficiency, and multimedia capabilities.

1.1 Functional Part Differences and Ordering Information

shows the functional differences between the different parts in the i.MX53 family.

Table 1 provides ordering information.

Table 1. Ordering Information

Part Number Mask Set CPU Frequency Notes Package1

1Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.

MCIMX537CVV8C 3N78C 800 MHz — 19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

Introduction

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 3

1.2 Features

The i.MX53 multimedia applications processor (AP) is based on the ARM Platform, which has the

following features:

• MMU, L1 instruction and L1 data cache

• Unified L2 cache

• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz

• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)

coprocessor supporting VFPv3

• TrustZone

The memory system consists of the following components:

• Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

• Level 2 cache:

— Unified instruction and data (256 Kbyte)

• Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

• External memory interfaces:

— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

— 32-bit LPDDR2

— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC

— 8/16-bit NOR Flash, PSRAM, and cellular RAM.

— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.

— 8-bit Asynchronous (DTACK mode) EIM interface.

— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects

EIM port, as primary muxing at system boot.

— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O

mode)

The i.MX53 system is built around the following system on chip interfaces:

• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,

GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.

• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.

• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral

devices operating at 66 MHz.

i.MX53 Applications Processors for Industrial Products, Rev. 7

4Freescale Semiconductor

Introduction

The i.MX53 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia

performance. The use of hardware accelerators provides both high performance and low power

consumption while freeing up the CPU core for other tasks.

The i.MX53 incorporates the following hardware accelerators:

• VPU, version 3—video processing unit

• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and

800 Mpix/s z-plane performance, 256 Kbyte RAM memory

• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,

• IPU, version 3M—image processing unit

• ASRC—asynchronous sample rate converter

The i.MX53 includes the following interfaces to external devices:

NOTE

Not all interfaces are available simultaneously, depending on I/O

multiplexer configuration.

• Hard disk drives:

— PATA, up to U-DMA mode 5, 100 MB/s

— SATA II, 1.5 Gbps

•Displays:

— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two

interfaces may be active at once.

— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,

UXGA at 60 Hz).

— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel

ports up to 85 MP/s (for example, WXGA at 60 Hz) each.

— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).

• Camera sensors:

— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up

to 120-MHz peak clock frequency.

• Expansion cards:

— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port

supporting 832 Mbps (8-bit, eMMC 4.4).

•USB

— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY

— Three USB 2.0 (480 Mbps) hosts:

– High-speed host with integrated on-chip high-speed PHY

– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB

• Miscellaneous interfaces:

— One-wire (OWIRE) port

Introduction

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 5

— Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer

(AUDMUX) providing four external ports.

— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support

4-wire.

— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port

— Three I2C ports, supporting 400 kbps

— Fast Ethernet controller, designed to be compliant with IEEE1588 V1, 10/100 Mbps

— Two controller area network (FlexCAN) interfaces, 1 Mbps each

— Sony Phillips Digital Interface (SPDIF), Rx and Tx

— Key pad port (KPP)

— Two pulse-width modulators (PWM)

— GPIO with interrupt capabilities

The system supports efficient and smart power control and clocking:

• Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes

• Power gating SRPG (State Retention Power Gating) for ARM core and Neon

• Support for various levels of system power modes

• Flexible clock gating control scheme

• On-chip temperature monitor

• On-chip oscillator amplifier supporting 32.768 kHz external crystal

• On-chip LDO voltage regulators for PLLs

Security functions are enabled and accelerated by the following hardware/features:

• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so

on)

• Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or

blocking the access to the system debug features

• Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and

mechanism to detect voltage and clock glitches

• Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine

• SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator

(TRNG)

• Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure

RAM and support for multiple keys as well as TZ/non-TZ separation

• Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is

configured during boot by eFUSEs, and determines the security level operation mode as well as

the TrustZone (TZ) policy

• Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

• Tamper detection mechanism—Provides evidence of any physical attempt to remove the device

cover. Upon detection of such an attack, sensitive information can immediately be erased.

i.MX53 Applications Processors for Industrial Products, Rev. 7

6Freescale Semiconductor

Architectural Overview

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX53 processor system.

2.1 Block Diagram

Figure 1 shows the functional modules in the i.MX53 processor system.

Figure 1. i.MX53 System Block Diagram

NOTE

The numbers in brackets indicate number of module instances. For example,

PWM (2) indicates two separate PWM peripherals.

Application Processor

Smart DMA

(SDMA)

Shared Peripherals

AP Peripherals

ARM Cortex A8

Platform

Timers

CSPI

UART (4)

GPT

PWM (2)

EPIT (2)

GPIOx32 (7)

WDOG (2)

OWIRE

C(3)

IOMUXC

IIM

AUDMUX

KPP

Boot

ROM

SSI (2)

RTICv3

SCCv2

SRTC

CSU

Fuse Box

Debug

DAP

TPIU

FIRI

SAHARAv4

Lite

Security

TZIC

Image Processing

USB OTG +

3 HS Ports

CTI (2) ECSPI

Internal

USB PHY2

USB PHY1

External

Memory I/F

RAM

144 KB

Subsystem

(IPU)

TV-EncoderLDB

LCD

Display-1,2

Domain (AP)

Composite CVBS/ S-Video

Component RGB, YCC

(HD TV-Out / VGA)

SJC

Neon, VFPv3

L2 cache 256 KB

ETM, CTI0,1

L1 I/D cache

IrDA

XVR WLAN USB OTG

(dev/host)

JTAG

(IEEE1149.1)

Bluetooth

Keypad Access.

Conn.

MMC/SD

eMMC/eSD

GPS

RF/IF

RF / IF

IC’s

Audio,

Power

Mngmnt.

SPBA

FlexCAN (2)

Digital

Audio

CAN i/f

eSDHCv2 (3)

UART

SPDIF Rx/Tx

ASRC

Video

Proc. Unit

(VPU)

3D Graphics

Proc. Unit

(GPU3D)

G-Memory

256 KB

2D Graphics

Proc. Unit

(

GPU2D

)

AXI and AHB Switch Fabric

LVDS

(WSXGA+)

Battery Ctrl

Device

NOR/NAND

Flash

Ethernet

10/100

Mbps

FEC

(IEEE1588)

Camera

(2)

64 KB

Clock and Reset

PLL (4)

CCM

GPC

SRC

XTALOSC(2)

CAMP (2)

Temperature

Sensor

eSDHCv3

Camera

(2)

(EXTMC)

LCD

Display (2)

SSI

ECSPI

ESAI

P-ATA

SATA

+ Temp Mon

SATA /

P-ATA

HDD

DDR2/DDR3/

LPDDR2

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 7

3 Modules List

The i.MX53 processor contains a variety of digital and analog modules. Table 2 describes these modules

in alphabetical order.

Table 2. i.MX53 Digital and Analog Blocks

Block

Mnemonic Block Name Subsystem Brief Description

ARM ARM Platform ARM The ARM CortexTM A8 platform consists of the ARM processor version r2p5

(with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte L1

instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a

256 Kbyte L2 cache. The platform also contains an event monitor and

debug modules. It also has a NEON coprocessor with SIMD media

processing architecture, a register file with 32/64-bit general-purpose

registers, an integer execute pipeline (ALU, Shift, MAC), dual

single-precision floating point execute pipelines (FADD, FMUL), a load/store

and permute pipeline and a non-pipelined vector floating point (VFP Lite)

coprocessor supporting VFPv3.

ASRC Asynchronous

Sample Rate

Converter

Multimedia

Peripherals

The asynchronous sample rate converter (ASRC) converts the sampling

rate of a signal associated to an input clock into a signal associated to a

different output clock. The ASRC supports concurrent sample rate

conversion of up to 10 channels of about -120 dB THD+N. The sample rate

conversion of each channel is associated to a pair of incoming and outgoing

sampling rates. The ASRC supports up to three sampling rate pairs.

AUDMUX Digital Audio

Multiplexer

Multimedia

Peripherals

The AUDMUX is a programmable interconnect for voice, audio, and

synchronous data routing between host serial interfaces (for example, SSI1,

SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs).

The AUDMUX has seven ports (three internal and four external) with

identical functionality and programming models. A desired connectivity is

achieved by configuring two or more AUDMUX ports.

CAMP-1

CAMP-2

Clock Amplifier Clocks,

Resets, and

Power Control

Clock amplifier

CCM

GPC

SRC

Clock Control

Module

Global Power

Controller

System Reset

Controller

Clocks,

Resets, and

Power Control

These modules are responsible for clock and reset distribution in the

system, as well as for system power management.

The system includes four PLLs.

CSPI

ECSPI-1

ECSPI-2

Configurable

SPI, Enhanced

CSPI

Connectivity

Peripherals

Full-duplex enhanced synchronous serial interface, with data rates

16-60 Mbit/s. It is configurable to support master/slave modes. In Master

mode it supports four slave selects for multiple peripherals.

CSU Central Security

Unit

Security The central security unit (CSU) is responsible for setting comprehensive

security policy within the i.MX53 platform, and for sharing security

information between the various security modules. The security control

registers (SCR) of the CSU are set during boot time by the high assurance

boot (HAB) code and are locked to prevent further writing.

i.MX53 Applications Processors for Industrial Products, Rev. 7

8Freescale Semiconductor

Modules List

DEBUG Debug System System

Control

The debug system provides real-time trace debug capability of both

instructions and data. It supports a trace protocol that is an integral part of

the ARM Real Time Debug solution (RealView).

Real-time tracing is controlled by specifying a set of triggering and filtering

resources, which include address and data comparators, three

cross-system triggers (CTI), counters, and sequencers.

debug access port (DAP)— The DAP provides real-time access for the

debugger without halting the core to system memory, peripheral register,

debug configuration registers and JTAG scan chains.

EXTMC External Memory

Controller

Connectivity

Peripherals

The EXTMC is an external and internal memory interface. It performs

arbitration between multi-AXI masters to multi-memory controllers, divided

into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel,

slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel,

internal memory (RAM, ROM) channel and graphical memory (GMEM)

channel.

In order to increase the bandwidth performance, the EXTMC separates the

buffering and the arbitration between different channels so parallel

accesses can occur. By separating the channels, slow accesses do not

interfere with fast accesses.

EXTMC Features:

• 64-bit and 32-bit AXI ports

• Enhanced arbitration scheme for fast channel, including dynamic master

priority, and taking into account which pages are open or closed and what

type (read or write) was the last access

• Flexible bank interleaving

• Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2.

• Support up to 2 GByte DDR memories.

• Support NFC, EIM signal muxing scheme.

• Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async

operating modes), at slow frequency. (8-bit is not supported on

D[23]-D[16]).

• Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB

Nand-Flash (including MLC)

• Multiple chip selects (up to 4).

• Enhanced DDR memory controller, supporting access latency hiding

• Support watermark for security (internal and external memories)

EPIT-1

EPIT-2

Enhanced

Periodic Interrupt

Timer

Peripherals

Each EPIT is a 32-bit “set and forget” timer that starts counting after the

EPIT is enabled by software. It is capable of providing precise interrupts at

regular intervals with minimal processor intervention. It has a 12-bit

prescaler for division of input clock frequency to get the required time setting

for the interrupts to occur, and counter values can be programmed on the fly.

ESAI Enhanced Serial

Audio Interface

Connectivity

Peripherals

The enhanced serial audio interface (ESAI) provides a full-duplex serial port

for serial communication with a variety of serial devices, including

industry-standard codecs, SPDIF transceivers, and other processors.

The ESAI consists of independent transmitter and receiver sections, each

section with its own clock generator.

The ESAI has 12 pins for data and clocking connection to external devices.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 9

ESDHCV3-3 Ultra-High-

Speed eMMC /

SD Host

Controller

Connectivity

Peripherals

Ultra high-speed eMMC / SD host controller, enhanced to support eMMC

4.4 standard specification, for 832 MBps.

• Port 3 is specifically enhanced to support eMMC 4.4 specification, for

double data rate (832 Mbps, 8-bit port).

ESDHCV3 is backward compatible to ESDHCV2 and supports all the

features of ESDHCV2 as described below.

ESDHCV2-1

ESDHCV2-2

ESDHCv2-4

Enhanced

Multi-Media Card

Secure Digital

Host Controller

Enhanced multimedia card / secure digital host controller

• Ports 1, 2, and 4 are compatible with the “MMC System Specification”

version 4.3, full support and supporting 1, 4 or 8-bit data.

The generic features of the eSDHCv2 module, when serving as SD / MMC

host, include the following:

• Can be configured either as SD / MMC controller

• Supports eSD and eMMC standard, for SD/MMC embedded type cards

• Conforms to SD Host Controller Standard Specification, version 2.0, full

support.

• Compatible with the SD Memory Card Specification, version 1.1

• Compatible with the SDIO Card Specification, version 1.2

• Designed to work with SD memory, miniSD memory, SDIO, miniSDIO,

SD Combo, MMC and MMC RS cards

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full/high speed mode.

• Host clock frequency variable between 32 kHz to 52 MHz

• Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data

lines

• Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines

FEC Fast Ethernet

Controller

Connectivity

Peripherals

The Ethernet media access controller (MAC) is designed to support both

10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external

transceiver interface and transceiver function are required to complete the

interface to the media. The i.MX53 also consists of HW assist for

IEEE1588™ standard. See, TSU and CE_RTC (IEEE1588) section for more

details.

FIRI Fast Infrared

Interface

Connectivity

Peripherals

Fast infrared interface

FLEXCAN-1

FLEXCAN-2

Flexible

Controller Area

Network

Connectivity

Peripherals

The controller area network (CAN) protocol was primarily, but not

exclusively, designed to be used as a vehicle serial data bus. Meets the

following specific requirements of this application: real-time processing,

reliable operation in the EXTMC environment of a vehicle,

cost-effectiveness and required bandwidth. The FLEXCAN is a full

implementation of the CAN protocol specification, Version 2.0 B (ISO

11898), which supports both standard and extended message frames at

1Mbps.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

10 Freescale Semiconductor

Modules List

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPIO-5

GPIO-6

GPIO-7

General Purpose

I/O Modules

System

Control

Peripherals

These modules are used for general purpose input/output to external ICs.

Each GPIO module supports up to 32 bits of I/O.

GPT General Purpose

Timer

Peripherals

Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a

programmable prescaler and compare and capture register. A timer counter

value can be captured using an external event, and can be configured to

trigger a capture event on either the leading or trailing edges of an input

pulse. When the timer is configured to operate in “set and forget” mode, it is

capable of providing precise interrupts at regular intervals with minimal

processor intervention. The counter has output compare logic to provide the

status and interrupt at comparison. This timer can be configured to run either

on an external clock or on an internal clock.

GPU3D Graphics

Processing Unit

Multimedia

Peripherals

The GPU, version 3, provides hardware acceleration for 2D and 3D graphics

algorithms with sufficient processor power to run desk-top quality interactive

graphics applications on displays up to HD1080 resolution. It supports color

representation up to 32 bits per pixel. GPU enables high-performance

mobile 3D and 2D vector graphics at rates up to 33 Mtriangles/s,

200 Mpix/s, 800 Mpix/s (z).

GPU2D Graphics

Processing

Unit-2D

Multimedia

Peripherals

The GPU2D version 1, provides hardware acceleration for 2D graphic

algorithms with sufficient processor power to run desk-top quality interactive

graphics applications on displays up to HD1080 resolution.

I2C-1

I2C-2

I2C-3

I2C Controller Connectivity

Peripherals

I2C provides serial interface for controlling peripheral devices. Data rates of

up to 400 kbps are supported.

IIM IC Identification

Module

Security The IC identification module (IIM) provides an interface for reading,

programming, and/or overriding identification and control information stored

in on-chip fuse elements. The module supports electrically programmable

poly fuses (e-Fuses). The IIM also provides a set of volatile

software-accessible signals that can be used for software control of

hardware elements not requiring non-volatility. The IIM provides the primary

user-visible mechanism for interfacing with on-chip fuse elements. Among

the uses for the fuses are unique chip identifiers, mask revision numbers,

cryptographic keys, JTAG secure mode, boot characteristics, and various

control signals requiring permanent non-volatility. The IIM also provides up

to 28 volatile control signals. The IIM consists of a master controller, a

software fuse value shadow cache, and a set of registers to hold the values

of signals visible outside the module.

IIM interfaces to the electrical fuse array (split to banks). Enabled to set up

boot modes, security levels, security keys and many other system

parameters.

i.MX53A consists of 4 x 256-bit + 1 x 128-bit fuse-banks (total 1152 bits)

through IIM interface.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 11

IOMUXC IOMUX Control System

Control

Peripherals

This module enables flexible I/O multiplexing. Each I/O pad has default as

well as several alternate functions. The alternate functions are software

configurable.

IPU Image

Processing Unit

Multimedia

Peripherals

Version 3M IPU enables connectivity to displays, relevant processing and

synchronization. It supports two display ports and two camera ports, through

the following interfaces:

• Legacy parallel interfaces

• Single/dual channel LVDS display interface

• Analog TV or VGA interfaces

The processing includes:

• Image enhancement—color adjustment and gamut mapping, gamma

correction and contrast enhancement

• Video/graphics combining

• Support for display backlight reduction

• Image conversion—resizing, rotation, inversion and color space

conversion

• Hardware de-interlacing support

• Synchronization and control capabilities, allowing autonomous operation.

KPP Keypad Port Connectivity

Peripherals

The KPP supports an 8 ×8 external keypad matrix. The KPP features are

as follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LDB LVDS Display

Bridge

Connectivity

Peripherals

LVDS display bridge is used to connect the IPU (image processing unit) to

external LVDS display interface. LDB supports two channels; each channel

has following signals:

• 1 clock pair

•4 data pairs

On-chip differential drivers are provided for each pair.

OWIRE One-Wire

Interface

Connectivity

Peripherals

One-wire support provided for interfacing with an on-board EEPROM, and

smart battery interfaces, for example, Dallas DS2502.

PATA Parallel ATA Connectivity

Peripherals

The PATA block is a AT attachment host interface. Its main use is to interface

with hard disk drives and optical disc drives. It interfaces with the ATA-6

compliant device over a number of ATA signals. It is possible to connect a

bus buffer between the host side and the device side.

PWM-1

PWM-2

Pulse Width

Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images. It can also generate

tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate

sound.

INTRAM Internal RAM Internal

Memory

Internal RAM, shared with VPU.

The on-chip memory controller (OCRAM) module, is an interface between

the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is

used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.

BOOTROM Boot ROM Internal

Memory

Supports secure and regular boot modes.

The ROM controller supports ROM patching.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

12 Freescale Semiconductor

Modules List

RTIC Run-Time

Integrity Checker

Security Protecting read only data from modification is one of the basic elements in

trusted platforms. The run-time integrity checker, version 3 (RTIC) block is

a data-monitoring device responsible for ensuring that the memory content

is not corrupted during program execution. The RTIC mechanism

periodically checks the integrity of code or data sections during normal OS

run-time execution without interfering with normal operation. The purpose of

the RTIC is to ensure the integrity of the peripheral memory contents,

protect against unauthorized external memory elements replacement and

assist with boot authentication.

SAHARA SAHARA

Security

Accelerator

Security SAHARA (symmetric/asymmetric hashing and random accelerator),

version 4, is a security coprocessor. It implements symmetric encryption

algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA

and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and

a hardware true random number generator. It has a slave IP Bus interface

for the host to write configuration and command information, and to read

status information. It also has a DMA controller, with an AHB bus interface,

to reduce the burden on the host to move the required data to and from

memory.

SATA Serial ATA Connectivity

Peripherals

SATA HDD interface, includes the SATA controller and the PHY. It is a

complete mixed-signal IP solution for SATA HDD connectivity.

SCCv2 Security

Controller, ver. 2

Security The security controller is a security assurance hardware module designed

to safely hold sensitive data, such as encryption keys, digital right

management (DRM) keys, passwords and biometrics reference data. The

SCCv2 monitors the system’s alert signal to determine if the data paths to

and from it are secure, that is, it cannot be accessed from outside of the

defined security perimeter. If not, it erases all sensitive data on its internal

RAM. The SCCv2 also features a key encryption module (KEM) that allows

non-volatile (external memory) storage of any sensitive data that is

temporarily not in use. The KEM utilizes a device-specific hidden secret key

and a symmetric cryptographic algorithm to transform the sensitive data into

encrypted data.

SDMA Smart Direct

Memory Access

System

Control

Peripherals

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

system performance by off loading various cores in dynamic data routing.

The SDMA features list is as follows:

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA

channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM and SDMA

• Very fast context-switching with two-level priority-based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement,

and no address changes on source and destination address)

• DMA ports can handle unidirectional and bidirectional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers to / from the EXTMC

• Support of byte swapping and CRC calculations

• A library of scripts and API is available

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 13

SECRAM Secure /

Non-secure RAM

Internal

Memory

Secure / non-secure Internal RAM, controlled by SCC.

SJC Secure JTAG

Interface

System

Control

Peripherals

JTAG manipulation is a known hacker’s method of executing unauthorized

program code, getting control over secure applications, and running code in

privileged modes. The JTAG port provides a debug access to several

hardware blocks including the ARM processor and the system bus.

The JTAG port must be accessible during platform initial laboratory bring-up,

manufacturing tests and troubleshooting, as well as for software debugging

by authorized entities. However, in order to properly secure the system,

unauthorized JTAG usage should be strictly forbidden.

In order to prevent JTAG manipulation while allowing access for

manufacturing tests and software debugging, the i.MX53 processor

incorporates a mechanism for regulating JTAG access. SJC provides four

different JTAG security modes that can be selected through an e-fuse

configuration.

SPBA Shared

Peripheral Bus

Arbiter

System

Control

Peripherals

SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP

bus) arbiter.

SPDIF Sony Philips

Digital Interface

Multimedia

Peripherals

A standard digital audio transmission protocol developed jointly by the Sony

and Philips corporations. Both transmitter and receiver functionalists are

supported.

SRTC Secure Real

Time Clock

Security The SRTC incorporates a special system state retention register (SSRR)

that stores system parameters during system shutdown modes. This

NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized separately

even if all other supply rails are shut down. This register is helpful for storing

warm boot parameters. The SSRR also stores the system security state. In

case of a security violation, the SSRR mark the event (security violation

indication).

SSI-1

SSI-2

SSI-3

I2S/SSI/AC97

Interface

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface used on the i.MX53A

processor to provide connectivity with off-chip audio peripherals. The SSI

interfaces connect internally to the AUDMUX for mapping to external ports.

The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,

and AC-97), bit depths (up to 24 bits per word), and clock/frame sync

options.

Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an

external DMA controller in order to minimize its impact on system

performance. The second pair of FIFOs provides hardware interleaving of a

second audio stream, which reduces CPU overhead in use cases where two

time slots are being used simultaneously.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

14 Freescale Semiconductor

Modules List

IPTP IEEE1588

Precision Time

Protocol

Connectivity

Peripherals

The IEEE 1588-2002 (version 1) standard defines a precision time protocol

(PTP) - which is a time-transfer protocol that enables synchronization of

networks (for example, Ethernet), to a high degree of accuracy and

precision.

The IEEE1588 hardware assist is composed of the two blocks: time stamp

unit and real time clock, which provide the timestamping protocol’s

functionality, generating and reading the needed timestamps.

The hardware-assisted implementation delivers more precise clock

synchronization at significantly lower CPU load compared to purely software

implementations.

Temperature

Monitor

(Part of SATA

Block)

System

Control

Peripherals

The temperature sensor is an internal module to the i.MX53 that monitors

the die temperature. The monitor is capable in generating SW interrupt, or

trigger the CCM, to reduce the core operating frequency.

TVE TV Encoder Multimedia The TV encoder, version 2.1 is implemented in conjunction with the image

processing unit (IPU) allowing handheld devices to display captured still

images and video directly on a TV or LCD projector. It supports composite

PAL/NTSC, VGA, S-video, and component up to HD1080p analog video

outputs.

TZIC TrustZone Aware

Interrupt

Controller

ARM/Control The TrustZone interrupt controller (TZIC) collects interrupt requests from all

i.MX53 sources and routes them to the ARM core. Each interrupt can be

configured as a normal or a secure interrupt. Software Force Registers and

software Priority Masking are also supported.

UART-1

UART-2

UART-3

UART-4

UART-5

UART Interface Connectivity

Peripherals

Each of the UART blocks supports the following serial data transmit/receive

protocols and configurations:

• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or

none)

• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate

relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F

standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USB USB Controller Connectivity

Peripherals

USB supports USB2.0 480 MHz, and contains:

• One high-speed OTG sub-block with integrated HS USB PHY

• One high-speed host sub-block with integrated HS USB PHY

• Two identical high-speed Host modules

The high-speed OTG module, which is internally connected to the HS USB

PHY, is equipped with transceiver-less logic to enable on-board USB

connectivity without USB transceivers

All the USB ports are equipped with standard digital interfaces (ULPI, HS

IC-USB) and transceiver-less logic to enable onboard USB connectivity

without USB transceivers.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 15

VPU Video Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU) version 3, which covers

many SD-level video decoders and SD-level encoders as a multi-standard

video codec engine as well as several important video processing such as

rotation and mirroring.

VPU Features:

• MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit

rate

• MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps

bit rate

• H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate

• H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit

rate

• VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit

rate

• RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate

• DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate

• MJPEG decode, Baseline profile, up to 8192 x 8192 resolution,

40 Mpixel/s bit rate for 4:4:4 format

• MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate1

• H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate1

• H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate1

• MJPEG encode, Baseline profile, up to 8192 x 8192 resolution,

80 Mpixel/s bit rate for 4:2:2 format

WDOG-1 Watch Dog Timer

Peripherals

The watch dog timer supports two comparison points during each counting

period. Each of the comparison points is configurable to evoke an interrupt

to the ARM core, and a second point evokes an external event on the

WDOG line.

WDOG-2

(TZ)

Watch Dog

(TrustZone)

Timer

Peripherals

The TrustZone watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and

forcing a switch to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. This situation should be

avoided, as it can compromise the system’s security. Once the TZ WDOG

module is activated, it must be serviced by TZ software on a periodic basis.

If servicing does not take place, the timer times out. Upon a time-out, the TZ

WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode.

If it is still not served, the TZ WDOG asserts a security violation signal to the

CSU. The TZ WDOG module cannot be programmed or deactivated by a

normal mode SW.

XTALOSC 24 MHz Crystal

Oscillator

Clocking Provides a crystal oscillator amplifier that supports a 24 MHz external crystal

XTALOSC_

32K

32.768 kHz

Crystal Oscillator

I/F

Clocking Provides a crystal oscillator amplifier that supports a 32.768 kHz external

crystal.

1VPU can generate higher bit rate than the maximum specified by the corresponding standard.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

16 Freescale Semiconductor

Electrical Characteristics

3.1 Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX53 Reference Manual. Special signal

considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide

(MX53UG).

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX53 processor.

4.1 Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference

to the individual tables and sections.

4.1.1 Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 4 may affect reliability or cause

permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions beyond those

indicated in the Operating Ranges table is not implied.

Table 3. i.MX53 Chip-Level Conditions

For these characteristics, … Topic appears …

Absolute Maximum Ratings Table 4 on page 16

TEPBGA-2 Package Thermal Resistance Data Table 5 on page 17

i.MX53 Operating Ranges Table 6 on page 18

External Clock Sources Table 7 on page 20

Maximal Supply Currents Table 8 on page 20

USB Interface Current Consumption Table 9 on page 23

Table 4. Absolute Maximum Ratings

Parameter Description Symbol Min Max Unit

Peripheral Core Supply Voltage VCC -0.3 1.35 V

ARM Core Supply Voltage VDDGP -0.3 1.4 V

Supply Voltage UHVIO Supplies denoted as I/O Supply -0.5 3.6 V

Supply Voltage for non UHVIO Supplies denoted as I/O Supply -0.5 3.3 V

USB VBUS VBUS — 5.25 V

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 17

4.1.2 Thermal Resistance

4.1.2.1 TEPBGA-2 Package Thermal Resistance

Table 5 provides the TEPBGA-2 package thermal resistance data.

Input voltage on USB_OTG_DP, USB_OTG_DN,

USB_H1_DP, USB_H1_DN pins

USB_DP/USB_DN -0.3 3.631V

Input/Output Voltage Range Vin/Vout -0.5 OVDD +0.32V

ESD Damage Immunity: Vesd V

• Human Body Model (HBM)

• Charge Device Model (CDM)

—

2000

500

Storage Temperature Range TSTORAGE -40 150 oC

1USB_DN and USB_DP can tolerate 5 V for up to 24 hours.

2The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in

Table 111 on page 148. The maximum range can be superseded by the DC tables.

Table 5. TEPBGA-2 Package Thermal Resistance Data

Rating Board Symbol Value Unit

Junction to Ambient (natural convection)1, 2

1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Single layer board

(1s)

RθJA 28 °C/W

Junction to Ambient (natural convection)1, 2, 3

3Per JEDEC JESD51-6 with the board horizontal.

Four layer board

(2s2p)

RθJA 16 °C/W

Junction to Ambient (at 200 ft/min)1, 3 Single layer board

(1s)

RθJMA 21 °C/W

Junction to Ambient (at 200 ft/min)1, 3 Four layer board

(2s2p)

RθJMA 13 °C/W

Junction to Board4

4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

—R

θJB 6°C/W

Junction to Case5

5Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

—R

θJC 4°C/W

Junction to Package Top (natural convection)6

6Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

—ΨJT 4°C/W

Table 4. Absolute Maximum Ratings (continued)

Parameter Description Symbol Min Max Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

18 Freescale Semiconductor

Electrical Characteristics

4.1.3 Operating Ranges

Table 6 provides the operating ranges of i.MX53 processor.

Table 6. i.MX53 Operating Ranges

Symbol Parameter Minimum1Nominal2Maximum1Unit

VDDGP3ARM core supply voltage

fARM ≤400 MHz

0.9 0.95 1.15 V

ARM core supply voltage

fARM ≤800 MHz

1.05 1.1 1.15 V

ARM core supply voltage

Stop mode

0.8 0.85 1.15 V

VCC Peripheral supply voltage41.25 1.3 1.35 V

Peripheral supply voltage—Stop mode 0.9 0.95 1.35 V

VDDA5Memory arrays voltage 1.25 1.30 1.35 V

Memory arrays voltage—Stop mode 0.9 0.95 1.35 V

VDDAL15L1 Cache Memory arrays voltage 1.25 1.30 1.35 V

L1 Cache Memory arrays voltage—Stop mode 0.9 0.95 1.35 V

VDD_DIG_PLL6PLL Digital supplies—external regulator option 1.25 1.3 1.35 V

VDD_ANA_PLL7PLL Analog supplies—external regulator option 1.75 1.8 1.95 V

NVCC_CKIH ESD protection of the CKIH pins, FUSE read Supply

and 1.8V bias for the UHVIO pads

1.65 1.8 1.95 V

NVCC_LCD

NVCC_JTAG

GPIO digital power supplies 1.65 1.8 or

2.775

3.1 V

NVCC_LVDS LVDS interface Supply 2.375 2.5 2.75 V

NVCC_LVDS_BG LVDS Band Gap Supply 2.375 2.5 2.75 V

NVCC_EMI_DRAM DDR Supply DDR2 range 1.7 1.8 1.9 V

DDR Supply LPDDR2 range 1.14 1.2 1.3

DDR Supply LV-DDR2 range

1.47 1.55 1.63

1.42 1.5 1.58

DDR Supply DDR3 range 1.42 1.5 1.58

VDD_FUSE8Fusebox Program Supply (Write Only) 3.0 — 3.3 V

NVCC_NANDF

NVCC_SD1

NVCC_SD2

NVCC_PATA

NVCC_KEYPAD

NVCC_GPIO

NVCC_FEC

NVCC_EIM_MAIN

NVCC_EIM_SEC

NVCC_CSI

Ultra High voltage I/O (UHVIO) supplies: V

• UHVIO_L 1.65 1.8 1.95

• UHVIO_H 2.5 2.775 3.1

• UHVIO_UH 3.0 3.3 3.6

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 19

TVDAC_DHVDD9

TVDAC_AHVDDRGB9

TVE digital and analog power supply, TVE-to-DAC

level shifter supply, cable detector supply, analog

power supply to RGB channel

2.69 2.75 2.91 V

For GPIO use only, when TVE is not in use 1.65 1.8 or

2.775

3.1 V

NVCC_SRTC_POW SRTC Core and slow I/O Supply (GPIO)10 1.25 1.3 1.35 V

NVCC_RESET LVIO 1.65 1.8 or

2.775

3.1 V

USB_H1_VDDA25

USB_OTG_VDDA25

NVCC_XTAL

USB_PHY analog supply, oscillator amplifier analog

supply11

2.25 2.5 2.75 V

USB_H1_VDDA33

USB_OTG_VDDA33

USB PHY I/O analog supply 3.0 3.3 3.6 V

VBUS See Ta b l e 4 on page 16 and Table 104 on page 141

for details. Note that this is not a power supply.

————

VDD_REG12 Power supply input for the integrated linear

regulators

2.37 2.5 2.63 V

VP SATA PHY core power supply 1.25 1.3 1.35 V

VPH SATA PHY I/O supply voltage 2.25 2.5 2.75 V

TJJunction temperature -40 10513 125 oC

1Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design

must allow for supply tolerances and system voltage drops.

2The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with

a tighter tolerance allows reduction of the setpoint with commensurate power savings.

3A voltage transition is allowed for the required supply ramp up to the nominal value prior to achieving a clock speed increase.

Similarly, to accommodate a frequency reduction, a voltage transition is allowed for a supply ramp down to the nominal value

after the frequency is decreased.

4For BSDL mode, the minimum operating temperature is 20 oC and the maximum operating temperature is the maximum

temperature specified for the particular part grade.

5VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this

configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should

increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.

6By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this

supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass

capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use

of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

7By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving

this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is

driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

8After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are

written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3

V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.

9If not using the TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and

TVDAC_AHVDDRGB can be kept floating or tied to GND—the recommendation is to float.

10 GPIO pad operational at low frequency

Table 6. i.MX53 Operating Ranges (continued)

Symbol Parameter Minimum1Nominal2Maximum1Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

20 Freescale Semiconductor

Electrical Characteristics

4.1.4 External Clock Sources

The i.MX53 device has four external input system clocks, a low frequency (CKIL), a high frequency

(XTAL), and two general purpose CKIH1 and CKIH2 clocks.

The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real

time clock operation, and slow system and watch-dog counters. The clock input can be connected to either

external oscillator or a crystal using internal oscillator amplifier.

The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either external oscillator or a crystal using internal

oscillator amplifier.

CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and

accurate frequencies.

Table 7 shows the interface frequency requirements. See Chapter 1 of i.MX53 System Development

User's Guide (MX53UG) for additional clock and oscillator information.

4.1.5 Maximal Supply Currents

Table 8 represents the maximal momentary current transients on power lines, and should be used for power

supply selection. Maximal currents higher by far than the average power consumption of typical use cases.

For typical power consumption information, see i.MX53 power consumption application note.

11 The analog supplies should be isolated in the application design. Use of series inductors is recommended.

12 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are

configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and

VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.

13 Lifetime of 87,600 hours based on 105 oC junction temperature at nominal supply voltages.

Table 7. External Input Clock Frequency

Parameter Description Symbol Min Typ Max Unit

CKIL Oscillator1

1External oscillator or a crystal with internal oscillator amplifier.

fckil — 32.7682/32.0

2Recommended nominal frequency 32.768 kHz.

—kHz

CKIH1, CKIH2 Operating

Frequency

fckih1,

fckih2

See Table 32, "CAMP Electrical Parameters (CKIH1,

CKIH2)," on page 44

MHz

XTAL Oscillator fxtal 22 24 27 MHz

Table 8. Maximal Supply Currents

Power Line Conditions Max Current Unit

VDDGP 800 MHz ARM clock 1450 mA

VCC 800 mA

VDDA+VDDAL1 100 mA

VDD_DIG_PLL 10 mA

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 21

VP 20 mA

VDD_ANA_PLL 10 mA

NVCC_XTAL 25 mA

VDD_REG 325 mA

VDD_FUSE Fuse Write Mode

operation

120 mA

NVCC_EMI_DRAM1

1.8V (DDR2) 800 mA

1.5V (DDR3) 650 mA

1.2V (LPDDR2) 250 mA

TVDAC_DHVDD + TVDAC_AHVDDRGB 200 mA

NVCC_SRTC_POW 502μA

USB_H1_VDDA25 +

USB_OTG_VDDA25

50 mA

USB_H1_VDDA33 +

USB_OTG_VDDA33

20 mA

VPH 60 mA

NVCC_CKIH Use maximal I/O Eq3, N=4

NVCC_CSI Use maximal I/O Eq3, N=20

NVCC_EIM_MAIN Use maximal I/O Eq3, N=39

NVCC_EIM_SEC Use maximal I/O Eq3, N=16

NVCC_FEC Use maximal I/O Eq3, N=11

NVCC_GPIO Use maximal I/O Eq3, N=13

NVCC_JTAG Use maximal I/O Eq3, N=6

NVCC_KPAD Use maximal I/O Eq3, N=11

NVCC_LCD Use maximal I/O Eq3, N=29

NVCC_LVDS Use maximal I/O Eq3, N=20

NVCC_LVDS_BG Use maximal I/O Eq3, N=1

NVCC_NANDF Use maximal I/O Eq3, N=8

NVCC_PATA Use maximal I/O Eq3, N=29

NVCC_REST Use maximal I/O Eq3, N=5

Table 8. Maximal Supply Currents (continued)

Power Line Conditions Max Current Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

22 Freescale Semiconductor

Electrical Characteristics

NVCC_SD1 Use maximal I/O Eq3, N=6

NVCC_SD2 Use maximal I/O Eq3, N=6

1The results are based on calculation assuming the following conditions:

—Four 16-bit DDR devices

—Heavy use profile

—On-Die Termination (ODT) of 50 Ω for DDR2 and 40 Ω for DDR3

—Dual rank termination schema

—Command and Address line termination to NVCC_EMI_DRAM/2 voltage

These numbers include both i.MX53 DDR controller I/O current consumption and DDR memory I/O power

consumption for data and DQS lines.

250 μA current is the worst case for fast silicon at 125 °C. The typical current is 3 μA for typical silicon at 25 °C.

3General Equation for estimated, maximal power consumption of an I/O power supply:

Imax = N x C x V x (0.5 x F)

Where:

N - Number of I/O pins supplies by the power line

C - Equivalent external capacitive load

V - I/O voltage

(0.5 x F) - Data change rate. Up to 0.5 of the clock rate (F).

Table 8. Maximal Supply Currents (continued)

Power Line Conditions Max Current Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 23

4.1.6 USB-OH-3 (OTG + 3 Host ports) Module and the Two USB PHY (OTG

and H1) Current Consumption

Table 9 shows the USB interface current consumption.

4.2 Power Supply Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from

these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the i.MX53 processor (worst-case scenario)

4.2.1 Power-Up Sequence

The following observations should be considered:

• The consequent steps in power up sequence should not start before the previous step supplies have

been stabilized within 90-110% of their nominal voltage, unless stated otherwise.

• NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time

clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.

• The VCC should be powered ON together, or any time after NVCC_SRTC_POW.

• NVCC_CKIH should be powered ON after VCC is stable and before other I/O supplies

(NVCC_xxx) are powered ON.

Table 9. USB Interface Current Consumption

Parameter Conditions Typical at 25 °C Max Unit

Analog Supply 3.3 V

USB_H1_VDDA33

USB_OTG_VDDA33

Full Speed

RX 5.5 6 mA

TX 7 8

High Speed

RX 5 6

TX 5 6

Analog Supply 2.5 V

USB_H1_VDDA25

USB_OTG_VDDA25

Full Speed

RX 6.5 7 mA

TX 6.5 7

High Speed

RX 12 13

TX 21 22

Digital Supply

VCC (1.2 V)

Full Speed

RX 8 — mA

TX 8 —

High Speed

RX 8 —

TX 8 —

i.MX53 Applications Processors for Industrial Products, Rev. 7

24 Freescale Semiconductor

Electrical Characteristics

• I/O Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede

NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is stabilized.

Within this group, the supplies can be powered-up in any order.

Alternatively, the on-chip regulator VDD_ANA_PLL can be used to power NVCC_CKIH and

NVCC_RESET. In this case, the sequence defined in the “Interfacing the i.MX53 Processor with

LTC3589-1” section of the i.MX53 System Development User's Guide (MX53UG) must be

followed.

• I/O Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after

NVCC_CKIH is stable.

• In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator

(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their

internal regulators power source.

If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage

during the power-up, it is recommended to activate the VDD_REG before or at the same time with

VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V

VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.

• VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on

after VCC and before NVCC_EMI_DRAM. The sequence should be:

VCC →VDD_REG →NVCC_EMI_DRAM

• If SRTC is not used, VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless

of any other power signal.

• When SRTC is used, VDDA and VDDAL1 must be powered on before VDD_REG.

• VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.

• VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come

before POR.

• TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This

is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is

powered ON before the other.

NOTE

The POR_B input must be immediately asserted at power-up and remain

asserted until after the last power rail reaches its working voltage.

NOTE

If NVCC_RESET power is removed or interrupted, a power-on reset is

generated.

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 25

Figure 2 shows the power-up sequence diagram.

Figure 2. Power-Up Detailed Sequence

1If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable.

2When SRTC is used, VDD_REG must power on after VDDA and VDDAL1.

NOTE

Need to ensure that there is no back voltage (leakage) from any supply on

the board towards the 3.3 V supply (for example, from the parts that use

both 1.8 V and the 3.3 V supply).

NOTE

For further details on power-up sequence, see the “Setting up Power

Management” chapter of i.MX53 System Development User’s Guide

(MX53UG).

NVCC_CKIH

(in any order, after NVCC_CKIH

POR_B

Δt>0

VCC 90%

90%

(in any order, if needed)

Δt>0

90%

NVCC_SRTC_POW

(may remain ON) 90%

I/O Supplies below or equal to

I/O Supplies above 2.8 V nom./3.1 V max

2.8 V nom./3.1 V max.

90%

Δt>0

90%

Δt>0

VDD_REG2

NVCC_EMI_DRAM

Δt>0

(in any order)

VP, VPH

Δt>0

90%

ramp up start, if needed)

(in any order)

VDDA,VDDAL1,VDDGP

Δt>0

90%

i.MX53 Applications Processors for Industrial Products, Rev. 7

26 Freescale Semiconductor

Electrical Characteristics

4.2.2 Power-Down Sequence

Power-down sequence should follow one of the following two options:

• Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

• Option 2: Switch down supplies, in any order, keeping the following rules:

— NVCC_CKIH must be powered down at the same time or after the UHVIO I/O cell supplies

(for full supply list, see Table 6, Ultra High voltage I/O (UHVIO) supplies). A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

— VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A

deviation of few microseconds of actual power-down of the different power rails is acceptable.

— If all of the following conditions are met:

– VDD_REG is powered down to 0V (Not Hi-Z)

– VDD_DIG_PLL and VDD_ANA_PLL are provided externally,

– VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL

Then the following rule should be kept: VDD_REG output impedance must be higher than 1

kW, when inactive.

4.2.3 Power Supplies Usage

• All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx)

is off. This can cause internal latch-up and malfunctions due to reverse current flows. For

information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of

Section 6, “Package Information and Contact Assignments.”

• If not using SATA interface and the embedded thermal sensor, the VP and VPH should be

grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not

recommended and might lead to excessive power consumption.

• When internal clock source is used for SATA temperature monitor the USB_PHY supplies and

PLL need to be active because they are providing the clock.

• If not using the TVE module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can be kept

floating or tied to GND—the recommendation is to float. If only the GPIO pads in

TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range

(1.65 V to 3.1 V).

4.3 I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 27

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output. The association is shown in Table 111.

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.3.1 General Purpose I/O (GPIO) DC Parameters

The parameters in Table 10 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

Table 10 shows DC parameters for GPIO pads, operating at two supply ranges:

• 1.1 V to 1.3 V

• 1.65 V to 3.1 V

Table 10. GPIO I/O DC Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

High-level output voltage1Voh Iout = -0.8 mA OVDD - 0.15 — — V

Low-level output voltage1Vol Iout = 0.8 mA — — 0.15 V

High-Level DC input voltage1, 2VIH — 0.7 ×OVDD — OVDD V

Low-Level DC input voltage1, 2VIL — 0 — 0.3 ×OVDD V

Input Hysteresis VHYS OVDD = 1.875 V

OVDD = 2.775 V

0.25 0.34

0.45

—V

Schmitt trigger VT+2, 3 VT+ — 0.5 ×OVDD — — V

Schmitt trigger VT-2, 3 VT- — — — 0.5 ×OVDD V

Input current (no pull-up/down) Iin Vin = OVDD or 0 — — 10 μA

Input current (22 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——161

μA

Input current (47 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——76

μA

Input current (100 kΩ Pull-up) Iin Vin = 0 V

Vin= OVDD

——40

μA

i.MX53 Applications Processors for Industrial Products, Rev. 7

28 Freescale Semiconductor

Electrical Characteristics

4.3.2 LPDDR2 I/O DC Parameters

The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.

4.3.2.1 DDR2 Mode I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The

parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

Input current (100 kΩ Pull-down) Iin Vin = 0 V

Vin = OVDD

——10

μA

Keeper Circuit Resistance — 1304—kΩ

1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

3Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 11. DDR2 I/O DC Electrical Parameters1

1Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any

specification in this document.

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage2

2OVDD is the I/O power supply (1.7 V–1.9 V for DDR2)

Voh Ioh = -0.1 mA 0.9 x OVDD — — V

Low-level output voltage Vol Iol = 0.1 mA — — 0.1 x OVDD V

Input Reference Voltage Vref 0.49 x

OVDD

0.5 x OVDD 0.51 x OVDD

DC input High Voltage (data pins) Vihd

(dc)

— Vref+0.125V — OVDD+0.3 V

DC input Low Voltage (data pins) Vild (dc) — -0.3 — Vref - 0.125V V

DC Input voltage range of each

differential input3

Vin (dc) — -0.3 — OVDD + 0.3 V

DC Differential input voltage required for

switching 4

Vid (dc) — 0.25 — OVDD + 0.6 V

Termination Voltage Vtt Vtt Vref - 0.04 Vref Vref + 0.04 V

Input current (no pull-up/down) Iin Vin = 0 V

Vin = OVDD

—

μA

Keeper Circuit Resistance — — — 1305—kΩ

Table 10. GPIO I/O DC Electrical Characteristics (continued)

Parameter Symbol Test Conditions Min Typ Max Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 29

4.3.2.2 LPDDR2 Mode I/O DC Parameters

The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.

The parameters in Table 12 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.3.2.3 DDR3 Mode I/O DC Parameters

The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The

parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

3Vin(dc) specifies the allowable DC voltage exertion of each differential input.

4Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the

“complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc).

5Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 12. LPDDR2 I/O DC Electrical Parameters1

1Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage Voh Ioh = -0.1 mA 0.9 x OVDD — — V

Low-level output voltage Vol Iol = 0.1 mA — — 0.1 x OVDD V

Input Reference Voltage Vref 0.49 x

OVDD

0.5 x OVDD 0.51 x OVDD

DC input High Voltage Vih(dc) — Vref+0.13V — OVDD V

DC input Low Voltage Vil(dc) — OVSS — Vref - 0.13V V

Differential Input Logic High Vih(diff) 0.26 See Note2

2The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

Differential Input Logic Low Vil(diff) See Note2-0.26

Input current (no pull-up/down) Iin Vin = 0 V

Vin = OVDD

—

μA

Pull-up/Pull-down impedance Mismatch -15 +15 %

240 Ω unit calibration resolution 10 Ω

Keeper Circuit Resistance — — — 1403

3Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

—kΩ

Table 13. DDR3 I/O DC Electrical Parameters

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage Voh Ioh = -0.1 mA 0.8 x OVDD1——V

Low-level output voltage Vol Iol = 0.1 mA — — 0.2 x OVDD V

DC input Logic High VIH(dc) — Vref2+0.1 — OVDD V

DC input Logic Low VIL(dc) — OVSS — Vref-0.1 V

Differential input Logic High VIH(diff) — 0.2 — See Note3V

i.MX53 Applications Processors for Industrial Products, Rev. 7

30 Freescale Semiconductor

Electrical Characteristics

4.3.3 Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 14 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

The LVIO pads operate only as inputs.

Differential input Logic Low VIL(diff) — See Note3—-0.2V

Over/undershoot peak Vpeak — — — 0.4 V

Over/undershoot area

(above OVDD or below OVSS)

Varea — — — 0.67 V-ns

Termination Voltage Vtt Vtt tracking OVDD/2 0.49 x OVDD Vref 0.51 x OVDD V

Input current (no pull-up/down) Iin VI = 0 V

VI=OVDD

—

μA

Pull-up/Pull-down impedance mismatch — Minimum impedance

configuration

—— 3Ω

240 Ω unit calibration resolution — — — — 10 Ω

Keeper Circuit Resistance — — — 1304—kΩ

1OVDD— I/O power supply (1.425 V–1.575 V for DDR3)

2Vref— DDR3 external reference voltage

3The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 14. LVIO DC Electrical Characteristics

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

High-Level DC input voltage1, 2 Vih Ioh = -0.8 mA 0.7 ×OVDD — OVDD V

Low-Level DC input voltage1, 2 Vil Iol = 0.8 mA 0 — 0.3 ×OVDD V

Input Hysteresis Vhys OVDD = 1.875 V

OVDD = 2.775 V

0.35 0.62

1.27

—V

Schmitt trigger VT+2, 3 VT+ — 0.5 ×OVDD — — V

Schmitt trigger VT-2, 3 VT- — — — 0.5 ×OVDD V

Input current (no pull-up/down) Iin Vin = OVDD or 0 V — — 1 μA

Input current (22 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

— — 161

μA

Input current (47 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——76

μA

Input current (100 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——36

μA

Input current (100 kΩ Pull-down) Iin Vin = 0 V

Vin = OVDD

—— 1

μA

Keeper Circuit Resistance — — 1304—kΩ

Table 13. DDR3 I/O DC Electrical Parameters (continued)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 31

4.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 15 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply

when hysteresis is enabled.

3Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled.

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 15. UHVIO DC Electrical Characteristics

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

High-level output voltage1

1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

Voh Iout = -0.8 mA OVDD-0.15 — — V

Low-level output voltage1Vol Iout = 0.8 mA — — 0.15 V

High-Level DC input voltage1, 2

2 To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current

DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply

when hysteresis is enabled.

VIH — 0.7 ×OVDD — OVDD V

Low-Level DC input voltage1, 2VIL — 0 — 0.3 ×OVDD V

Input Hysteresis VHYS low voltage mode

high voltage mode

0.38

0.95

—0.43

1.33

Schmitt trigger VT+2, 3

3Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

VT+ — 0.5 ×OVDD — — V

Schmitt trigger VT-2, 3 VT- — — — 0.5 ×OVDD V

Input current (no pull-up/down) Iin Vin = OVDD or 0 V — — 1 μA

Input current (22 kΩ Pull-up) Iin Vin = 0

Vin = OVDD

— — 202

μA

Input current (75 kΩ Pull-up) Iin Vin = 0

Vin = OVDD

——61

μA

Input current (100 kΩ Pull-up) Iin Vin = 0

Vin = OVDD

——47

μA

Input current (360 kΩ Pull-down) Iin Vin = 0

Vin = OVDD

—— 1

5.7

μA

Keeper Circuit Resistance — — — 1304

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

—kΩ

i.MX53 Applications Processors for Industrial Products, Rev. 7

32 Freescale Semiconductor

Electrical Characteristics

4.3.5 LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics. The

parameters in Table 16 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.4 Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX53 processor for the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

NOTE

Output driver impedance is measured with “long” transmission line of

impedance Ztl attached to I/O pad and incident wave launched into

transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 4).

Table 16. LVDS DC Electrical Characteristics

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

Output Differential Voltage VOD Rload = 100Ω between

padP and padN

250 350 450 mV

Output High Voltage VOH 1.25 1.375 1.6 V

Output Low Voltage VOL 0.9 1.025 1.25

Offset Voltage VOS 1.125 1.2 1.375

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 33

Figure 4. Impedance Matching Load for Measurement

ipp_do

Cload = 1p

Ztl Ω, L = 20 inches

predriver

PMOS (Rpu)

NMOS (Rpd)

pad

OVDD

OVSS

t,(ns)

U,(V)

OVDD

t,(ns)

VDD

Vin (do)

Vout (pad)

U,(V)

Vref

Rpu = Vovdd - Vref1

Vref1

× Ztl

Rpd = × Ztl

Vref2

Vovdd - Vref2

Vref1 Vref2

i.MX53 Applications Processors for Industrial Products, Rev. 7

34 Freescale Semiconductor

Electrical Characteristics

4.4.1 GPIO Output Buffer Impedance

Table 17 shows the GPIO output buffer impedance.

4.4.2 DDR Output Driver Average Impedance

The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April,

2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.

Table 17. GPIO Output Buffer Impedance

Parameter Symbol Test Conditions Min

Typ

Max Unit

OVDD 2.775 V OVDD 1.875 V

Output Driver

Impedance

Rpu Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5 Ω

104

150

250

125

Output Driver

Impedance

Rpd Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5 Ω

134

243

122

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 35

Table 18 shows DDR output driver average impedance of the i.MX53 processor.

Table 18. DDR Output Driver Average Impedance1

1Output driver impedance is controlled across PVTs (process, voltages, and temperatures) using calibration procedure and

pu_*cal, pd_*cal input pins.

Parameter Symbol Test Conditions

Drive strength (DSE)

Unit

000 001 010 011 100 101 110 111

Output

Driver

Impedance

Rdrv2

2Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

LPDDR1/DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 00

Calibration resistance = 300 Ω3

3Calibration is done against external reference resistor. Value of the resistor should be varied depending on DDR mode and

DDR_SEL setting.

Hi-Z 300 150 100 75 60 50 43 Ω

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 01

Calibration resistance = 180 Ω3

Hi-Z 180 90 60 45 36 30 26

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 10

Calibration resistance = 200 Ω3

Hi-Z 200 100 66 50 40 33 28

DDR2 mode

NVCC_DRAM= 1.8 V

DDR_SEL = 11

Calibration resistance = 140 Ω3

Hi-Z 140 70 46 35 28 23 20

LPDDR2 mode

NVCC_DRAM= 1.2 V

DDR_SEL = 014

Calibration resistance = 160 Ω3

4If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference

resistor value must be 160 Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory

devices should be kept to 240 Ω per the JEDEC standard.

Hi-Z 160 80 53 40 32 27 23

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 10

Calibration resistance = 240 Ω3

Hi-Z 240 120 80 60 48 40 34

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 114

Calibration resistance = 160 Ω3

Hi-Z 160 80 53 40 32 27 23

DDR3 mode

NVCC_DRAM = 1.5 V

DDR_SEL = 00

Calibration resistance = 200 Ω3

Hi-Z 240 120 80 60 48 48 34

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36 Freescale Semiconductor

Electrical Characteristics

4.4.3 UHVIO Output Buffer Impedance

Table 19 shows the UHVIO output buffer impedance.

4.4.4 LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.5 I/O AC Parameters

This section includes the AC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.

Figure 5. Load Circuit for Output

Figure 6. Output Transition Time Waveform

Table 19. UHVIO Output Buffer Impedance

Parameter Symbol Test Conditions

Min Typ Max

Unit

OVDD

1.95 V

OVDD

3.0 V

OVDD

1.875 V

OVDD

3.3 V

OVDD

1.65 V

OVDD

3.6 V

Output Driver

Impedance

Rpu Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

114

124

135

198

206

103

Output Driver

Impedance

Rpd Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

118

126

154

179

217

109

Tes t P o in t

From Output

Under Test

CL includes package, probe and fixture capacitance

OVDD

20%

80% 80%

20%

tr tf

Output (at pad)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 37

4.5.1 GPIO I/O AC Electrical Characteristics

AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 20 and

Table 21, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit

in the IOMUXC control registers.

Table 20. GPIO I/O AC Parameters Slow Mode

Parameter Symbol Test Condition Min Typ Max Unit

Output Pad Transition Times (Max Drive) tr, tf 15 pF

35 pF

— — 1.91/1.52

3.07/2.65

Output Pad Transition Times (High Drive) tr, tf 15 pF

35 pF

— — 2.22/1.81

3.81/3.42

Output Pad Transition Times (Medium Drive) tr, tf 15 pF

35 pF

— — 2.88/2.42

5.43/5.02

Output Pad Transition Times (Low Drive) tr, tf 15 pF

35 pF

— — 4.94/4.50

10.55/9.70

Output Pad Slew Rate (Max Drive)1

1tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

tps 15 pF

35 pF

0.5/0.65

0.32/0.37

—— V/ns

Output Pad Slew Rate (High Drive)1tps 15 pF

35 pF

0.43/0.54

0.26/0.41

——

Output Pad Slew Rate (Medium Drive)1tps 15 pF

35 pF

0.34/0.41

0.18/0.2

——

Output Pad Slew Rate (Low Drive)1tps 15 pF

35 pF

0.20/0.22

0.09/0.1

——

Output Pad di/dt (Max Drive) tdit — — — 30 mA/ns

Output Pad di/dt (High Drive) tdit — — — 23

Output Pad di/dt (Medium drive) tdit — — — 15

Output Pad di/dt (Low drive) tdit — — — 7

Input Transition Times2

2Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

trm — — — 25 ns

Table 21. GPIO I/O AC Parameters Fast Mode

Parameter Symbol Test

Condition Min Typ Max Unit

Output Pad Transition Times (Max Drive) tr, tf 15 pF

35 pF

— — 1.45/1.24

2.76/2.54

Output Pad Transition Times (High Drive) tr, tf 15 pF

35 pF

— — 1.81/1.59

3.57/3.33

Output Pad Transition Times (Medium

Drive)

tr, tf 15 pF

35 pF

— — 2.54/2.29

5.25/5.01