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©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6
January 2016
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Features
• Very High Speed – 10 MBit/s
• Superior CMR – 10 kV/µs
• Fan-out of 8 Over -40°C to +85°C
• Logic Gate Output
• Strobable Output
• Wired OR-open Collector
• Safety and Regulatory Approvals
– UL1577, 5,000 VACRMS for 1 Minute
– DIN EN/IEC60747-5-5
Applications
• Ground Loop Elimination
• LSTTL to TTL, LSTTL or 5 V CMOS
• Line Receiver, Data Tr ansmission
• Data Multiplexing
• Switching Power Supplies
• Pulse Tr ansformer Replacement
• Computer-peripheral Interface
Description
The 6N137M, HCPL260 1M, HCPL2 611M single-ch annel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-d etector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
An internal noise shield provides superior common mode
rejection of typically 10 kV/µs. The HCPL2601M and
HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M ha s a minimum CMR of 10 kV/µs.
Schematics Package Outlines
1
2
3
4 5
6
7
8
N/C
_
VCC
VE
VO
GND
+
N/C
VF
1
2
3
4 5
6
7
8
+
_
VF1
VCC
V01
V02
GND
VF2
_
+
HCPL2630M,
HCPL2631M
6N137M,
HCPL2601M,
HCPL2611M
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
Truth Table (Positive Logic)
Input Enable Output
H H L
L H H
H L H
L L H
H NC L
L NC H
8
8
1
8
1
1
8
1
Figure 1. Schematics
Figure 2. Package Optio ns
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 2
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Safety and Insulation Ratings
As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only withi n the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1 µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to
the package VCC and GND pins of each device.
2. Safety limit value - maximum values allowed in the event of a failure.
Parameter Characteristics
Installation Classifications per DIN VDE
0110/1.89 Table 1, For Rated Mains Voltage
< 150 VRMS I–IV
< 300 VRMS I–IV
< 450 VRMS I–III
< 600 VRMS I–III
Climatic Classification 40/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Comparative Tracking Index 175
Symbol Parameter Value Unit
VPR
Input-to-Output Test Voltage, Method A, VIORM x 1.6 = VPR,
Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC 1,335 Vpeak
Input-to-Output Test Voltage, Method B, VIORM x 1.875 = VPR,
100% Production Test with tm = 1 s, Partial Discharge < 5 pC 1,669 Vpeak
VIORM Maximum Working Insulation Voltage 890 Vpeak
VIOTM Highest Allowable Over-Voltage 6,000 Vpeak
External Creepage ≥ 8.0 mm
External Clearance ≥ 7.4 mm
External Clearance (for Option TV, 0.4" Lead Spacing) ≥ 10.16 mm
DTI Distance Through Insulation (Insulation Thickness) ≥ 0.5 mm
TSCase Temperature(2) 150 °C
IS,INPUT Input Current(2) 200 mA
PS,OUTPUT Output Power (Duty Factor ≤ 2.7%)(2) 300 mW
RIO Insulation Resistance at TS, VIO = 500 V(2) > 109Ω
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 3
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended expo sure to stresses above the recommende d operating conditions ma y affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Recommended Operating Conditions
The Recommended Operating Conditio ns table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note:
3. 6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0 mA or less.
Symbol Parameter Value Unit
TSTG Sto r age Temperature -40 to +125 °C
TOPR Operating Temperature -40 to +100 °C
TJJunction Temperature -40 to +125 °C
TSOL Lead Solder Temperature 260 for 10 sec °C
Symbol Parameter Device Value Unit
EMITTER
IF (avg) DC/Average Forward Input Current Per Chann el Single Channel 50 mA
Dual Channel 30
VEEnable Input Voltage Not to Exceed VCC
by more than 500 mV Single Channel 5.5 V
VRReverse Input Voltage Per Channel All 5.0 V
PIInput Power Dissipation Per Channel Single Channel 100 mW
Dual Channel 45
DETECTOR
VCC Supply Voltage A ll -0.5 to 7.0 V
IO (avg) Average Output Current Per Channel All 25 mA
IO (pk) Peak Output Current Per Channel All 50 mA
VOOutput Voltage Per Channel All -0.5 to 7.0 V
POOutput Power Dissipation Per Channel Single Channel 85 mW
Dual Channel 60
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
IFL Input Current, Low Level 0 250 µA
IFH Input Current, High Level 6.3(3) 20.0 mA
VEL Enable Voltage, Low Level 0 0.8 V
VEH Enable Voltage, High Level 2.0 VCC V
TAAmbient Operating Temperature -40 +85 °C
N Fan Out (TTL load) 8
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 4
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Electrical Characteristics
Individual Component Characteristic s (VCC = 5.5 V, TA = 0°C to 70°C unless otherwise specified)
Note:
4. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
Transfer Characteristics (VCC = 5.5 V, TA = -40°C to +85°C unless otherwise specified)
Symbol Parameter Device Test Conditions Min. Typ. Max. Unit
EMITTER
VFInput Forward Voltage All IF = 10 mA, TA = 25°C 1.45 1.70 V
IF = 10 mA 1.80
BVR Input Reverse Breakdown
Voltage All IR = 10 µA 5.0 V
CIN Input Capacitance All VF = 0, f = 1 MHz 60 pF
ΔVF / ΔTATemperature Coefficient of
Forward Voltage All IF = 10 mA -1.4 mV/°C
DETECTOR
ICCL Logic Low Supply Current Single Channel IF = 10 mA, VO = Open,
VE = 0.5 V 813
mA
Dual Channel IF1 = IF2 = 10 mA,
VO = Open 14 21
ICCH Logic High Supply Current Single Channel IF = 0 mA, VO = Open,
VE = 0.5 V 610
mA
Dual Channel IF = 0 mA, VO = Open, 10 15
IEL Low Level Enable Current Single Channel VE = 0.5 V -0.7 -1.6 mA
IEH High Level Enable Current Single Channel VE = 2.0 V -0.5 -1.6 mA
VEL Low Level Enable Voltage Single Channel IF = 10 mA(4) 0.8 V
VEH High Level Enable Voltage Single Channel IF = 10 mA 2. 0 V
Symbol Parameter Device Test Conditions Min. Typ. Max. Unit
IFT Input Threshol d Curre nt All VO = 0.6 V, VE = 2.0 V,
IOL = 13 mA 3 5 mA
IOH HIGH Level Output Current All VO = 5.5 V, IF = 250 µA,
VE = 2.0 V 100 µA
VOL LOW Level Out pu t Voltage All IF = 5 mA, VE = 2.0 V,
IOL = 13 mA 0.4 0.6 V
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 5
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Electrical Characteristics (Continued)
Switching Characteristics (VCC = 5 V, IF = 7.5 mA, TA = -40°C to +85°C unless otherwise specified )
Notes:
5. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HI GH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
7. tR – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
8. tF – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
9. tEHL – Enable input propagati on delay is measured from the 1.5 V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5 V level on the HIGH to LOW transition of the ou tput voltage pulse.
10. tELH – Enable input propagati on delay is measured from the 1.5 V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
11. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge
of the common mode pu l se sign a l , VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0 V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge
of the common mode pu l s e si gn a l , VCM, to assure that the output will remain in a logic low state (i.e., VO < 0.8 V).
Symbol Parameter Device Test Conditions Min. Typ. Max. Unit
tPHL Propagation Delay
Time to Logic LOW All
RL = 350 Ω, CL = 15 pF,
TA = 25°C(5) (Fig. 14) 25 40 75 ns
RL = 350 Ω, CL = 15 pF(5)
(Fig. 14) 100
tPLH Propagation Delay
Time to Logic HIGH All
RL = 350 Ω, CL = 15 pF,
TA = 25°C(6) (Fig. 14) 20 40 75 ns
RL = 350 Ω, CL = 15 pF(6)
(Fig. 14) 100
|tPHL–tPLH| Pulse Width Distortion All RL = 350 Ω, CL = 15 pF
(Fig. 14) 135ns
tROutput Rise Time
(10% to 90%) All RL = 350 Ω, CL = 15 pF(7)
(Fig. 14) 30 ns
tFOutput Fall Time
(90% to 10%) All RL = 350 Ω, CL = 15 pF(8)
(Fig. 14) 10 ns
tEHL
Enable Propagation
Delay Time to Output
LOW Level Single Channel VEH = 3.5 V, RL = 350 Ω,
CL = 15 pF(9) (Fig. 15) 15 ns
tELH
Enable Propagation
Delay Time to Output
HIGH Level Single Channel VEH = 3.5 V, RL = 350 Ω,
CL = 15 pF(10) (Fig. 15) 15 ns
|CMH|Common Mode
Transient Immunity
at Logic High
6N137M,
HCPL2630M IF = 0 mA, VCM = 50 VPEAK,
RL = 350 Ω, TA = 25°C (11)
(Fig. 16)
10,000
V/µs
HCPL2601M,
HCPL2631M 5000 10,000
HCPL2611M IF = 0 mA, VCM = 400 VPEAK,
RL = 350 Ω, TA = 25°C (11)
(Fig. 16) 10,000 15,000
|CML|Common Mode
Transient Immunity
at Logic Low
6N137M,
HCPL2630M VCM = 50 VPEAK,
RL = 350 Ω, TA = 25°C (11)
(Fig. 16)
10,000
V/µs
HCPL2601M,
HCPL2631M 5000 10,000
HCPL2611M VCM = 400 VPEAK,
RL = 350 Ω, TA = 25°C (11)
(Fig. 16) 10,000 15,000
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 6
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Electrical Characteristics (Continued)
Isolation Characteristics (TA =25°C unless otherwise specified.)
Notes:
12. Device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are shorted
together.
13. 5000 VACRMS for 1 minute duration is equivalent to 6000 VACRMS for 1 second duration.
Symbol Parameter Device Test Conditions Min. Typ. Max. Unit
VISO Withstand Insulation
Test Voltage All Relative Humidity ≤ 50%,
II-O ≤ 10 µA, t = 1 min,
f = 50 Hz(12)(13) 5,000 VACRMS
RI-O Resistance
(Input to Output) All VI-O = 500 VDC(12) 1011 Ω
CI-O Capacitance
(Input to Output) All f = 1 MHz, VI-O = 0 VDC(12) 1pF
II-O Input-Output Insulation
Leakage Current All Relative Humidity ≤ 45%,
VI-I = 3000 VDC, t = 5 sec(12) 1.0 µA
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 7
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves
For Single-Channel Device s: 6N137M, HCPL2601M, and HCPL2611M
Figure 3. Low Level Output Voltage vs. Ambient Temperature Figure 4. Input Diode Forward Voltage vs. Forward Current
Figure 5. Switching Time vs. Forward Current Figure 6. Low Level Output vs. Ambient Temperature
T
A
– AMBIENT TEMPERATURE (°C)
I
F
= 5 mA
V
E
= 2 V
V
CC
= 5.5 V
Figure 7. Input Threshold Current vs. Ambient Temperature Figure 8. Output Voltage vs. Input Forward Current
V
CC
= 5 V
T
A
= 25°C
V
CC
= 5 V
V
E
= 2 V
V
OL
= 0.6 V
V
CC
= 5 V
V
E
= 2 V
V
OL
= 0.6 V
I
F
= 15 mA
I
F
= 10 mA
I
F
= 5 mA
I
OL
= 12.8 mA
I
OL
= 16 mA
I
OL
= 9.6 mA
I
OL
= 6.4 mA
-40 -20 0 20 40 60 80 100
V
OL
– LOW LEVEL OUTPUT VOLTAGE (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
I
F
– FORWARD CURRENT (mA)
V
F
– FORWARD VOLTAGE (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
0.001
0.010
0.100
1
10
T
P
– PROPAGATION DELAY (ns)
I
F
– FORWARD CURRENT (mA)
5 7 9 111315
20
0
40
4.0
3.5
3.0
2.5
2.0
1.5
1.0
60
80
100
120
R
L
= 4 kΩ (t
PLH
)
R
L
= 1 kΩ (t
PLH
)
R
L
= 350 Ω
R
L
= 350 Ω
R
L
= 1 kΩ
R
L
= 1 kΩ
R
L
= 4 kΩ
R
L
= 4 kΩ
R
L
= 350 Ω (t
PLH
)
R
L
= 4 kΩ (t
PHL
)
R
L
= 1 kΩ (t
PHL
)
R
L
= 350 Ω (t
PHL
)
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
I
OL
– LOW LEVEL OUTPUT CURRENT (mA)
20
25
30
35
40
45
50
I
FT
– INPUT THRESHOLD CURRENT (mA)
V
O
– OUTPUT VOLTAGE (V)
I
F
- FORWARD CURRENT (mA)
0123456
0
1
2
3
4
5
6
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 8
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves (Continued)
For Single-Channel Device s: 6N137M, HCPL2601M, HCPL2611M
Figure 9. Pulse Width Distortion vs. Temperature Figure 10. Rise and Fall Time vs. Temperature
I
F
= 7.5 mA
V
CC
= 5 V
I
F
= 7.5 mA
V
CC
= 5 V I
F
= 7.5 mA
V
CC
= 5 V
I
F
= 7.5 mA
V
CC
= 5 V
60
50
40
30
20
10
0
-10
100
80
60
40
20
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
500
400
300
200
100
0
-100
100
90
80
70
60
50
40
30
20
R
L
= 350 Ω
R
L
= 1 kΩ
R
L
= 4 kΩ
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
Figure 11. Enable Propagation Delay vs. Temperature Figure 12. Switching Time vs. Temperature
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
Figure 13. High Level Output Current vs. Temperature
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
PWD – PULSE WIDTH DISTORTION (ns)
T
E
– ENABLE PROPAGATION DELAY (ns)
I
OH
– HIGH LEVEL OUTPUT CURRENT (μA)
T
P
– PROPAGATION DELAY (ns) t
R
/ t
F
– RISE AND FALL TIME (ns)
R
L
= 4 kΩ (t
R
)
R
L
= 1 kΩ (t
R
)
R
L
= 350 Ω (t
R
)
R
L
= 4 kΩ (t
F
)
R
L
= 1 kΩ (t
F
)
R
L
= 350 Ω (t
F
)
R
L
= 4 kΩ (t
ELH
)
R
L
= 4 kΩ (t
PLH
)
R
L
= 1 kΩ (t
PLH
)
R
L
= 350 Ω (t
PLH
)
R
L
= 4 kΩ (t
PHL
)
R
L
= 1 kΩ (t
PHL
)
R
L
= 350 Ω (t
PHL
)
R
L
= 1 kΩ (t
ELH
)
R
L
= 350 Ω (t
ELH
)
R
L
= 4 kΩ / 1 kΩ / 350 Ω (t
EHL
)
V
CC
= 5 V
V
O
= 5.5 V
V
E
= 2 V
I
F
= 250 μA
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 9
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves (Continued)
For Dual-Channel Devices: HCPL26 30M and HCPL2631M
Figure 14. Low Level Output Voltage vs. Ambient Temperature
T
A
– AMBIENT TEMPERATURE (°C)
T
A
– AMBIENT TEMPERATURE (°C)
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
V
OL
– LOW LEVEL OUTPUT VOLTAGE (V)
T
P
– PROPAGATION DELAY (ns)
I
F
– FORWARD CURRENT (mA)
I
OL
– LOW LEVEL OUTPUT CURRENT (mA)
V
O
– OUTPUT VOLTAGE (V)
I
F
– FORWARD CURRENT (mA)
I
F
- FORWARD CURRENT (mA)
IOL
= 16 mA
Figure 17. Low Level Output Current
vs. Ambient Temperature
IF
= 5 mA
IF = 10 mA
IF = 15 mA
Figure 18. Input Threshold Current
vs. Ambient Temperature
I
FT
– INPUT THRESHOLD CURRENT (mA)
RL = 350 Ω
RL = 1 kΩ
RL = 4 kΩ
Figure 19. Output Voltage vs. Input Forward Current
RL = 350 Ω
RL = 1 kΩ
RL = 4 kΩ
IOL
= 6.4 mA IOL
= 9.6 mA
IOL
= 12.8 mA
IF = 5 mA
VCC
= 5.5 V
VCC
= 5.0 V
VOL = 0.6 V
Figure 15. Input Diode Forward Voltage
vs. Forward Current
V
F
– FORWARD VOLTAGE (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
VCC
= 5 V
VOL
= 0.6 V
Figure 16. Switching Time vs. Forward Current
5
0123456
7 9 11 13 15
V
TA = 25°C
CC = 5 V
RL = 1 kΩ(TPLH)
RL = 4 kΩ(TPLH)
RL = 350 Ω (TPLH )
RL = 1 kΩ
RL = 4 kΩ
RL = 350 Ω
(TPHL)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
3
4
0
20
40
60
80
100
120
20
25
30
35
40
45
50
0
1
2
3
4
5
6
100
10
1
0.1
0.01
0.001
-40 -20 0 20 40 60 80 100
-40 -20 0 20 40 60 80 100
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 10
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves (Continued)
For Dual-Channel Devices: HCPL2630M and HCPL2631M
Figure 20. Pulse Width Distortion vs. Temperature
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C) TA – TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
PWD – PULSE WIDTH DISTORTION (ns)
IOH – HIGH LEVEL OUTPUT CURRENT (μA)
TP – PROPAGATION DELAY (ns)
Tr/Tf – RISE AND FALL TIME (ns)
RL = 4 kΩ
RL = 1 kΩ
RL = 350 Ω
F
I = 7.5 mA
VCC = 5 V
Figure 21. Rise and Fall Time vs. Temperature
LR = 4 kΩ(tr)
IF = 7.5 mA
VCC = 5 V
RL = 1 kΩ(tr)
(tf)
RL = 350 Ω (tr)
RL = 1 kΩ
RL = 4 kΩ
RL = 350 Ω
Figure 22. Switching Time vs. Temperature
RL = 1 kΩ (TPLH)
RL = 350 Ω (TPLH)
RL = 4 kΩ (TPLH)
RL = 1 kΩ
RL = 4 kΩ
RL = 350 Ω
(TPHL)
Figure 23. High Level Output Current
vs. Temperature
80
60
40
20
0
600
500
400
300
200
100
0
20
40
60
80
100
120 1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VCC = 5.5 V
VO = 5.5 V
IF = 250 μA
FI = 7.5 mA
VCC = 5 V
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 11
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Test Circuits
47
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
7.5 mA
+5 V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
6
5
4 5
Pulse
1
2
3
Generator
tr = 5 ns
Z = 50 Ω
O
8
7
6
+5 V
PLH
t
I = 3.75 mA
F
Output
O
(V )
Input
(I )
F
Output
(V )
O
f
t
r
t
Output
(V )
O
L
R
C
L
(I )
Input
F
Monitor
O
Z = 50 Ω
Pulse
Generator
tr = 5 ns
(V )
E
Input
Monitor
GND
V
CC
O
(V )
Output
L
R
L
C
(V )
Output
O
Input
(V )
E
EHL
tt
ELH
bypass
.1 μF
bypass
.1 μF
Figure 24. Test Circuit and Waveforms for tPLH, tPHL, trand tf
Figure 25. Test Circuit tEHL and tELH
GND
V
CC
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 12
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Test Circuits (Continued)
+5 V
Peak
3
2
1
4
8
7
6
5
GND
V
CC
O
(V )
Output
350 Ω
V
CM
FF
V
A
B
Pulse Gen
I
F
CM
V
0V
O
V
5V Switching Pos. (A), I = 0
F
O
V (Max)
CM
0.5 V
O
V
Switching Pos. (B), I = 7
.5 mA
F
H
CM
L
V (Min)
O
bypass
.1 μF
Figure 26. Test Circuit Common Mode Transient Immunity
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 13
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Reflow Profile
Figure 27. Reflow Profile
Profile Freature Pb-Free Assembly Profile
Temperature Min. (Tsmin) 150°C
Temperature Max. (Tsmax) 200°C
Time (tS) from (Tsmin to Tsmax) 60 to 120 s
Ramp-up Rate (tL to tP) 3°C/second maximum
Liquidous Temperature (TL) 217°C
Time (tL) Maintained Above (TL) 60 to 150 s
Peak Body Package Temperature 260°C +0°C / –5°C
Time (tP) within 5°C of 260°C 30 s
Ramp-down Rate (TP to TL) 6°C/s maximum
Time 25°C to Peak Temperature 8 minutes maximum
Time (seconds)
Temperature (°C)
Time 25°C to Peak
260
240
220
200
180
160
140
120
100
80
60
40
20
0
TL
ts
tL
tP
TP
Tsma x
Tsmi n
120
Preheat Area
Maximum Ramp-up Rate = 3°C/S
Maximum Ramp-down Rate = 6°C/S
240 360
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 14
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Ordering Information
Note:
The product orderable part number system listed in this table also applies to the HCPL2601M, HCPL2611M,
HCPL2630M and HCPL2631M product families.
Marking Information
Part Number Package Packing Method
6N137M DIP 8-Pin Tube (50 units per tube)
6N137SM SMT 8-Pin (Lead Bend) Tube (50 units per tube)
6N137SDM SMT 8-Pin (Lead Bend) Tape and Reel (1,000 units per reel)
6N137VM DIP 8-Pin, DIN EN/IEC 60747-5-5 Option Tube (50 units per tube)
6N137SVM SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-5 Option Tube (50 units per tube)
6N137SDVM SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-5 Option Tape and Reel (1,000 units per reel)
6N137TVM DIP 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 Option Tube (50 units per tube)
6N137TSVM SMT 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 Option Tube (50 units per tube)
6N137TSR2VM SMT 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 Option Tape and Reel (1,000 units per reel)
1
2
6
43 5
Definitions
1 Fairchild Logo
2 Device Numbe r
3DIN EN/IEC60747-5-5 Option (only appears on component
ordered with this option)
4 Two Digit Year Code, e.g., ‘16’
5 Two Digit Work Wee k Ranging from ‘01’ to ‘53’
6 Assembly Package Code
6N137
BYY
XXV
Figure 28. Top Mark
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 15
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Carrier Tape Specifications (Option SD)
Symbol Description Dimension in mm
W Tape Width 16.0 ± 0.3
t Tape Thickness 0.30 ± 0.05
P0Sprocket Hole Pitch 4.0 ± 0.1
D0Sprocket Hole Diameter 1.55 ± 0.05
E Sprocket Hole Location 1.75 ± 0.10
F Pocket Location 7.5 ± 0.1
P22.0 ± 0.1
P Pocket Pitch 12.0 ± 0.1
A0Pocket Dimensions 10.30 ±0.20
B010.30 ±0.20
K04.90 ±0.20
W1Cover Tape Width 13.2 ± 0.2
d Cover Tape Thickness 0.1 Maximum
Maximum Component Rotation or Tilt 10°
R Minimum Bending Radius 30
d
0
P
t2
D0
1
1
W
User Direction of Feed
0
K
B0
A0W
E
D
F
P
P
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1. 6 16
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Carrier Tape Specifications (Option TSR2)
Symbol Description Dimension in mm
W Tape Width 24.0 ± 0.3
t Tape Thickness 0.40 ± 0.1
P0Sprocket Hole Pitch 4.0 ± 0.1
D0Sprocket Hole Diameter 1.55 ± 0.05
E Sprocket Hole Location 1.75 ± 0.10
F Pocket Location 11.5 ± 0.1
P22.0 ± 0.1
P Pocket Pitch 16.0 ± 0.1
A0Pocket Dimensions 12.80 ± 0.1
B010.35 ± 0.1
K05.7 ±0.1
W1Cover Tape Width 21.0 ± 0.1
d Cover Tape Thickness 0.1 Maximum
Maximum Component Rotation or Tilt 10°
R Minimum Bending Radius 30
d
0
P
t2
D0
1
1
W
User Direction of Feed
0
K
B0
A0W
E
D
F
P
P
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