NL17SZ125DTT1G - ON Semiconductor

May, 2012 − Rev. 13

1Publication Order Number:

NL17SZ125/D

NL17SZ125

Non-Inverting 3-State Buffer

The NL17SZ125 is a high performance non−inverting buffer operating

from a 1.65 V to 5.5 V supply.

Features

•Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V

•Designed for 1.65 V to 5.5 V VCC Operation

•Overvoltage Tolerant Inputs and Outputs

•LVTTL Compatible − Interface Capability With 5.0 V TTL Logic

with VCC = 3.0 V

•LVCMOS Compatible

•24 mA Balanced Output Sink and Source Capability

•Near Zero Static Supply Current Substantially Reduces System

Power Requirements

•3−State OE Input is Active−Low

•Replacement for NC7SZ125

•Chip Complexity = 36 FETs

•These Devices are Pb−Free and are RoHS Compliant

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Figure 1. Pinout (Top View)

VCC

IN A

OUT Y

GND

IN A OUT Y

Figure 2. Logic Symbol

PIN ASSIGNMENT

3 GND

IN A

OUT Y

OE Input

SC−88A (SOT−353)

DF SUFFIX

CASE 419A

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

FUNCTION TABLE

A Input Y Output

MARKING DIAGRAMS

X = Don’t Care

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SOT−553

XV5 SUFFIX

CASE 463B

M0 MG

M0 = Specific Device Code

M = Date Code

G= Pb−Free Package

M0 M G

M0 MG

TSOP−5

DT SUFFIX

CASE 483

(*Note: Microdot may be in either location)

*Date Code orientation and/or position may

vary depending upon manufacturing location.

UDFN6

1.0 x 1.0

CASE 517BX

NL17SZ125

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MAXIMUM RATINGS

Symbol Parameter Value Units

VCC DC Supply Voltage −0.5 to +7.0 V

VIN DC Input Voltage −0.5 to +7.0 V

VOUT DC Output Voltage −0.5 to +7.0 V

IIK DC Input Diode Current −50 mA

IOK DC Output Diode Current −50 mA

IOUT DC Output Sink Current ±50 mA

ICC DC Supply Current per Supply Pin ±100 mA

TSTG Storage Temperature Range −65 to +150 °C

TLLead Temperature, 1 mm from Case for 10 Seconds 260 °C

TJJunction Temperature Under Bias +150 °C

qJA Thermal Resistance (Note 1)

SC−88A/SOT−553

TSOP−5

350

230

°C/W

PDPower Dissipation in Still Air at 85°C 150 mW

MSL Moisture Sensitivity Level 1

FRFlammability Rating

Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

VESD ESD Withstand Voltage

Human Body Model (Note 2)

Machine Model (Note 3)

Charged Device Model (Note 4)

u2000

u200

N/A

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace with no air flow.

2. Tested to EIA/JESD22−A114−A.

3. Tested to EIA/JESD22−A115−A.

4. Tested to JESD22−C101−A.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Units

VCC DC Supply Voltage 1.65 5.5 V

VIN DC Input Voltage 0 5.5 V

VOUT DC Output Voltage 0 5.5 V

TAOperating Temperature Range −55 +125 °C

tr, tfInput Rise and Fall Time

VCC = 1.8 V ±0.15 V

VCC = 2.5 V ±0.2 V

VCC = 3.0 V ±0.3 V

VCC = 5.0 V ±0.5 V

5.0

ns/V

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DEVICE JUNCTION TEMPERATURE VERSUS

TIME TO 0.1% BOND FAILURES

Junction

Temperature °CTime, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

1 10 100 1000

FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLICS OCCUR

Figure 3. Failure Rate vs. Time Junction Temperature

NORMALIZED FAILURE RATE

TIME, YEARS

TJ = 130°C

TJ = 120°C

TJ = 110°C

TJ = 100°C

TJ = 90°C

TJ = 80°C

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter

VCC

(V)

TA = 255C−555C 3 TA 3 1255C

Units Condition

Min Typ Max Min Max

VIH High−Level Input

Voltage

1.65 to 1.95

2.3 to 5.5

0.75 VCC

0.7 VCC

0.75 VCC

0.7 VCC

VIL Low−Level Input

Voltage

1.65 to 1.95

2.3 to 5.5

0.25 VCC

0.3 VCC

0.25 VCC

0.3 VCC

VOH High−Level Output

Voltage

VIN = VIH

1.65

1.8

2.3

3.0

4.5

1.55

1.7

2.2

2.9

4.4

1.65

1.8

2.3

3.0

4.5

1.55

1.7

2.2

2.9

4.4

VIOH = −100 mA

1.65

2.3

3.0

4.5

1.29

1.9

2.4

2.3

3.8

1.52

2.15

2.80

2.68

4.20

1.29

1.9

2.4

2.3

3.8

V IOH = −4 mA

IOH = −8 mA

IOH = −16 mA

IOH = −24 mA

IOH = −32 mA

VOL Low−Level Output

Voltage

VIN = VIL

1.65

1.8

2.3

3.0

4.5

0.0

0.1

VIOL = 100 mA

1.65

2.3

3.0

4.5

0.08

0.10

0.15

0.22

0.24

0.30

0.40

0.55

0.24

0.30

0.40

0.55

V IOL = 4 mA

IOL = 8 mA

IOL = 16 mA

IOL = 24 mA

IOL = 32 mA

IIN Input Leakage Current 0 to 5.5 ±0.1 ±1.0 mAVIN = 5.5 V or GND

IOZ 3−State Output

Leakage

1.65 to 5.5 ±0.5 ±5.0 mAVIN = VIH or VIL

0 V ≤ VOUT ≤ 5.5 V

IOFF Power Off Leakage

Current

0 1.0 10 mAVIN = 5.5 V or

VOUT = 5.5 V

ICC Quiescent Supply

Current

5.5 1.0 10 mAVIN = 5.5 V or GND

NL17SZ125

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AC ELECTRICAL CHARACTERISTICS (tR = tF = 3.0 ns)

Symbol Parameter Condition

VCC

(V)

TA = 255C−555C 3 TA 3 1255C

Units

Min Typ Max Min Max

tPLH

tPHL

Propagation Delay

AN to YN

(Figures 4 and 5, Table 1)

RL = 1 MWCL = 15 pF 1.8 ±0.15 2.0 9.0 10 2.0 10.5 ns

RL = 1 MWCL = 15 pF 2.5 ±0.2 1.0 7.5 1.0 8.0

RL = 1 MWCL = 15 pF

RL = 500 WCL = 50 pF

3.3 ±0.3 0.8

1.2

5.2

5.7

0.8

1.2

5.5

6.0

RL = 1 MWCL = 15 pF

RL = 500 WCL = 50 pF

5.0 ±0.5 0.5

0.8

4.5

5.0

0.5

0.8

4.8

5.3

tPZH

tPZL

Output Enable Time

(Figures 6, 7and 8, Table 1)

RL = 250 WCL = 50 pF 1.8 ±0.15 2.0 7.6 9.5 2.0 10 ns

2.5 ±0.2 1.8 8.5 1.8 9.0

3.3 ±0.3 1.2 6.2 1.2 6.5

5.0 ±0.5 0.8 5.5 0.8 5.8

tPHZ

tPLZ

Output Disable Time

(Figures 6, 7and 8, Table 1)

RL and R1= 500 WCL = 50 pF 1.8 ±0.15 2.0 8.0 10 2.0 10.5 ns

2.5 ±0.2 1.5 8.0 1.5 8.5

3.3 ±0.3 0.8 5.7 0.8 6.0

5.0 ±0.5 0.3 4.7 0.3 5.0

CAPACITIVE CHARACTERISTICS

Symbol Parameter Condition Typical Units

CIN Input Capacitance VCC = 5.5 V, VI = 0 V or VCC 2.5 pF

COUT Output Capacitance VCC = 5.5 V, VI = 0 V or VCC 2.5 pF

CPD Power Dissipation Capacitance

(Note 5)

10 MHz, VCC = 3.3 V, VI = 0 V or VCC

10 MHz, VCC = 5.5 V, VI = 0 V or VCC

5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the no−load dynamic

power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NL17SZ125

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CL*

Figure 4. Switching Waveform

INPUT

*Includes all probe and jig capacitance.

A 1 MHz square input wave is recommended for

propagation delay tests.

Figure 5. tPLH or tPHL

OUTPUT

OE = GND

Figure 6. tPZL or tPLZ

A 1 MHz square input wave is recommended for

propagation delay tests.

Figure 7. tPZH or tPHZ

A 1 MHz square input wave is recommended for

propagation delay tests.

CL = 50 pF RL = 500 W

OUTPUT

INPUT R1 = 500 W

2 VCC

CL = 50 pF RL = 250 W

OUTPUT

VCC

INPUT

2.7 V

0 V

≈ 0 V

tPZH

≈ 3.0 V

tPHZ

tPZL tPLZ

Vmo

Vmi

VCC

VOH − 0.3 V

VOL + 0.3 V

GND

Vmi

Figure 8. AC Output Enable and Disable Waveform

50%

50% VCC

VCC

GND

tPLH tPHL

Table 1. OUTPUT ENABLE AND DISABLE TIMES

tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

Symbol

VCC

3.3 V + 0.3 V 2.7 V 2.5 V + 0.2 V

Vmi 1.5 V 1.5 V VCC/2

Vmo 1.5 V 1.5 V VCC/2

NL17SZ125

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DEVICE ORDERING INFORMATION

Device Package Shipping†

NL17SZ125DFT2G SC−88A (SOT−353)

(Pb−Free)

3000 / Tape & Reel

NLV17SZ125DFT2G* SC−88A (SOT−353)

(Pb−Free)

3000 / Tape & Reel

NL17SZ125XV5T2G SOT−553

(Pb−Free)

4000 / Tape & Reel

NL17SZ125DTT1G TSOP−5

(Pb−Free)

3000 / Tape & Reel

NL17SZ125CMUTCG UDFN6, 1.0 x 1.0 x 0.35P

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

NL17SZ125

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 419A−01 OBSOLETE. NEW STANDARD

419A−02.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

DIM

MIN MAX MIN MAX

MILLIMETERS

1.80 2.200.071 0.087

INCHES

B1.15 1.350.045 0.053

C0.80 1.100.031 0.043

D0.10 0.300.004 0.012

G0.65 BSC0.026 BSC

H--- 0.10---0.004

J0.10 0.250.004 0.010

K0.10 0.300.004 0.012

N0.20 REF0.008 REF

S2.00 2.200.079 0.087

B0.2 (0.008) MM

12 3

D 5 PL

−B−

SC−88A (SC−70−5/SOT−353)

CASE 419A−02

ISSUE K

0.65

0.025

0.65

0.025

0.50

0.0197

0.40

0.0157

1.9

0.0748

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NL17SZ125

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PACKAGE DIMENSIONS

SOT−553, 5 LEAD

CASE 463B

ISSUE B

0.08 (0.003) X

b5 PL

−X−

−Y−

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS

OF BASE MATERIAL.

12 3

1.35

0.0531

0.5

0.0197

ǒmm

inchesǓ

SCALE 20:1

0.5

0.0197

1.0

0.0394

0.45

0.0177

0.3

0.0118

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

HEDIM

MIN NOM MAX MIN

MILLIMETERS

0.50 0.55 0.60 0.020

INCHES

b0.17 0.22 0.27 0.007

D1.50 1.60 1.70 0.059

E1.10 1.20 1.30 0.043

e0.50 BSC

L0.10 0.20 0.30 0.004

0.022 0.024

0.009 0.011

0.063 0.067

0.047 0.051

0.008 0.012

NOM MAX

1.50 1.60 1.70 0.059 0.063 0.067

0.08 0.13 0.18 0.003 0.005 0.007

0.020 BSC

NL17SZ125

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PACKAGE DIMENSIONS

TSOP−5

CASE 483−02

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS

OF BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

5. OPTIONAL CONSTRUCTION: AN

ADDITIONAL TRIMMED LEAD IS ALLOWED

IN THIS LOCATION. TRIMMED LEAD NOT TO

EXTEND MORE THAN 0.2 FROM BODY.

DIM MIN MAX

MILLIMETERS

A3.00 BSC

B1.50 BSC

C0.90 1.10

D0.25 0.50

G0.95 BSC

H0.01 0.10

J0.10 0.26

K0.20 0.60

L1.25 1.55

M0 10

S2.50 3.00

123

54 S

0.7

0.028

1.0

0.039

ǒmm

inchesǓ

SCALE 10:1

0.95

0.037

2.4

0.094

1.9

0.074

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.20

CAB

T0.10

2X T0.20

NOTE 5

SEATING

PLANE

0.05

DETAIL Z

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PACKAGE DIMENSIONS

ÉÉÉ

UDFN6, 1x1, 0.35P

CASE 517BX

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. PACKAGE DIMENSIONS EXCLUSIVE OF

BURRS AND MOLD FLASH.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIMENSION: MILLIMETERS

RECOMMENDED

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTION

ÉÉ

ÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION

0.52

1.20

0.25

0.35

PITCH

PACKAGE

OUTLINE 1

DIM MIN MAX

MILLIMETERS

A0.50 0.65

A1 0.00 0.05

A3 0.13 REF

b0.17 0.23

D1.00 BSC

E1.00 BSC

e0.35

L0.20 0.40

L1 −−− 0.15

L3 0.26 0.33

A B

BOTTOM VIEW

L6X

NOTE 3

0.08 C

PIN ONE

REFERENCE

TOP VIEW

0.08 C

0.05 C

CSEATING

PLANE

SIDE VIEW

DETAIL B

0.07 BC

0.05 C

DETAIL A

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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NL17SZ125/D

PUBLICATION ORDERING INFORMATION

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USA/Canada

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Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

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