PWRDWN
Driving PWRDWN low puts the outputs in high impedance,
stops the PLL, and reduces supply current to 50μA or less.
Driving PWRDWN high drives the outputs low until the
PLL locks. The outputs of two deserializers ca be bused to
form a 2:1 mux with the outputs controlled by PWRDWN.
Wait 100ns between disabling one deserializer (driving
PWRDWN low) and enabling the second one (driving
PWRDWN high) to avoid contention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the application
or reapplication of the parallel rate clock (RxCLK IN) rela-
tive to PWRDWN, or to a power-supply ramp for proper
PLL lock. The PLL lock time is set by an internal counter.
The maximum time to lock is 32,800 clock periods. Power
and clock should be stable to meet the lock time specifica-
tion. When the PLL is locking, the outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital cir-
cuits, outputs, PLL, and LVDS inputs. Bypass each VCC,
VCCO, PLL VCC, and LVDS VCC pin with high-frequency,
surface-mount ceramic 0.1μF and 0.001μF capacitors in
parallel as close to the device as possible, with the small-
est value capacitor closest to the supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer supe-
rior signal quality compared to ribbon cable and tend to
generate less EMI due to magnetic field canceling effects.
Balanced cables pick up noise as common mode, which
is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer print-
edcircuit board (PCB) with separate layers for power,
ground, LVDS inputs, and digital signals is recommended.
ESD Protection
The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler-
ance is rated for IEC 61000-4-2, Human Body Model and
ISO 10605 standards. IEC 61000-4-2 and ISO 10605
specify ESD tolerance for electronic systems. The IEC
61000-4-2 discharge components are CS = 150pF and
RD = 330Ω (Figure 14). For IEC 61000-4-2, the LVDS
inputs are rated for ±8kV Contact Discharge and ±15kV
Air Discharge. The Human Body Model discharge com-
ponents are CS = 100pF and RD = 1.5kΩ (Figure 15).
For the Human Body Model, all pins are rated for ±5kV
Contact Discharge. The ISO 10605 discharge compo-
nents are CS = 330pF and RD = 2kΩ (Figure 16). For
ISO 10605, the LVDS inputs are rated for ±8kV Contact
Discharge and ±25kV Air Discharge.
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND. DCB/NC is not 5V tolerant. The input voltage range
for DCB/NC is nominally ground to VCC. Normally, DCB/
NC is connected to VCC or ground.
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 15. Human Body ESD Test Circuit
Figure 16. ISO 10605 Contact Discharge ESD Test Circuit
CS
150pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50Ω TO 100Ω
RD
330Ω
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MΩ
RD
1.5kΩ
CS
100pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50Ω TO 100Ω
R
D
2kΩ
C
S
330pF
MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
www.maximintegrated.com Maxim Integrated
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