General Description
The MAX8795A includes a high-performance step-up
regulator, two linear-regulator controllers, and five high-
current operational amplifiers for active-matrix, thin-film
transistor (TFT), liquid-crystal displays (LCDs). Also
included is a logic-controlled, high-voltage switch with
adjustable delay.
The step-up DC-DC converter provides the regulated
supply voltage for the panel source driver ICs. The con-
verter is a high-frequency (1.2MHz) current-mode regu-
lator with an integrated 20V n-channel MOSFET that
allows the use of ultra-small inductors and ceramic
capacitors. It provides fast transient response to pulsed
loads while achieving efficiencies over 85%.
The gate-on and gate-off linear-regulator controllers
provide regulated TFT gate-on and gate-off supplies
using external charge pumps attached to the switching
node. The MAX8795A includes five high-performance
operational amplifiers. These amplifiers are designed to
drive the LCD backplane (VCOM) and/or the gamma-
correction divider string. The device features high out-
put current (±130mA), fast slew rate (45V/µs), wide
bandwidth (20MHz), and rail-to-rail inputs and outputs.
The MAX8795A is available in a lead-free, 32-pin, thin
QFN package with a maximum thickness of 0.8mm for
ultra-thin LCD panels, as well as in a 32-pin LQFP
package with 0.8mm pin pitch.
Applications
Notebook Computer Displays
LCD Monitor Panels
Automotive Displays
Features
o2.5V to 5.5V Input Supply Range
o1.2MHz Current-Mode Step-Up Regulator
Fast Transient Response to Pulsed Load
High-Accuracy Output Voltage (1%)
Built-In 20V, 3A, 0.16Ωn-Channel MOSFET
High Efficiency (85%)
oLinear-Regulator Controllers for VGON and VGOFF
oHigh-Performance Operational Amplifiers
±130mA Output Short-Circuit Current
45V/µs Slew Rate
20MHz, -3dB Bandwidth
Rail-to-Rail Inputs/Outputs
oLogic-Controlled, High-Voltage Switch with
Adjustable Delay
oTimer-Delay Fault Latch for All Regulator Outputs
oThermal-Overload Protection
o0.6mA Quiescent Current
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
STEP-UP
CONTROLLER
GATE-ON
CONTROLLER
SWITCH
CONTROL
GATE-OFF
CONTROLLER
REF
VCN VCP
VMAIN
LX
FB
PGND
AGND
DRVP
FBP
VCP
VGON
VCN
VGOFF
DEL
CTL
DRVN
FBN
NEG4
REF
POS4
NEG5
POS5
OUT4
OUT5
BGND
NEG2
POS2
OP3
POS3
OUT2
OUT3
POS1
OUT1
NEG1
SUP
COM
DRN
SRC
COMP
IN
VIN
MAX8795A
OP2
OP1
OP5
OP4
EP
Minimal Operating Circuit
19-0793; Rev 5; 5/12
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX8795AETJ+ -40°C to +85°C 32 Thi n QFN
MAX8795AGCJ+ -40°C to +105°C 32 LQ FP
MAX8795AGCJ/V+ -40°C to +105°C 32 LQ FP
MAX8795AGTJ+ -40°C to +105°C 32 TQ FN
MAX8795AGTJ/V+ -40°C to +105°C 32 TQ FN
Pin Configurations appear at end of data sheet.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive-qualified part.
EVALUATION KIT
AVAILABLE
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, CTL to AGND ...................................................-0.3V to +7.5V
COMP, FB, FBP, FBN, DEL, REF to AGND ....-0.3V to (VIN + 0.3V)
PGND, BGND to AGND ......................................................±0.3V
LX to PGND ............................................................-0.3V to +20V
SUP to AGND .........................................................-0.3V to +20V
DRVP to AGND.......................................................-0.3V to +36V
POS_, NEG_, OUT_ to AGND ...................-0.3V to (VSUP + 0.3V)
DRVN to AGND ...................................(VIN - 30V) to (VIN + 0.3V)
SRC to AGND .........................................................-0.3V to +40V
COM, DRN to AGND ................................-0.3V to (VSRC + 0.3V)
DRN to COM............................................................-30V to +30V
POS_ to NEG_ RMS Current ...................................5mA (Note 1)
OUT_ Maximum Continuous Output Current....................±75mA
LX Switch Maximum Continuous RMS Current .....................1.6A
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (derate 34.5mW/°C above +70°C) 2758mW
32-Pin LQFP (derate 48.4mW/°C above +70°C)....1652.9mW
Operating Temperature Range, E Grade ............-40°C to +85°C
Operating Temperature Range, G Grade .........-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= 0°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IN Supply Range VIN (Note 2) 2.5 6.0 V
IN Undervoltage-Lockout
Threshold VUVLO VIN rising, typical hysteresis = 50mV 2.05 2.25 2.45 V
VFB = VFBP = 1.3V, VFBN = 0V,
LX not switching 0.6 1.0
IN Quiescent Current IIN VFB = 1.2V, VFBP = 1.4V, VFBN = 0V,
LX switching 23
mA
Duration-to-Trigger Fault
Condition
FB or FBP below threshold or FBN above
threshold 200 ms
TA = +25°C to +85°C 1.238 1.250 1.262
REF Output Voltage No external load TA = 0°C to +85°C 1.232 1.250 1.266 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current In regulation 10 µA
REF Undervoltage Lockout
Threshold Rising edge; typical hysteresis = 160mV 1.15 V
Temperature rising +160
Thermal Shutdown Hysteresis 15 °C
MAIN STEP-UP REGULATOR
Output Voltage Range VMAIN VIN 18 V
Operating Frequency fOSC 1000 1200 1400 kHz
Oscillator Maximum Duty Cycle 86 90 93 %
TA = +25°C to +85°C 1.221 1.233 1.245
FB Regulation Voltage VFB No load TA = 0°C to +85°C 1.212 1.233 1.248 V
FB Fault Trip Level VFB falling 1.10 1.14 1.17 V
FB Load Regulation 0 < IMAIN < full load, transient only -1 %
FB Line Regulation VIN = 2.5V to 6V 0.1 ±0.4 %/ V
FB Input Bias Current VFB = 1.233V +100 +200 nA
Note 1: See Figure 2 for the op amp clamp structure.
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= 0°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB Transconductance ∆ICOMP = ±2.5µA 75 160 280 µS
FB Voltage Gain From FB to COMP 700 V/
V
LX On-Resistance RLX
(
ON
)
ILX = 200mA 160 260 mΩ
LX Leakage Current ILX VLX = 19V 10 20 µA
LX Current Limit ILIM VFB = 1.2V, duty cycle = 75% 2.5 3.0 3.5 A
Current-Sense Transresistance 0.1 0.2 0.3 V/A
Soft-Start Period tSS 14 ms
Soft-Start Step Size VREF /
128 V
OPERATIONAL AMPLIFIERS
SUP Supply Range VSUP 6.0 18.0 V
S U P O ver vol tag e Faul t Thr eshol d 18.0 19 19.9 V
SUP Supply Current ISUP Buffer configuration, VPOS_ = VSUP / 2,
no load 3.5 5.0 mA
Input Offset Voltage VOS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2 0 12 mV
Input Bias Current IBIAS (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2 -50 0 +50 nA
Input Common-Mode Voltage
Range VCM 0V
SUP V
Common-Mode Rejection Ratio CMRR 0 ≤ (VNEG_, VPOS_) ≤ VSUP 45 80 dB
Open-Loop Gain 125 dB
Output Voltage Swing, High VOH IOUT_ = 5mA VSUP -
100
VSUP -
50 mV
Output Voltage Swing, Low VOL IOUT_ = -5mA 50 100 mV
Short-Circuit Current To VSUP / 2, source or sink 75 130 mA
Power-Supply Rejection Ratio PSRR DC, 6V ≤ VSUP ≤ 18V,
(VNEG_, VPOS_) ≅ VSUP / 2 60 dB
Slew Rate 45 V/µs
-3dB Bandwidth RL = 10kΩ, CL = 10pF, buffer configuration 20 MHz
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVN = 100µA
1.231
1.250
1.269
V
FBP Fault Trip Level VFBP falling
0.96
1.00
1.04
V
FBP Input Bias Current IFBP VFBP = 1.25V
-50
+50
nA
FBP Effective Load-Regulation
Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA
-0.7
-1.5
%
FBP Line (IN) Regulation Error IDRVP = 100µA, 2.5V < VIN < 6V
±1
±10
mV
DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V
1
5
mA
DRVP Off-Leakage Current VFBP = 1.4V, VDRVP = 34V
0.01
10
µA
Soft-Start Period tSS
14
ms
Soft-Start Step Size VREF /
128 V
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= 0°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE-OFF LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN
IDRVN = 100µA, VREF - VFBN
0.984
1
1.015
V
FBN Fault Trip Level
VFBN rising
370
420
470
mV
FBN Input Bias Current IFBN
VFBN = 0.25V
-50
+50
nA
FBN Effective Load-Regulation
Error (Transconductance)
VDRVN = -10V, IDRVN = 50µA to 1mA
11
25
mV
FBN Line (IN) Regulation Error
IDRVN = 0.1mA, 2.5V < VIN < 6V
±0.7
±5
mV
DRVN Source Current IDRVN
VFBN = 300mV, VDRVN = -10V
1
5
mA
DRVN Off-Leakage Current
VFBN = 0V, VDRVN = -25V
-0.01
-10
µA
Soft-Start Period tSS
14
ms
Soft-Start Step Size
(VREF -
VFBN) /
128
V
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current During startup, VDEL = 1V 4 5 6 µA
DEL Turn-On Threshold VTH
(
DEL
)
1.19 1.25 1.31 V
DEL Discharge Switch
On-Resistance During UVLO, VIN = 2.0V 20 Ω
CTL Input Low Voltage VIN = 2.5V to 5.5V 0.6 V
CTL Input High Voltage VIN = 2.5V to 5.5V 2 V
CTL Input Leakage Current CTL = AGND or IN -1 +1 µA
CTL-to-SRC Propagation Delay 100 ns
SRC Input Voltage Range 36 V
VDEL = 1.5V, CTL = IN 200 300
SRC Input Current ISRC VDEL = 1.5V, CTL = AGND 115 200 µA
S RC - to- C O M S w i tch On- Resi stance RSRC
(
ON
)
VDEL = 1.5V, CTL = IN 5 10 Ω
D RN - to- C O M S w i tch
On- Resi stance RDRN
(
ON
)
VDEL = 1.5V, CTL = AGND 30 60 Ω
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
IN Supply Range VIN (Note 2) 2.5 6.0 V
IN Undervoltage-Lockout
Threshold VUVLO VIN rising, typical hysteresis = 150mV 2.05 2.45 V
VFB = VFBP = 1.3V, VFBN = 0V,
LX not switching 1.0
IN Quiescent Current IIN VFB = 1.2V, VFBP = 1.4V, VFBN = 0V,
LX switching 3
mA
REF Output Voltage No external load 1.218 1.277 V
REF Undervoltage-Lockout
Threshold Rising edge; typical hysteresis = 160mV 1.15 V
MAIN STEP-UP REGULATOR
Output Voltage Range VMAIN VIN 18 V
Operating Frequency fOSC 900 1400 kHz
FB Regulation Voltage VFB No load 1.198 1.260 V
FB Line Regulation VIN = 2.5V to 6V ±0.4 %/ V
FB Transconductance ∆ICOMP = ±2.5µA 75 280 µS
LX On-Resistance RLX
(
ON
)
ILX = 200mA 260 mΩ
LX Current Limit ILIM VFB = 1.2V, duty cycle = 75% 2.5 3.5 A
OPERATIONAL AMPLIFIERS
SUP Supply Range VSUP 618V
SUP Overvoltage Fault Threshold 18.0 19.9 V
SUP Supply Current ISUP Buffer configuration, VPOS_ = VSUP / 2,
no load 5mA
Input Offset Voltage VOS (VNEG_, VPOS_, IOUT_) = ≅ VSUP / 2 12 mV
Input Common-Mode Voltage
Range VCM 0V
SUP V
Output Voltage Swing, High VOH IOUT_ = 5mA VSUP -
100 mV
Output Voltage Swing Low VOL IOUT_ = -5mA 100
Source 75
Short-Circuit Current To VSUP / 2 Sink 75 mA
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 100µA 1.210 1.280 V
FBP Effective Load-Regulation
Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA -1.5 %
FBP Line (IN) Regulation Error IDRVP = 100µA, 2.5V < VIN < 6V 10 mV
DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V 1 mA
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= -40°C to +85°C, unless otherwise noted.) (Note 3)
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
GATE-OFF LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 100µA, VREF - VFBN 0.972 1.022 V
FBN Effective Load-Regulation
Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA 25 mV
FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.5V < VIN < 6V ±5 mV
DRVN Source Current IDRVN VFBN = 300mV, VDRVN = -10V 1 mA
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current During startup, VDEL = 1V 4 6 µA
DEL Turn-On Threshold VTH
(
DEL
)
1.19 1.31 V
CTL Input Low Voltage VIN = 2.5V to 5.5V 0.6 V
CTL Input High Voltage VIN = 2.5V to 5.5V 2 V
SRC Input Voltage Range 36 V
VDEL = 1.5V, CTL = IN 300
SRC Input Current ISRC VDEL = 1.5V, CTL = AGND 200 µA
S RC - to- C O M S w i tch On- Resi stance RSRC
(
ON
)
VDEL = 1.5V, CTL = IN 10 Ω
D RN - to- C O M S w i tch On- Resi stance RDRN
(
ON
)
VDEL = 1.5V, CTL = AGND 60 Ω
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= 0°C to +105°C. Typical values are at TA= +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IN Supply Range VIN (Note 2) 2.5 6.0 V
IN Undervoltage-Lockout
Threshold VUVLO VIN rising, typical hysteresis = 50mV 2.05 2.25 2.45 V
VFB = VFBP = 1.3V, VFBN = 0V,
LX not switching 0.6 1.0
IN Quiescent Current IIN VFB = 1.2V, VFBP = 1.4V, VFBN = 0V,
LX switching 23
mA
Duration-to-Trigger Fault
Condition
VFB or FBP below threshold or FBN above
threshold 200 ms
TA = +25°C to +105°C 1.238 1.250 1.262
REF Output Voltage No external load TA = 0°C to +105°C 1.232 1.250 1.266 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current In regulation 10 µA
REF Undervoltage-Lockout
Threshold Rising edge, typical hysteresis = 160mV 1.15 V
Temperature rising +160
Thermal Shutdown Hysteresis 15 °C
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= 0°C to +105°C. Typical values are at TA= +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAIN STEP-UP REGULATOR
Output Voltage Range VMAIN VIN 18 V
Operating Frequency fOSC 1000 1200 1400 kHz
Oscillator Maximum Duty Cycle 86 90 93 %
TA = +25°C to +105°C 1.221 1.233 1.245
FB Regulation Voltage VFB No load TA = 0°C to +105°C 1.212 1.233 1.248 V
FB Fault Trip Level VFB falling 1.10 1.14 1.17 V
FB Load Regulation 0 < IMAIN < full load, transient only -1
FB Line Regulation VIN = 2.5V to 6V 0.1 ±0.4 %/V
FB Input Bias Current VFB = 1.233V +100 +200 nA
FB Transconductance ∆ICOMP = ±2.5µA 75 160 280 µS
FB Voltage Gain From FB to COMP 700 V/V
LX On-Resistance RLX
(
ON
)
ILX = 200mA 160 300 mΩ
LX Leakage Current ILX VLX = 19V 10 20 µA
LX Current Limit ILIM VFB = 1.2V, duty cycle = 75% 2.5 3.0 3.5 A
Current-Sense Transresistance 0.1 0.2 0.3 V/A
Soft-Start Period tSS 14 ms
Soft-Start Step Size VREF /
128 V
OPERATIONAL AMPLIFIERS
SUP Supply Range VSUP 6.0 18.0
SUP Overvoltage Fault Threshold 18.0 19 19.9 V
SUP Supply Current ISUP Buffer configuration, VPOS_ = VSUP / 2,
no load 3.5 5.0 mA
Input Offset Voltage VOS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2 0 12 mV
Input Bias Current IBIAS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2 -50 0 +50 nA
Input Common-Mode Voltage
Range VCM 0V
SUP V
Common-Mode Rejection Ratio CMRR 0 ≤ (VNEG_, VPOS_) ≤ VSUP 45 80 dB
Open-Loop Gain 125 dB
Output Voltage Swing, High VOH IOUT_ = 5mA VSUP -
100
VSUP -
50 mV
Output Voltage Swing, Low VOL IOUT_ = -5mA 50 100 mV
Short-Circuit Current To VSUP / 2, source or sink 75 130 mA
Power-Supply Rejection Ratio PSRR DC, 6V ≤ VSUP ≤ 18V,
(VNEG_, VPOS_) ≅ VSUP / 2 60 dB
Slew Rate 45 V/µs
-3dB Bandwidth RL = 10kΩ, CL = 10pF, buffer configuration 20 MHz
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= 0°C to +105°C. Typical values are at TA= +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 100µA 1.231 1.250 1.269 V
FBP Fault Trip Level VFBP falling 0.96 1.00 1.04 V
FBP Input Bias Current IFBP VFBP = 1.25V -50 +50 nA
FBP Effective Load-Regulation
Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA -0.7 -1.5 %
FBP Line (IN) Regulation Error IDRVP = 100µA, 2.5V < VIN < 6V ±1 ±10 mV
DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V 1 5
mA
DRVP Off-Leakage Current VFBP = 1.4V, VDRVP = 34V 0.01 10 µA
Soft-Start Period tSS 14 ms
Soft-Start Step Size
VREF /
128
V
GATE-OFF LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 100µA, VREF - VFBN 0.984 1 1.015 V
FBN Fault Trip Level VFBN rising 340 420 510 mV
FBN Input Bias Current IFBN VFBN = 0.25V -50 +50 nA
FBN Effective Load-Regulation
Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA 11 25 mV
FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.5V < VIN < 6V ±0.7 ±5 mV
DRVN Source Current IDRVN VFBN = 300mV, VDRVN = -10V 1 5 mA
DRVN Off-Leakage Current VFBN = 0V, VDRVN = -25V -0.01 -10 µA
Soft-Start Period tSS 14 ms
Soft-Start Step Size
(VREF -
VFBN) /
128
V
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current During startup, VDEL = 1V 4 5 6 µA
DEL Turn-On Threshold VTH
(
DEL
)
1.19 1.25 1.31 V
DEL Discharge Switch
On-Resistance During UVLO, VIN = 2.0V 20 Ω
CTL Input Low Voltage VIN = 2.5V to 5.5V 0.6 V
CTL Input High Voltage VIN = 2.5V to 5.5V 2 V
CTL Input Leakage Current CTL = AGND or IN -1 +1 µA
CTL-to-SRC Propagation Delay 100 ns
SRC Input Voltage Range 36 V
VDEL = 1.5V, CTL = IN 200 300
SRC Input Current ISRC VDEL = 1.5V, CTL = AGND 115 200 µA
S RC - to- C O M S w i tch On- Resi stance RSRC
(
ON
)
VDEL = 1.5V, CTL = IN 5 12 Ω
D RN- to-C OM S w i tch On- Resi stance RDRN
(
ON
)
VDEL = 1.5V, CTL = AGND 30 70 Ω
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= -40°C to +105°C, unless otherwise noted.) (Note3)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
IN Supply Range VIN (Note 2) 2.5 6.0 V
IN Undervoltage-Lockout
Threshold VUVLO VIN rising, typical hysteresis = 150mV 2.05 2.45 V
VFB = VFBP = 1.3V, VFBN = 0V,
LX not switching 1.0
IN Quiescent Current IIN VFB = 1.2V, VFBP = 1.4V, VFBN = 0V,
LX switching 3
mA
REF Output Voltage No external load 1.218 1.277 V
REF Undervoltage-Lockout
Threshold Rising edge, typical hysteresis = 160mV 1.15 V
MAIN STEP-UP REGULATOR
Output Voltage Range VMAIN VIN 18 V
Operating Frequency fOSC 900 1400 kHz
FB Regulation Voltage VFB No load 1.198 1.260 V
FB Line Regulation VIN = 2.5V to 6V ±0.4 %/ V
FB Transconductance ∆ICOMP = ±2.5µA 75 280 µS
LX On-Resistance RLX
(
ON
)
ILX = 200mA 300 mΩ
LX Current Limit ILIM VFB = 1.2V, duty cycle = 75% 2.5 3.5 A
OPERATIONAL AMPLIFIERS
SUP Supply Range VSUP 618V
SUP Overvoltage Fault Threshold 18.0 19.9 V
SUP Supply Current ISUP Buffer configuration, VPOS_ = VSUP / 2,
no load 5mA
Input Offset Voltage VOS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2 12 mV
Input Common-Mode Voltage
Range VCM 0V
SUP V
Output Voltage Swing, High VOH IOUT_ = 5mA VSUP -
100 mV
Output Voltage Swing, Low VOL IOUT_ = -5mA 100 mV
Source 75
Short-Circuit Current To VSUP / 2 Sink 75 mA
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
10 ______________________________________________________________________________________
Note 2: For 5.5V < VIN < 6.0V, use MAX8795A for no longer than 1% of IC lifetime. For continuous operation, input voltage should
not exceed 5.5V.
Note 3: Specifications to -40°C and +105°C are guaranteed by design, not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VMAIN = VSUP = 14V, VPGND = VAGND = VBGND = 0V, IREF = 25µA, TA= -40°C to +105°C, unless otherwise noted.) (Note3)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
GATE-ON LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 100µA 1.210 1.280 V
FBP Effective Load-Regulation
Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA -1.5 %
FBP Line (IN) Regulation Error IDRVP = 100µA, 2.5V < VIN < 6V 10 mV
DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V 1 mA
GATE-OFF LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 100µA, VREF - VFBN 0.972 1.022 V
FBN Effective Load-Regulation
Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA 25 mV
FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.5V < VIN < 6V ±5 mV
DRVN Source Current IDRVN VFBN = 300mV, VDRVN = -10V 1 mA
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
DEL Capacitor Charge Current During startup, VDEL = 1V 4 6 µA
DEL Turn-On Threshold VTH
(
DEL
)
1.19 1.31 V
CTL Input Low Voltage VIN = 2.5V to 5.5V 0.6 V
CTL Input High Voltage VIN = 2.5V to 5.5V 2 V
SRC Input Voltage Range 36 V
VDEL = 1.5V, CTL = IN 300
SRC Input Current ISRC VDEL = 1.5V, CTL = AGND 200 µA
SRC-to-COM Switch
On-Resistance RSRC
(
ON
)
VDEL = 1.5V, CTL = IN 12 Ω
DRN-to-COM Switch
On-Resistance RDRN
(
ON
)
VDEL = 1.5V, CTL = AGND 70 Ω
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________
11
10µs/div
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE
13.9V
50mA
C
MAX8795A toc05
B
0A
A
A: LOAD CURRENT, 1A/div
B: VMAIN, 200mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 1A/div
TIMER-DELAYED OVERLOAD PROTECTION
MAX8795A toc06
40ms/div
A: VMAIN, 2V/div
B: INDUCTOR CURRENT, 1A/div
A
B
0A
0U
REF VOLTAGE LOAD REGULATION
MAX8795A toc07
LOAD CURRENT (µA)
REF VOLTAGE (V)
40302010
1.2475
1.2480
1.2485
1.2490
1.2495
1.2500
1.2470
050
GATE-ON REGULATOR LINE REGULATION
MAX8795A toc08
INPUT VOLTAGE (V)
VOLTAGE ERROR (%)
29282726
-0.6
-0.4
-0.2
0
-0.8
25 30
IPOS = 20mA
GATE-ON REGULATOR LOAD REGULATION
MAX8795A toc09
LOAD CURRENT (mA)
VOLTAGE ERROR (%)
15105
-0.3
-0.1
-0.5
020
IBOOST = 200mA
A
0V
B
0V
C
0A
STEP-UP REGULATOR SOFT-START
(HEAVY LOAD)
MAX8795A toc04
2ms/div
A: VIN, 5V/div
B: VMAIN, 5V/div
C: INDUCTOR CURRENT, 1A/div
STEP-UP EFFICIENCY
vs. LOAD CURRENT
MAX9795A toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010
75
80
85
90
70
1 1000
VIN = 5V
VMAIN = 13.9V
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
MAX9795A toc02
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
5.04.54.03.53.0
1.1
1.2
1.3
1.4
1.0
2.5 5.5
STEP-UP SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX8795A toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.55.04.54.03.53.0
3
9
6
12
15
18
0
2.5 6.0
NO LOAD, SUP DISCONNECTED,
R1 = 221kΩ, R2 = 21.5kΩ
CURRENT INTO INDUCTOR
CURRENT INTO IN PIN
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 5V, VMAIN = 14V, VGON = 25V, VGOFF = -10V, TA= +25°C, unless otherwise noted.)
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
12 ______________________________________________________________________________________
GATE-OFF REGULATOR LINE REGULATION
MAX8795A toc10
INPUT VOLTAGE (V)
VOLTAGE ERROR (%)
-10-12-14
-0.8
-0.4
-0.6
-0.2
0.2
0
0.4
-1.0
-16
INEG = 50mA
GATE-OFF REGULATOR LOAD REGULATION
MAX8795A toc11
LOAD CURRENT (mA)
VOLTAGE ERROR (%)
40302010
-0.8
-0.6
-0.4
-0.2
0
0.2
-1.0
050
IBOOST = 0mA
4ms/div
POWER-UP SEQUENCE
0V
MAX8795A toc12
B
0V
A
A: VMAIN, 10V/div
B: VPOS, 20V/div
C: VNEG, 10V/div
D: VCOM, 20V/div
0V
C
D
0V
SUP SUPPLY CURRENT
vs. SUP VOLTAGE
ISUP (mA)
MAX8795A toc13
6 8 10 12 1614 18
2.8
3.1
3.0
2.9
3.3
3.2
3.5
3.4
3.6
VSUP (V) 4µs/div
OPERATIONAL-AMPLIFIER
RAIL-TO-RAIL INPUT/OUTPUT
0V
MAX8795A toc14
B
0V
A
A: INPUT SIGNAL, 5V/div
B: OUTPUT SIGNAL, 5V/div
VSUP = 15V
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 5V, VMAIN = 14V, VGON = 25V, VGOFF = -10V, TA= +25°C, unless otherwise noted.)
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________
13
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 5V, VMAIN = 14V, VGON = 25V, VGOFF = -10V, TA= +25°C, unless otherwise noted.)
400ns/div
OPERATIONAL-AMPLIFIER
LOAD-TRANSIENT RESPONSE
0V
MAX8795A toc15
B
-50mA
A
A: OUTPUT VOLTAGE, 1V/div, AC-COUPLED
B: OUTPUT CURRENT, 50mA/div
+50mA
0mA
1µs/div
OPERATIONAL-AMPLIFIER
LARGE-SIGNAL RESPONSE
0V
MAX8795A toc16
B
A
A: INPUT SIGNAL, 5V/div
B: OUTPUT SIGNAL, 5V/div
0V
VSUP = 15V
400ns/div
OPERATIONAL-AMPLIFIER
SMALL-SIGNAL RESPONSE
0V
MAX8795A toc17
B
A
A: INPUT SIGNAL, 100mV/div
B: OUTPUT SIGNAL, 100mV/div
0V
PIN NAME FUNCTION
1 SRC Switch Input. Source of the internal high-voltage p-channel MOSFET. Bypass SRC to PGND with a
minimum 0.1µF capacitor close to the pins.
2 REF Reference Bypass Terminal. Bypass REF to AGND with a minimum of 0.22µF close to the pins.
3 AGND Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power ground (PGND)
underneath the IC.
4 PGND
Power Ground. PGND is the source of the main step-up n-channel power MOSFET. Connect PGND to
the output-capacitor ground terminals through a short, wide PCB trace. Connect to analog ground
(AGND) underneath the IC.
5 OUT1 Operational-Amplifier 1 Output
6 NEG1 Operational-Amplifier 1 Inverting Input
7 POS1 Operational-Amplifier 1 Noninverting Input
8 OUT2 Operational-Amplifier 2 Output
9 NEG2 Operational-Amplifier 2 Inverting Input
10 POS2 Operational-Amplifier 2 Noninverting Input
11 BGND Analog Ground for Operational Amplifiers. Connect to power ground (PGND) underneath the IC.
12 POS3 Operational-Amplifier 3 Noninverting Input
13 OUT3 Operational-Amplifier 3 Output
14 SUP Operational-Amplifier Power Input. Positive supply rail for the operational amplifiers. Typically
connected to VMAIN. Bypass SUP to BGND with a 0.1µF capacitor.
15 POS4 Operational-Amplifier 4 Noninverting Input
16 NEG4 Operational-Amplifier 4 Inverting Input
Pin Description
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
17 OUT4 Operational-Amplifier 4 Output
18 POS5 Operational-Amplifier 5 Noninverting Input
19 NEG5 Operational-Amplifier 5 Inverting Input
20 OUT5 Operational-Amplifier 5 Output
21 LX n-Channel Power MOSFET Drain and Switching Node. Connect the inductor and Schottky diode to LX
and minimize the trace area for lowest EMI.
22 IN Supply Voltage Input. IN can range from 2.5V to 6V.
23 FB Step-Up Regulator Feedback Input. Regulates to 1.233V (nominal). Connect a resistive voltage-divider
from the output (VMAIN) to FB to analog ground (AGND). Place the divider within 5mm of FB.
24 COMP Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC from COMP to AGND.
See the Loop Compensation section for component selection guidelines.
25 FBP
Gate-On Linear-Regulator Feedback Input. FBP regulates to 1.25V (nominal). Connect FBP to the
center of a resistive voltage-divider between the regulator output and AGND to set the gate-on linear-
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
26 DRVP Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channel MOSFET. Connect DRVP to
the base of an external pnp pass transistor. See the Pass-Transistor Selection section.
27 FBN
Gate-Off Linear-Regulator Feedback Input. FBN regulates to 250mV (nominal). Connect FBN to the
center of a resistive voltage-divider between the regulator output and REF to set the gate-off linear-
regulator output voltage. Place the resistive voltage-divider within 5mm of FBN.
28 DRVN Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel MOSFET. Connect DRVN to
the base of an external npn pass transistor. See the Pass-Transistor Selection section.
29 DEL High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set the high-voltage
switch startup delay.
30 CTL
High-Voltage Switch Control Input. When CTL is high, the high-voltage switch between COM and SRC
is on and the high-voltage switch between COM and DRN is off. When CTL is low, the high-voltage
switch between COM and SRC is off and the high-voltage switch between COM and DRN is on. CTL is
inhibited by the undervoltage lockout or when the voltage on DEL is less than 1.25V.
31 DRN Switch Input. Drain of the internal high-voltage back-to-back p-channel MOSFETs connected to COM.
32 COM Internal High-Voltage MOSFET Switch Common Terminal. Do not allow the voltage on COM to exceed
VSRC.
— EP Exposed Paddle. Must be connected to AGND. Do not use as the only ground connection.
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 15
Typical Operating Circuit
The MAX8795A typical operating circuit (Figure 1) is a
complete power-supply system for TFT LCDs. The circuit
generates a +14V source-driver supply and +25V and
-10V gate-driver supplies. The input voltage range for the
IC is from +2.5V to +5.5V. The listed load currents in
Figure 1 are available from a +4.5V to +5.5V supply.
Table 1 lists some recommended components, and Table
2 lists the contact information of component suppliers.
C3
0.1µF
C4
0.1µF
C14
68pF
C11
0.1µF
LX
D1
L1
3.0µH
LX
C2
22µF
D2
VMAIN
14V/500mA
R1
137kΩ
1%
R2
13.3kΩ
1%
R3
6.8kΩ
R6
1kΩ
R19
100kΩ
R20
100kΩ
R17
100kΩ
R18
100kΩ
R15
100kΩ
R16
100kΩ
R13
100kΩ
R14
100kΩ
R11
100kΩ
R12
100kΩ
R4
191kΩ
1%
R5
10.0kΩ
1%
Q1
C5
0.47µF
VGON
25V/20mA
C6
0.1µF
LX
VIN
4.5V TO 5.5V
D3
Q2
C1
22µF
C12
220µF
C13
0.1µF
R10
10Ω
180kΩ
R9
6.8kΩ
C10
0.1µF
R7
324kΩ
1%
R8
31.6kΩ
1%
C9
0.22µF
C8
0.22µF
VGOFF
-10V/50mA
C7
0.033µF
TO VCOM
BACKPLANE
IN
COMP
DRVN
FBN
REF
FB
AGND
PGND
DRVP
FBP
SRC
COM
LX
DEL
NEG1
NEG2
OUT2
OUT3
NEG4
OUT4
NEG5
OUT5
OUT1
DRN
CTL
SUP
BGND
POS1
POS2
POS3
POS4
POS5
MAX8795A
EP
Figure 1. Typical Operating Circuit
DESIGNATION DESCRIPTION
C1 22µF, 6.3V X5R ceramic capacitor (1210)
TDK C3225X5R0J227M
C2 22µF, 16V X5R ceramic capacitor (1812)
TDK C4532X5X1C226M
D1 3A, 30V Schottky diode (M-flat)
Toshiba CMS02
D2, D3 200mA, 100V, dual ultra-fast diodes (SOT23)
Fairchild MMBD4148SE
DESIGNATION DESCRIPTION
L1 3.0µH, 3A inductor
Sumida CDRH6D28-3R0
Q1 200mA, 40V pnp bipolar transistor (SOT23)
Fairchild MMBT3906
Q2 200mA, 40V npn bipolar transistor (SOT23)
Fairchild MMBT3904
Table 1. Component List
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
16 ______________________________________________________________________________________
SUPPLIER PHONE FAX WEBSITE
Fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida 847-545-6700 847-545-6720 www.sumida.com
TDK 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec
Table 2. Component Suppliers
Detailed Description
The MAX8795A contains a high-performance step-up
switching regulator, two low-cost linear-regulator con-
trollers, multiple high-current operational amplifiers,
and startup timing and level-shifting functionality useful
for active-matrix TFT LCDs. Figure 2 shows the
MAX8795A functional diagram.
Main Step-Up Regulator
The main step-up regulator employs a current-mode,
fixed-frequency PWM architecture to maximize loop
bandwidth and provide fast transient response to
pulsed loads typical of TFT-LCD panel source drivers.
The 1.2MHz switching frequency allows the use of low-
profile inductors and ceramic capacitors to minimize
the thickness of LCD panel designs. The integrated
high-efficiency MOSFET and the IC’s built-in digital
soft-start functions reduce the number of external com-
ponents required while controlling inrush currents. The
output voltage can be set from VIN to 18V with an exter-
nal resistive voltage-divider.
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
Figure 3 shows the functional diagram of the step-up
regulator. An error amplifier compares the signal at FB
to 1.233V and changes the COMP output. The voltage
at COMP sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP output accordingly to produce the inductor peak
current necessary to service the load. To maintain sta-
bility at high duty cycles, a slope-compensation signal
is summed with the current-sense signal.
On the rising edge of the internal clock, the controller sets
a flip-flop, turning on the n-channel MOSFET and applying
the input voltage across the inductor. The current through
the inductor ramps up linearly, storing energy in its
magnetic field. Once the sum of the current-feedback
signal and the slope compensation exceeds the COMP
DVV
V
MAIN IN
MAIN
≈−
STEP-UP
CONTROLLER
GATE-ON
CONTROLLER
SWITCH
CONTROL
GATE-OFF
CONTROLLER
REF
VCN VCP
VMAIN
LX
FB
PGND
AGND
DRVP
FBP
VCP
VGON
VCN
VGOFF
DEL
CTL
DRVN
FBN
NEG4
REF
POS4
NEG5
POS5
OUT4
OUT5
BGND
NEG2
POS2
OP3
POS3
OUT2
OUT3
POS1
OUT1
NEG1
SUP
COM
DRN
SRC
COMP
IN
VIN
MAX8795A
OP2
OP1
OP5
OP4
EP
Figure 2. MAX8795A Functional Diagram
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 17
QR
S
RESET DOMINANT
CURRENT
SENSE
Σ
OSCILLATOR
SLOPE COMP
CLOCK
LX
PGND
FB
COMP
1.233V
1.14V
SOFT-
START VLIMIT
PWM
COMPARATOR
FAULT
COMPARATOR
ILIM
COMPARATOR
TO FAULT LATCH
ERROR AMP
Figure 3. Step-Up Regulator Functional Diagram
voltage, the controller resets the flip-flop and turns off
the MOSFET. Since the inductor current is continuous,
a transverse potential develops across the inductor that
turns on the diode (D1). The voltage across the induc-
tor then becomes the difference between the output
voltage and the input voltage. This discharge condition
forces the current through the inductor to ramp back
down, transferring the energy stored in the magnetic
field to the output capacitor and the load. The MOSFET
remains off for the rest of the clock cycle.
Gate-On Linear-Regulator Controller, REG P
The gate-on linear-regulator controller (REG P) is an
analog gain block with an open-drain n-channel output.
It drives an external pnp pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive sink current is at least 1mA. The regulator including
Q1 in Figure 1 uses a 0.47µF ceramic output capacitor
and is designed to deliver 20mA at 25V. Other output
voltages and currents are possible with the proper pass
transistor and output capacitor. See the
Pass-Transistor
Selection
and
Stability Requirements
sections.
REG P is typically used to provide the TFT-LCD gate
drivers’ gate-on voltage. Use a charge pump with as
many stages as necessary to obtain a voltage exceed-
ing the required gate-on voltage (see the
Selecting the
Number of Charge-Pump Stages
section). Note the
voltage rating of DRVP is 36V. If the charge-pump out-
put voltage can exceed 36V, an external cascode npn
transistor should be added as shown in Figure 4.
Alternately, the linear regulator can control an interme-
diate charge-pump stage while regulating the final
charge-pump output (Figure 5).
MAX8795A
DRVP
FBP
VMAIN FROM CHARGE-PUMP
OUTPUT
npn CASCODE
TRANSISTOR
pnp PASS
TRANSISTOR
VGON
Figure 4. Using Cascoded npn for Charge-Pump Output
Voltages > 36V
MAX8795A
DRVP
FBP
VGON
35V
LX
VMAIN
14V
0.22µF
0.1µF
0.1µF
0.47µF
47pF
150pF
274kΩ
1%
10.2kΩ
1%
6.8kΩ
68pF
Q1
Figure 5. The linear regulator controls the intermediate charge-
pump stage.
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
18 ______________________________________________________________________________________
REG P is enabled after the REF voltage exceeds 1.0V.
Each time it is enabled, the controller goes through a
soft-start routine that ramps up its internal reference
DAC in 128 steps.
Gate-Off Linear-Regulator Controller, REG N
The gate-off linear-regulator controller (REG N) is an
analog gain block with an open-drain p-channel output.
It drives an external npn pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed base-
drive source current is at least 1mA. The regulator
including Q2 in Figure 1 uses a 0.47µF ceramic output
capacitor and is designed to deliver 50mA at -10V. Other
output voltages and currents are possible with the proper
pass transistor and output capacitor (see the
Pass-
Transistor Selection
and
Stability Requirements
sections).
REG N is typically used to provide the TFT-LCD gate
drivers’ gate-off voltage. A negative voltage can be
produced using a charge-pump circuit as shown in
Figure 1. REG N is enabled after the voltage on REF
exceeds 1.0V. Each time it is enabled, the control goes
through a soft-start routine that ramps down its internal
reference DAC from VREF to 250mV in 128 steps.
Operational Amplifiers
The MAX8795A has five operational amplifiers. The opera-
tional amplifiers are typically used to drive the LCD back-
plane (VCOM) or the gamma-correction divider string.
They feature ±130mA output short-circuit current, 45V/µs
slew rate, and 20MHz/3dB bandwidth. The rail-to-rail input
and output capability maximizes system flexibility.
Short-Circuit Current Limit and Input Clamp
The operational amplifiers limit short-circuit current to
approximately ±130mA if the output is directly shorted to
SUP or to BGND. If the short-circuit condition persists, the
junction temperature of the IC rises until it reaches the
thermal-shutdown threshold (+160°C typ). Once the junc-
tion temperature reaches the thermal-shutdown threshold,
an internal thermal sensor immediately sets the thermal
fault latch, shutting off all the IC’s outputs. The device
remains inactive until the input voltage is cycled.
The operational amplifiers have 4V input clamp structures
in series with a 500Ωresistance and a diode (Figure 2).
Driving Pure Capacitive Load
The operational amplifiers are typically used to drive
the LCD backplane (VCOM) or the gamma-correction
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation.
As the operational amplifier’s capacitive load increases,
the amplifier’s bandwidth decreases and gain peaking
increases. A 5Ωto 50Ωsmall resistor placed between
OUT_ and the capacitive load reduces peaking, but also
reduces the gain. An alternative method of reducing
peaking is to place a series RC network (snubber) in par-
allel with the capacitive load. The RC network does not
continuously load the output or reduce the gain. Typical
values of the resistor are between 100Ωand 200Ω, and
the typical value of the capacitor is 10nF.
Undervoltage Lockout (UVLO)
The UVLO circuit compares the input voltage at IN with the
UVLO threshold (2.25V rising, 2.20V falling, typ) to ensure
the input voltage is high enough for reliable operation. The
50mV (typ) hysteresis prevents supply transients from
causing a restart. Once the input voltage exceeds the
UVLO rising threshold, startup begins. When the input volt-
age falls below the UVLO falling threshold, the controller
turns off the main step-up regulator, turns off the linear-
regulator outputs, and disables the switch control block;
the operational-amplifier outputs are high impedance.
Reference Voltage (REF)
The reference output is nominally 1.25V and can
source at least 50µA (see the
Typical Operating
Characteristics
). Bypass REF with a 0.22µF ceramic
capacitor connected between REF and AGND.
Power-Up Sequence and Soft-Start
Once the voltage on IN exceeds approximately 2.25V, the
reference turns on. With a 0.22µF REF bypass capacitor,
the reference reaches its regulation voltage of 1.25V in
approximately 1ms. When the reference voltage exceeds
1.0V, the IC enables the main step-up regulator, the gate-
on linear-regulator controller, and the gate-off linear-regu-
lator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a well-
defined startup behavior. Each output uses a 7-bit soft-start
DAC. For the step-up and the gate-on linear regulator, the
DAC output is stepped in 128 steps from zero up to the ref-
erence voltage. For the gate-off linear regulator, the DAC
output steps from the reference down to 250mV in 128
steps from zero up to the reference voltage. For the gate-
off linear regulator’s voltage ramp soft-start, the DAC output
steps from the reference down to 250mV in 128 steps. The
soft-start duration is 14ms (typ) for all three regulators, and
DEL remains pulled down to AGND during the soft start
period.
Once the main step-up regulator, the gate-on linear-regula-
tor controller, and the gate-off linear-regulator controller
reach regulation, a 5µA current source starts charging
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 19
CDEL. Once the CDEL capacitor voltage exceeds 1.25V
(typ), the switch-control block is and op amps are enabled
as shown in Figure 6. After the switch-control block is
enabled, COM can be connected to SRC or DRN through
the internal p-channel switches, depending upon the state of
CTL. Before startup and when IN is less than VUVLO, DEL is
internally connected to AGND to discharge CDEL. Select
CDEL to set the initial start-up delay and the switch-control
block startup delay times using the following equation:
Switch-Control Block
The switch-control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds VUVLO, the soft-start routine of all the
regulators is complete, there is no fault condition detect-
ed, and VDEL exceeds its turn-on threshold. Once acti-
vated and if CTL is high, the 5Ωinternal p-channel
switch (Q1) between COM and SRC turns on and the
CDELAYTIME
IA
V
DEL =×
µ
_.
6
125
2.25V
1.05V
INPUT
VOLTAGE
OK
SOFT-
START
BEGINS
SOFT-
START
ENDS
SWITCH
CONTROL
ENABLED
12ms
VIN
VREF
VMAIN
VGON
VGOFF
1.25V
VDEL
Figure 6. Power-Up Sequence
MAX8795A
FB OK
FBP OK
FBN OK
2.25V
5µA
REF
DRN
COM
SRC
Q1
Q2
CTL
DEL
IN
Figure 7. Switch-Control Block
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
20 ______________________________________________________________________________________
30Ωp-channel switch (Q2) between DRN and COM
turns off. If CTL is low, Q1 turns off and Q2 turns on.
Fault Protection
During steady-state operation, if the output of the main
regulator or any of the linear-regulator outputs does not
exceed its respective fault-detection threshold, the
MAX8795A activates an internal fault timer. If any condi-
tion or combination of conditions indicates a continuous
fault for the fault-timer duration (200ms typ), the
MAX8795A sets the fault latch to shut down all the outputs
except the reference. Once the fault condition is removed,
cycle the input voltage (below the UVLO falling threshold)
to clear the fault latch and reactivate the device. The fault-
detection circuit is disabled during the soft-start time.
Thermal-Overload Protection
Thermal-overload protection prevents excessive power dis-
sipation from overheating the MAX8795A. When the junc-
tion temperature exceeds +160°C, a thermal sensor
immediately activates the fault protection, which shuts
down all outputs except the reference, allowing the device
to cool down. Once the device cools down by approximate-
ly 15°C, cycle the input voltage (below the UVLO falling
threshold) to clear the fault latch and reactivate the device.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of +150°C.
Design Procedure
Main Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating,
and series resistance are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient-response time, and output voltage ripple. Size
and cost are also important factors to consider.
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the current
ripple, and therefore, reduce the peak current, which
decreases core losses in the inductor and conduction
losses in the entire power path. However, large inductor
values also require more energy storage and more turns of
wire, which increase size and can increase conduction
losses in the inductor. Low inductance values decrease
the size, but increase the current ripple and peak current.
Finding the best inductor involves choosing the best com-
promise between circuit efficiency, inductor size, and cost.
The equations used here include a constant LIR, which is
the ratio of the inductor peak-to-peak ripple current to the
average DC inductor current at the full load current. The
best trade-off between inductor size and circuit efficiency
for step-up regulators generally has an LIR between 0.3
and 0.6. However, depending on the AC characteristics of
the inductor core material and ratio of inductor resistance
to other power-path resistances, the best LIR can shift up
or down. If the inductor resistance is relatively high, more
ripple can be accepted to reduce the number of turns
required and increase the wire diameter. If the inductor
resistance is relatively low, increasing inductance to lower
the peak current can decrease losses throughout the
power path. If extremely thin high-resistance inductors are
used, as is common for LCD-panel applications, the best
LIR can increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficien-
cy improvements in typical operating regions.
Calculate the approximate inductor value using the typ-
ical input voltage (VIN), the maximum output current
(IMAIN(MAX)), the expected efficiency (ηTYP) taken from
an appropriate curve in the
Typical Operating
Characteristics
section, and an estimate of LIR based
on the above discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage (VIN(MIN)) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from the appropriate curve
in the
Typical Operating Characteristics
:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX8795A’s LX current limit (ILIM) should exceed IPEAK,
and the inductor’s DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor with
less than 0.1Ωseries resistance.
Considering the typical operating circuit, the maximum
load current (IMAIN(MAX)) is 500mA with a 14V output and
IVVV
LV f
II I
RIPPLE IN MIN MAIN IN MIN
MAIN OSC
PEAK IN DCMAX RIPPLE
=×−
××
=+
() ()
(, )
()
2
IIV
V
IN DCMAX MAIN MAX MAIN
IN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
I f LIR
IN
MAIN
MAIN IN
MAIN MAX OSC
TYP
=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
2
()
η
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 21
a typical input voltage of 5V. Choosing an LIR of 0.5 and
estimating efficiency of 85% at this operating point:
Using the circuit’s minimum input voltage (4.5V) and
estimating efficiency of 80% at that operating point:
The ripple current and the peak current are:
Output-Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharging
of the output capacitance, and the ohmic ripple due to the
capacitor’s equivalent series resistance (ESR):
where IRIPPLE is the RIPPLE inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output voltage ripple is typically dominated by
VRIPPLE(C). The voltage rating and temperature charac-
teristics of the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injection
into the IC. A 22µF ceramic capacitor is used in the typi-
cal applications circuit (Figure 1) because of the high
source impedance seen in typical lab setups. Actual
applications usually have much lower source impedance
since the step-up regulator often runs directly from the
output of another regulated supply. Typically, CIN can
be reduced below the values used in the typical applica-
tions circuit. Ensure a low-noise supply at IN by using
adequate CIN. Alternately, greater voltage variation can
be tolerated on CIN if IN is decoupled from CIN using an
RC lowpass filter (see R10 and C13 in Figure 1).
Rectifier Diode
The MAX8795A’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 2A Schottky
diode complements the internal MOSFET well.
Output-Voltage Selection
The output voltage of the main step-up regulator can be
adjusted by connecting a resistive voltage-divider from the
output (VMAIN) to AGND with the center tap connected to
FB (see Figure 1). Select R2 in the 10kΩto 50kΩrange.
Calculate R1 with the following equation:
where VFB, the step-up regulator’s feedback set point,
is 1.233V. Place R1 and R2 close to the IC.
Loop Compensation
Choose RCOMP to set the high-frequency integrator
gain for fast transient response. Choose CCOMP to set
the integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient-response waveforms.
Charge Pumps
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement. Figures 8 and 9 show the positive and
negative charge-pump output voltages for a given
VMAIN for one-, two-, and three-stage charge pumps.
RVV C
LI
CVC
IR
COMP IN OUT OUT
MAIN MAX
COMP OUT OUT
MAIN MAX COMP
≈×× ×
×
≈×
××
253
10
()
()
RR V
V
MAIN
FB
12 1=× −
⎛
⎝
⎜⎞
⎠
⎟
:
() ( )
()
() ( )
VV V
VI
C
VV
Vf
and
VIR
RIPPLE RIPPLE C RIPPLE ESR
RIPPLE C MAIN
OUT
MAIN IN
MAIN OSC
RIPPLE ESR PEAK ESR COUT
=+
≈−
⎛
⎝
⎜⎞
⎠
⎟
≈
IVVV
H V MHz A
IA
AA
RIPPLE
PEAK
=×−
µ× × ≈
=+ ≈
45 14 45
33 14 12 077
194 077
2233
.( .)
..
.
...
IAV
VA
IN DCMAX (, ) .
..
.=×
×≈
05 14
45 08 194
LV
V
VV
A MHz H=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟≈µ
5
14
14 5
05 12
085
05 33
2
..
.
..
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
22 ______________________________________________________________________________________
The number of positive charge-pump stages is given by:
where nPOS is the number of positive charge-pump
stages, VGON is the gate-on linear-regulator REG P out-
put, VMAIN is the main step-up regulator output, VDis
the forward-voltage drop of the charge-pump diode,
and VDROPOUT is the dropout margin for the linear reg-
ulator. Use VDROPOUT = 0.3V.
The number of negative charge-pump stages is given by:
where nNEG is the number of negative charge-pump
stages, VGOFF is the gate-off linear-regulator REG N
output, VMAIN is the main step-up regulator output, VD
is the forward-voltage drop of the charge-pump diode,
and VDROPOUT is the dropout margin for the linear reg-
ulator. Use VDROPOUT = 0.3V.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to VMAIN and the first stage of the
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
stage to VIN or another available supply. If the first
charge-pump stage is powered from VIN, the above
equations become:
Flying Capacitors
Increasing the flying-capacitor (CX) value lowers the
effective source impedance and increases the output-
current capability. Increasing the capacitance indefinitely
has a negligible effect on output-current capability
because the internal switch resistance and the diode
impedance place a lower limit on the source imped-
ance. A 0.1µF ceramic capacitor works well in most
low-current applications. The flying capacitor’s voltage
rating must exceed the following:
where n is the stage number in which the flying capaci-
tor appears, and VMAIN is the output voltage of the
main step-up regulator.
VnV
CX MAIN
>×
nVV V
VV
nVV V
VV
POS GON DROPOUT IN
MAIN D
NEG GOFF DROPOUT IN
MAIN D
=++
−×
=−+ +
−×
2
2
nVV
VV
NEG GOFF DROPOUT
MAIN D
=−+
−×2
nVV V
VV
POS GON DROPOUT MAIN
MAIN D
=+−
−×2
POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. VMAIN
VMAIN (V)
G_ON (V)
1210864
10
20
30
40
50
60
0
214
2-STAGE CHARGE PUMP
3-STAGE CHARGE PUMP
VD = 0.3V TO 1V
1-STAGE CHARGE PUMP
Figure 8. Positive Charge-Pump Output Voltage vs. VMAIN
NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. VMAIN
VMAIN (V)
G_OFF (V)
1210864
-40
-35
-30
-25
-20
-15
-10
-5
-0
-45
214
1-STAGE
CHARGE PUMP
2-STAGE
CHARGE PUMP
3-STAGE
CHARGE PUMP
VD = 0.3V TO 1V
Figure 9. Negative Charge-Pump Output Voltage vs. VMAIN
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 23
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where COUT_CP is the output capacitor of the charge
pump, ILOAD_CP is the load current of the charge
pump, and VRIPPLE_CP is the peak-to-peak value of the
output ripple.
Charge-Pump Rectifier Diodes
Use low-cost silicon switching diodes with a current rat-
ing equal to or greater than two times the average
charge-pump input current. If it helps avoid an extra
stage, some or all of the diodes can be replaced with
Schottky diodes with an equivalent current rating.
Linear-Regulator Controllers
Output-Voltage Selection
Adjust the gate-on linear-regulator (REG P) output volt-
age by connecting a resistive voltage-divider from the
REG P output to AGND with the center tap connected
to FBP (Figure 1). Select the lower resistor of the divider
R5 in the range of 10kΩto 30kΩ. Calculate the upper
resistor R4 with the following equation:
where VFBP = 1.25V (typ).
Adjust the gate-off linear-regulator REG N output volt-
age by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R8 in the 20kΩto 50kΩrange.
Calculate R7 with the following equation:
where VFBN = 250mV, VREF = 1.25V. Note that REF can
only source up to 50µA; using a resistor less than 20kΩ
for R8 results in higher bias current than REF can supply.
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (hFE), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
where IDRV is the minimum guaranteed base-drive cur-
rent, VBE is the transistor’s base-to-emitter forward volt-
age drop, and RBE is the pullup resistor connected
between the transistor’s base and emitter. Furthermore,
the transistor’s current gain increases the linear regula-
tor’s DC loop gain (see the
Stability Requirements
sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 100 at the
maximum output current can be difficult to stabilize and
are not recommended unless the high gain is needed to
meet the load-current requirements.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator can support.
Also, the package’s power dissipation limits the usable
maximum input-to-output voltage differential. The maxi-
mum power-dissipation capability of the transistor’s
package and mounting must exceed the actual power
dissipated in the device. The power dissipated equals
the maximum load current (ILOAD(MAX)_LR) multiplied
by the maximum input-to-output voltage differential:
where VIN(MAX)_LR is the maximum input voltage of the
linear regulator, and VOUT_LR is the output voltage of
the linear regulator.
Stability Requirements
The MAX8795A linear-regulator controllers use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, the
pass transistor, the base-emitter resistor, and the out-
put capacitor determine the loop stability. The following
applies to both linear-regulator controllers in the
MAX8795A.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
where VTis 26mV at room temperature, and IBIAS is the
current through the base-to-emitter resistor (RBE). For
the MAX8795A, the bias currents for both the gate-on
AV
Ih
IV
VLR T
BIAS FE
LOAD LR REF__
≅⎛
⎝
⎜⎞
⎠
⎟×+ ×
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥×
10 1
PI V V
LOAD MAX LR IN MAX LR OUT LR
=×−
()_ ()_ _
()
II
V
Rh
LOAD MAX DRV BE
BE FE MIN() ()
=−
⎛
⎝
⎜⎞
⎠
⎟×
RR VV
VV
FBN GOFF
REF FBN
78=× −
−
RR V
V
GON
FBP
45 1=× −
⎛
⎝
⎜⎞
⎠
⎟
CI
fV
OUT CP LOAD CP
OSC RIPPLE CP
__
_
≥2
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
24 ______________________________________________________________________________________
and gate-off linear-regulator controllers are 0.1mA.
Therefore, the base-to-emitter resistor for both linear
regulators should be chosen to set 0.1mA bias current:
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system, and the output capaci-
tor’s ESR generates a zero. For proper operation, use
the following equations to verify the linear regulator is
properly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
The unity-gain crossover of the linear regulator is:
fCROSSOVER = AV_LR fPOLE_LR
2) The pole created by the internal amplifier delay is
approximately 1MHz:
fPOLE_AMP = 1MHz
3) Next, calculate the pole set by the transistor’s input
capacitance, the transistor’s input resistance, and
the base-to-emitter pullup resistor:
gmis the transconductance of the pass transistor, and fT
is the transition frequency. Both parameters can be found
in the transistor’s data sheet. Because RBE is much
greater than RIN, the above equation can be simplified:
Substituting for CIN and RIN yields:
4) Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FB_ and AGND (including stray capacitance):
where CFB is the capacitance between FB_ and
AGND, RUPPER is the upper resistor of the linear regu-
lator’s feedback divider, and RLOWER is the lower resis-
tor of the divider.
5) Next, calculate the zero caused by the output
capacitor’s ESR:
where RESR is the equivalent series resistance of
COUT_LR.
To ensure stability, choose COUT_LR large enough so
the crossover occurs well before the poles and zero
calculated in steps 2 to 5. The poles in steps 3 and 4
generally occur at several megahertz, and using
ceramic capacitors ensures the ESR zero occurs at
several megahertz as well. Placing the crossover below
500kHz is sufficient to avoid the amplifier-delay pole
and generally works well, unless unusual component
choices or extra capacitances move one of the other
poles or the zero below 1MHz.
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PCB copper area,
other thermal mass, and airflow.
The MAX8795A, with its exposed backside paddle sol-
dered to 1in2of PCB copper and a large internal ground
plane layer, can dissipate approximately 2.76W into
+70°C still air. More PCB copper, cooler ambient air,
and more airflow increase the possible dissipation, while
less copper or warmer air decreases the IC’s dissipation
capability. The major components of power dissipation
are the power dissipated in the step-up regulator and
the power dissipated by the operational amplifiers.
fCR
POLE ESR OUT LR ESR
__
=××
1
2π
fCR R
POLE FB FB UPPER LOWER
_(|| )
=××
1
2π
ff
h
POLE IN T
FE
_=
fCR
POLE IN IN IN
_=××
1
2π
:where
Cg
f
IN m
=2πTIN FE
m
Rh
g
,=
fCRR
POLE IN IN BE IN
_(||)
=××
1
2π
fI
CV
POLE LR LOAD MAX LR
OUT LR OUT LR
_()_
__
=××2π
RV
mA
V
mA k
BE BE
==≈
01
07
01 68
.
.
..Ω
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 25
Step-Up Regulator
The largest portions of power dissipation in the step-up
regulator are the internal MOSFET, the inductor, and the
output diode. If the step-up regulator has 90% efficiency,
approximately 3% to 5% of the power is lost in the internal
MOSFET, approximately 3% to 4% in the inductor, and
approximately 1% in the output diode. The remaining 1%
to 3% is distributed among the input and output capacitors
and the PCB traces. If the input power is about 5W, the
power lost in the internal MOSFET is approximately 150mW
to 250mW.
Operational Amplifier
The power dissipated in the operational amplifiers
depends on their output current, the output voltage,
and the supply voltage:
where IOUT_(SOURCE) is the output current sourced by
the operational amplifier, and IOUT_(SINK) is the output
current that the operational amplifier sinks.
In a typical case where the supply voltage is 13V and
the output voltage is 6V with an output source current
of 30mA, the power dissipated is 180mW.
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of high-current loops by placing
the inductor, the output diode, and the output
capacitors near the input capacitors and near the
LX and PGND pins. The high-current input loop
goes from the positive terminal of the input capacitor
to the inductor, to the IC’s LX pin, out of PGND, and
to the input capacitor’s negative terminal. The high-
current output loop is from the positive terminal of
the input capacitor to the inductor, to the output
diode (D1), and to the positive terminal of the output
capacitors, reconnecting between the output capac-
itor and input capacitor ground terminals. Connect
these loop components with short, wide connec-
tions. Avoid using vias in the high-current paths. If
vias are unavoidable, use many vias in parallel to
reduce resistance and inductance.
• Create a power-ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all of
these together with short, wide traces or a small
ground plane. Maximizing the width of the power-
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes. Create an
analog ground plane (AGND) consisting of the
AGND pin, all the feedback-divider ground connec-
tions, the operational-amplifier divider ground con-
nections, the COMP and DEL capacitor ground
connections, and the device’s exposed backside
paddle. Connect the AGND and PGND islands by
connecting the PGND pin directly to the exposed
backside paddle. Make no other connections
between these separate ground planes.
• Place all feedback voltage-divider resistors within
5mm of their respective feedback pins. The divider’s
center trace should be kept short. Placing the resis-
tors far away causes their FB traces to become
antennas that can pick up switching noise. Take
care to avoid running any feedback trace near LX or
the switching nodes in the charge pumps, or pro-
vide a ground shield.
• Place the IN pin and REF pin bypass capacitors as
close as possible to the device. The ground connec-
tion of the IN bypass capacitor should be connected
directly to the AGND pin with a wide trace.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
• Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes (FB, FBP, and FBN) and analog ground.
Use DC traces to shield if necessary.
Refer to the MAX8795A evaluation kit for an example of
proper PCB layout.
PD I V V
PD I V
SOURCE OUT SOURCE SUP OUT
SINK OUT SINK OUT
=×−
=×
_( ) _
_( ) _
()
Chip Information
TRANSISTOR COUNT: 6595
PROCESS: BiCMOS
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
26 ______________________________________________________________________________________
Pin Configurations
32COM
MAX8795A
THIN QFN
5mm x 5mm
28DRVN
27FBN
26DRVP
25FBP
29DEL
30CTL
31DRN
20
OUT5
19
NEG5
18
POS5
17
OUT4
21
LX
22
IN
23
FB
24
COMP
12 POS3
11 BGND
10 POS2
9 NEG2
13 OUT3
14 SUP
15 POS4
16 NEG4
5
OUT1
6
NEG1
7
POS1
8
OUT2
4
PGND
3
AGND
2
REF
1
SRC
TOP VIEW
MAX8795A
LQFP
7mm x 7mm
+
TOP VIEW
29
30
28
27
12
11
13
REF
PGND
OUT1
NEG1
POS1
14
SRC
FB
LX
OUT5
COMP
NEG5
POS5
12
DRVN
4567
2324 22 20 19 18
DEL
CTL
SUP
OUT3
POS3
BGND
AGND IN
3
21
31 10
DRN POS2
32 9
COMNEG2
FBN
26 15 POS4
DRVP
25 16 NEG4
OUT2 OUT4
8
17
FBP
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 27
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
32 TQFN T3255+3 21-0140 90-0025
32 LQFP C32+2 21-0054 90-0111
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
28 ______________________________________________________________________________________
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
______________________________________________________________________________________ 29
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
30 ______________________________________________________________________________________
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX8795A
TFT-LCD DC-DC Converter with
Operational Amplifiers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
31
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/07 Initial release 0
1 6/07 Added LQFP package and G temperature grade versions 1, 2, 6–30
2 12/10 Added TQFN version 1–10, 27–30
3 3/11 Added automotive-qualified part 1
4 6/11 Corrected automotive /V temperature range 1
5 5/12 Added automotive-qualified part 1
