© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 9
1Publication Order Number:
MC1488/D
MC1488
Quad Line EIA-232D Driver
The MC1488 is a monolithic quad line driver designed to interface
data terminal equipment with data communications equipment in
conformance with the specifications of EIA Standard No. EIA−232D.
Features
•Current Limited Output
±10 mA typical
•Power−Off Source Impedance
300 W minimum
•Simple Slew Rate Control with External Capacitor
•Flexible Operating Supply Range
•Compatible with All ON Semiconductor DTL and TTL Logic
Families
•Pb−Free Packages are Available
Figure 1. Simplified Application
DTL Logic Output
Interconnecting
Cable
Interconnecting
Cable
DTL Logic Input
Line Receiver
MC1489
Line Driver
MC1488
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PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
1
14 SOEIAJ−14
M SUFFIX
CASE 965
1
14
1
14
1
PIN CONNECTIONS
2
Output C
Input C2
Input C1
Output D
Input D2
VCC
14
Input D1
VEE
Input A
Output A
Input B1
Input B2
Gnd
Output B
8
9
10
11
12
13
7
5
3
4
1
6
See general marking information in the device marking
section on page 8 of this data sheet.
DEVICE MARKING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
MC1488
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2
Figure 2. Circuit Schematic
(1/4 of Circuit Shown)
GND 7
3.6 k
Pins 4, 9, 12 or 2
Input
Pins 5, 10, 13
Input
8.2 k
VCC 14
7.0 k 70
6.2 k
70
Output
300
10 k
VEE 1
Pins 6, 8, 11 or 3
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MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating Symbol Value Unit
Power Supply Voltage VCC
VEE
+ 15
− 15
Vdc
Input Voltage Range VIR − 15 p VIR p
7.0
Vdc
Output Signal Voltage VO±15 Vdc
Power Derating (Package Limitation, SO−14 and Plastic Dual−In−Line Package)
Derate above TA = + 25°C
PD
1/RqJA
1000
6.7
mW
mW/°C
Operating Ambient Temperature Range TA0 to + 75 °C
Storage Temperature Range Tstg − 65 to + 175 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (VCC = + 9.0 ± 1% Vdc, VEE = −9.0 ± 1% Vdc, TA = 0 to 75°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Input Current − Low Logic State (VIL = 0) IIL −1.0 1.6 mA
Input Current − High Logic State (VIH = 5.0 V) IIH − − 10 mA
Output Voltage − High Logic State
(VIL = 0.8 Vdc, RL = 3.0 kW, VCC = + 9.0 Vdc, VEE = − 9.0 Vdc)
(VIL = 0.8 Vdc, RL = 3.0 kW, VCC = + 13.2 Vdc, VEE = − 13.2 Vdc)
VOH
+ 6.0
+ 9.0
+7.0
+10.5
−
−
Vdc
Output Voltage − Low Logic State
(VIH = 1.9 Vdc, RL = 3.0 kW, VCC = + 9.0 Vdc, VEE = − 9.0 Vdc)
(VIH = 1.9 Vdc, RL = 3.0 kW, VCC = + 13.2 Vdc, VEE = − 13.2 Vdc)
VOL
− 6.0
− 9.0
− 7.0
− 10.5
−
−
Vdc
Positive Output Short−Circuit Current, Note 1 IOS++ 6.0 + 10 + 12 mA
Negative Output Short−Circuit Current, Note 1 IOS−− 6.0 − 10 − 12 mA
Output Resistance (VCC = VEE = 0, ⎥VO⎜ = ± 2.0 V) ro300 − − Ohms
Positive Supply Current (RI = ∞)
(VIH = 1.9 Vdc, VCC = + 9.0 Vdc)
(VIL = 0.8 Vdc, VCC = + 9.0 Vdc)
(VIH = 1.9 Vdc, VCC = + 12 Vdc)
(VIL = 0.8 Vdc, VCC = + 12 Vdc)
(VIH = 1.9 Vdc, VCC = + 15 Vdc)
(VIL = 0.8 Vdc, VCC = + 15 Vdc)
ICC
−
−
−
−
−
−
+ 15
+ 4.5
+ 19
+ 5.5
−
−
+ 20
+ 6.0
+ 25
+ 7.0
+ 34
+ 12
mA
Negative Supply Current (RL = ∞)
(VIH = 1.9 Vdc, VEE = − 9.0 Vdc)
(VIL = 0.8 Vdc, VEE = − 9.0 Vdc)
(VIH = 1.9 Vdc, VEE = − 12 Vdc)
(VIL = 0.8 Vdc, VEE = − 12 Vdc)
(VIH = 1.9 Vdc, VEE = − 15 Vdc)
(VIL = 0.8 Vdc, VEE = − 15 Vdc)
IEE
−
−
−
−
−
−
− 13
−
− 18
−
−
−
− 17
− 500
− 23
− 500
− 34
− 2.5
mA
mA
mA
mA
mA
mA
Power Consumption
(VCC = 9.0 Vdc, VEE = − 9.0 Vdc)
(VCC = 12 Vdc, VEE = − 12 Vdc)
PC
−
−
−
−
333
576
mW
SWITCHING CHARACTERISTICS (VCC = +9.0 ± 1% Vdc, VEE = −9.0 ± 1% Vdc, TA = +25°C.)
Propagation Delay Time (zI = 3.0 k and 15 pF) tPLH −275 350 ns
Fall Time (zI = 3.0 k and 15 pF) tTHL −45 75 ns
Propagation Delay Time (zI = 3.0 k and 15 pF) tPHL −110 175 ns
Rise Time (zI = 3.0 k and 15 pF) tTLH −55 100 ns
1. Maximum Package Power Dissipation may be exceeded if all outputs are shorted simultaneously.
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CHARACTERISTIC DEFINITIONS
10
13
9
4
12
5
1
2
14
9.0 V
5.0 V
IIH
IIL
-9.0 V
7
1.9 V
7
VOL
9.0 V
VOH
0.8 V
VOL
3.0 k
VOH
14 1
-9.0 V
2
4
9
12
3
6
8
11
9
2
14
4
5
IOS+
1
11
6
8
13
9
4
12
3
1
±6.6 mA Max
3
7
8
6
11
0.8 V
2
1.9 V 14
VEE
VCC
7
10
12
IOS±
VO
±2.0 Vdc
IOS-
tTHL and tTLH Measured 10% to 90%
VO
15 pF3.0 k
50%
tPHL
tPLH
tTLH
tTHL
ein
0 V
3.0 V
1.5 V
ein
VO
ICC
VIL
2
VCC
1
14
7
12
4
9
IEE
VEE
1.9 V
VIH
0.8 V
Figure 3. Input Voltage Figure 4. Output Current
Figure 5. Output Short−Circuit Current Figure 6. Output Resistance (Power Off)
Figure 7. Power Supply Currents Figure 8. Switching Response
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TYPICAL CHARACTERISTICS
(TA = +25°C, unless otherwise noted.)
2.01.81.61.41.20.40.2 0.6 0.8 1.0
-9.0
-3.0
0
3.0
6.0
-12
9.0
12
-6.0
0
VCC = VEE = ± 12 V
Vin, INPUT VOLTAGE (V)
V , OUTPUT VOLTAGE (V)
O
VCC = VEE = ± 9.0 V
VCC = VEE = ± 6.0 V
Figure 9. Transfer Characteristics
versus Power Supply Voltage
VIVO
3.0 k
IOS-
12
9.0
6.0
3.0
0
-3.0
-6.0
-9.0
-12
125
IOS+
75-55 0 25
T, TEMPERATURE (°C)
I , SHORT CIRCUIT OUTPUT CURRENT (mA)
SC
Figure 10. Short Circuit Output Current
versus Temperature
VEE = 9.0 V
0.8 V
VI
1.9 V VCC = 9.0 V
1000
1.0 100 10,0001,000
CL, CAPACITANCE (pF)
10
10
100
1.0
SLEW RATE (V/s)μ
Figure 11. Output Slew Rate
versus Load Capacitance
VIVO
CL
12
0
-4.0
-8.0
-12
-16
-20
4.0
8.0
16-16 -12 -8.0 12-4.0 4.0
16
8.0
20
0
3.0 kW LOAD LINE
VO, OUTPUT VOLTAGE (V)
I , OUTPUT CURRENT (mA)
O
VO
IOS
1.9 V
VCC = VEE = ± 9.0V
0.8 V
VI
+
-
Figure 12. Output Voltage and
Current−Limiting Characteristics
25
4.0
6.0
8.0
10
12
14
-55 12575
2.0
0
16
T, TEMPERATURE (°C)
V , V , POWER SUPPLY VOLTAGE (V)
CC EE
0
VEE
1
3.0 k
3.0 k
3.0 k
3.0 k
14
VCC
8
6
3
11
7
Figure 13. Maximum Operating Temperature
versus Power Supply Voltage
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APPLICATIONS INFORMATION
The Electronic Industries Association EIA−232D
specification details the requirements for the interface
between data processing equipment and data
communications equipment. This standard specifies not
only the number and type of interface leads, but also the
voltage levels to be used. The MC1488 quad driver and its
companion circuit, the MC1489 quad receiver, provide a
complete interface system between DTL or TTL logic levels
and the EIA−232D defined levels. The EIA−232D
requirements as applied to drivers are discussed herein.
The required driver voltages are defined as between
5.0 and 15 V in magnitude and are positive for a Logic “0”
and negative for a Logic “1.” These voltages are so defined
when the drivers are terminated with a 3000 to 7000 W
resistor. The MC1488 meets this voltage requirement by
converting a DTL/TTL logic level into EIA−232D levels
with one stage of inversion.
The EIA−232D specification further requires that
during transitions, the driver output slew rate must not
exceed 30 V per microsecond. The inherent slew rate of the
MC1488 is much too fast for this requirement. The current
limited output of the device can be used to control this slew
rate by connecting a capacitor to each driver output. The
required capacitor can be easily determined by using the
relationship C = IOS x DT/DV from which Figure 14 is
derived. Accordingly, a 330 pF capacitor on each output
will guarantee a worst case slew rate of 30 V per
microsecond.
1000
10
100
1.0
10
333 pF
30 V/ms
Figure 14. Slew Rate versus Capacitance
for ISC = 10 mA
C, CAPACITANCE (pF)
10,000100 1,0001.0
SLEW RATE (V/s)μ
The interface driver is also required to withstand an
accidental short to any other conductor in an
interconnecting cable. The worst possible signal on any
conductor would be another driver using a plus or minus
15 V, 500 mA source. The MC1488 is designed to
indefinitely withstand such a short to all four outputs in a
package as long as the power supply voltages are greater
than 9.0 V (i.e., VCC q 9.0 V; VEE p − 9.0 V). In some
power supply designs, a loss of system power causes a low
impedance on the power supply outputs. When this occurs,
a low impedance to ground would exist at the power inputs
to the MC1488 effectively shorting the 300 W output
resistors to ground. If all four outputs were then shorted to
plus or minus 15 V, the power dissipation in these resistors
would be excessive. Therefore, if the system is designed to
permit low impedances to ground at the power supplies of
the drivers, a diode should be placed in each power supply
lead to prevent overheating in this fault condition. These two
diodes, as shown in Figure 15, could be used to decouple all
the driver packages in a system. (These same diodes will
allow the MC1488 to withstand momentary shorts to the
±25 V limits specified in the earlier Standard EIA−232B.)
The addition of the diodes also permits the MC1488 to
withstand faults with power supplies of less than the 9.0 V
stated above.
Figure 15. Power Supply Protection
to Meet Power Off Fault Conditions
VCC 14
MC1488
VEE
7
MC1488
14
MC1488
14
71 171
The maximum short circuit current allowable under
fault conditions is more than guaranteed by the previously
mentioned 10 mA output current limiting.
Other Applications
The MC1488 is an extremely versatile line driver with
a myriad of possible applications. Several features of the
drivers enhance this versatility:
1. Output Current Limiting − this enables the circuit
designer to define the output voltage levels independent of
power supplies and can be accomplished by diode
clamping of the output pins. Figure 16 shows the MC1488
used as a DTL to MOS translator where the high level
voltage output is clamped one diode above ground. The
resistor divider shown is used to reduce the output voltage
below the 300 mV above ground MOS input level limit.
MC1488
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2. Power Supply Range − as can be seen from the
schematic drawing of the drivers, the positive and negative
driving elements of the device are essentially independent
and do not require matching power supplies. In fact, the
positive supply can vary from a minimum 7.0 V (required for
driving the negative pulldown section) to the maximum
specified 15 V. The negative supply can vary from
approximately − 2.5 V to the minimum specified − 15 V. The
MC1488 will drive the output to within 2.0 V of the positive
or negative supplies as long as the current output limits are not
exceeded. The combination of the current limiting and supply
voltage features allow a wide combination of possible outputs
within the same quad package. Thus if only a portion of the
four drivers are used for driving EIA−232D lines, the
remainder could be used for DTL to MOS or even DTL to
DTL translation. Figure 17 shows one such combination.
Figure 16. DTL/TTL−to−MOS Translator
Figure 17. Logic Translator Applications
MOS Output
(with VSS = GND)
10 k
1.0 k
DTL
TTL
Input
1/4 MC1488
12 V
-12 V-12 V
MOS Output
-10 V to 0 V
DTL Output
-0.7 V to +5.7 V
HTL Output
-0.7 V to 10 V
RTL Output
-0.7 V to +3.7 V
-12 V
10 k
1.0 k
5.0 V
8
1
11
63.0 V
3
MC1488
13
12
10
9
5
4
DTL
MMOS
Input
DTL
HTL
Input
2
DTL
NAND
Gate
Input
DTL
Input
12 V
147
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ORDERING INFORMATION
Device Package Operating Temperature Range Shipping
MC1488D SOIC−14
TA = 0 to +75°C
55 Units/Rail
MC1488DG SOIC−14
(Pb−Free)
MC1488DR2 SOIC−14
2500/Tape & Reel
MC1488DR2G SOIC−14
(Pb−Free)
MC1488P PDIP−14
25 Units/Rail
MC1488PG PDIP−14
(Pb−Free)
MC1488M SOEIAJ−14
50 Units/Rail
MC1488MG SOEIAJ−14
(Pb−Free)
MC1488MEL SOEIAJ−14
2000/Tape & Reel
MC1488MELG SOEIAJ−14
(Pb−Free)
MARKING DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
1
14
MC1488P
AWLYYWWG
1
14
MC1488G
AWLYWW
1
14
MC1488DG
AWLYWW
SOEIAJ−14
M SUFFIX
CASE 965
MC1488
ALYWG
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PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG D
K
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J
0.290 0.310 7.37 7.87
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PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.004 0.008
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC1488/D
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