ACML-7400, ACML-7410 and ACML-7420
3.3 V/5 V 100 MBd High Speed CMOS Digital Isolator
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Description
ACML-7400, ACML-7410 and ACML-7420 are multi-channel
high speed CMOS digital isolators. Using magnetic
coupling through a thick insulation barrier, the isolators
enable high speed transmissions without compromise
in isolation performance. These isolators consume low
power even at high data rates, yet provide excellent
transient immunity performance in compact surface
mount packages. The devices are quali ed to a maximum
propagation delay of 36 ns and a maximum pulse width
distortion of 3 ns. They are capable of running at a 100
MBaud data rate
ACML-7400, ACML-7410 and ACML-7420 are available in
16-pin SOIC wide-body packages. They operate at dual
3.3 V/5 V supply voltages. The DC and timing speci ca-
tions are speci ed over the temperature range of -40° C
to +105° C. ACML-7400, ACML-7410 and ACML-7420 are
built using CMOS input bu ers and CMOS output drivers
to eliminate the need for both input limiters and output
pull-up resistors. Refresh circuitry is built in to ensure
DC-correctness.
Applications
Isolated data interfaces
Data acquisition
Digital oscilloscopes
Power meters
High speed video transmission
Features
Dual supply voltage compatible – 3.3 V & 5 V
Wide operating temperature range (-40° C to +105° C)
Support high speed data rate of at least 100 MBd
Lower power consumption – 15 mA per channel typical
Low propagation delay: 36 ns max
Low propagation delay skew
– Channel-to-channel: 4 ns max
– Part-to-part: 8 ns max
Low pulse width distortion: 3 ns max
Safety and Regulatory Approvals
UL Recognised
– 5600 VRMS for 1 min. per UL1577
– CSA Component Acceptance Notice #5
IEC 60950-1
– Basic Insulation, 800 VRMS max. working voltage
– Reinforced Insulation, 400 VRMS max. working
voltage
IEC 61010-1
– Basic Insulation, 800 VRMS max. working voltage
– Reinforced Insulation, 400 VRMS max. working voltage
IEC 60601-1
– 2 Means of Patient Protection, 250 VRMS max.
working voltage
– 2 Means of Operator Protectioin, 400 VRMS max.
working voltage
High Common Mode Transient Immunity – 25 kV/s min
CMOS bu er input and output
DC correctness
Lead-free
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
2
Device Selection Guide
Device Number Channel Con guration Package
ACML-7400 Quad, All-in-One 16-pin Small Outline, Wide Body
ACML-7410 Quad, Bi-directional, 3/1 16-pin Small Outline, Wide Body
ACML-7420 Quad, Bi-directional, 2/2 16-pin Small Outline, Wide Body
Ordering Information
ACML-7400, ACML-7410 and ACML-7420 are UL Recognized with 5600 VRMS for 1 minute per UL1577.
Part number
Option
Package Surface Mount Tape & Reel
UL 5600 VRMS /
1 Minute rating QuantityRoHS Compliant
ACML-7400
ACML-7410
ACML-7420
-000E Wide Body SO-16 X X45 per tube
-500E X X X850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACML-7420-500E to order product of Wide Body SO-16 package in Tape and Reel in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Functional Diagram
Quad Channel
ACML-7400
1
2
3
4
16
15
14
13
VDD2
Galvanic Isolation
5
6
7
8
12
11
10
9
GND2
VO1
VO2
VO3
VO4
VOE2
GND2
VDD1
GND1
VIN1
VIN2
VIN3
VIN4
NC
GND1
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
ACML-7410
VDD2
GND2
VO1
VO2
VO3
VIN4
VOE2
VOE1
GND2
VDD1
GND1
VIN1
VIN2
VIN3
VO4
GND1
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
VDD2
GND2
VO1
VO2
VIN3
VIN4
VOE2
VOE1
GND2
VDD1
GND1
VIN1
VIN2
VO3
VO4
GND1
ACML-7420
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
Pin Description
Pin Description
VDD1, VDD2 Power supply at primary and secondary side
GND1, GND2Ground at primary and secondary side
VIN1, VIN2, VIN3, VIN4 Input for channel 1, 2, 3 and 4
VO1, VO2, VO3, VO4 Output for channel 1, 2, 3 and 4
VOE1, VOE2 Output enable at VDD1 and VDD2 side, these pins should be connected to the respective VDD when
not in use.
NC No connectivity
Truth Table (ACML-7410)
VDD1 VIN1,IN2,IN3 VOE1 VO4 VDD2 VIN4 VOE2 VO1, O2, O3 Remark
HH XXHXH or
NC
H Input (VIN1, IN2, IN3) logic High during normal operation.
The default state for VOE2 is High state.
HL XXHXH or
NC
L Input (VIN1, IN2, IN3) logic Low during normal operation.
The default state for VOE2 is High state.
H X X X H X L Z Output (VO1, O2, O3) is disabled to high impedance state
when VOE2 is set to Low.
L X X X H X H H When VDD1 is not powered, the output (VO1, O2, O3)
default state is High. Output (VO1, O2, O3) typically
restored 100 s after VDD1 is restored.
H X H or
NC
HHHXX Input (VIN4) logic High during normal operation.
The default state for VOE1 is High state.
H X H or
NC
L H L X X Input (VIN4) logic Low during normal operation.
The default state for VOE1 is High state.
H X L Z H X X X Output (VO4) is disabled to high impedance state when
VOE1 is set to Low.
H X H H L X X X When VDD2 is not powered, the output (VO4) default
state is High. Output (VO4) typically restored 100 s
after VDD2 is restored.
X means don’t care
NC means not connection.
4
Package Outline Drawings
ACML-7400, ACML-7410 and ACML-7420 16-Lead Surface Mount (SOIC-16) Package
Recommended Pb-Free IR Pro le
Recommended re ow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACML-7400, ACML-7410 and ACML-7420 are approved by the following organizations:
UL
UL1577, component recognition program.
CSA Component Acceptance Service Notice #5A.
9
7.493 ± 0.254
(0.295 ± 0.010)
10111213141516
87654321
0.457
(0.018)
3.505 ± 0.127
(0.138 ± 0.005)
9°
10.312 ± 0.254
(0.406 ± 0.10)
10.160 ± 0.254
(0.408 ± 0.010)
0.025 MIN.
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
8.986 ± 0.254
(0.345 ± 0.010)
0-8°
0.457
(0.018) 1.270
(0.050)
ALL LEADS
TO BE
COPLANAR
± 0.002
A 7400
YYWW
TYPE NUMBER
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
11.63 (0.458)
2.16 (0.085)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
TUV Rheinland
Insulation
Category
IEC 60950-1 IEC 61010-1 IEC 60601-1
Reinforced Basic Reinforced Basic
2 Means of
Patient Protection
2 Means of
Operator Protection
Working Voltage 400 VRMS
(567 VPEAK)
800 VRMS
(1132 VPEAK)
400 VRMS
(567 VPEAK)
800 VRMS
(1132 VPEAK)
250 VRMS
(354 VPEAK)
400 VRMS
(567 VPEAK)
5
Insulation and Safety Related Speci cations
Parameter Symbol
ACML-7400
ACML-7410
ACML-7420 Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 8.1 mm Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102) 8.1 mm Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.05 mm Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
All creepage and clearance pertain to the isolation component itself. These dimensions are needed as a starting point
for the designer when determining the circuit insulation requirements, and not re ective of the equipment standard
requirements.
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS-55 +125 °C
Ambient Operating Temperature TA-40 +125 °C
Supply Voltages VDD1, VDD2 0 6.5 Volts
Input Voltage VI-0.5 VDD +0.5 Volts
Output Voltage VO-0.5 VDD +0.5 Volts
Average Output Current IO±15 mA
Electrostatic Discharge Human Body Model HBM ±4 kV
Charge Device Model CDM ±1 kV
Solder Re ow Temperature Pro le Please refer to Solder Re ow Temperature Pro le
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Notes
Ambient Operating Temperature TA-40 +105 °C
Supply Voltages ( 3.3 V operation) VDD1, VDD2 3.0 3.6 V
Supply Voltages ( 5 V operation) VDD1, VDD2 4.5 5.5 V
Logic High Input Voltage VIH 0.7 x VDD VDD V
Logic Low Input Voltage VIL 0.0 0.3 x VDD V
6
Electrical Speci cations
The following speci cations apply to ACML-7400 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C,
input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2 ≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V.
All typical speci cations at TA = +25° C.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes
Input Supply Current,
No data
IDD1(0) 5.9* 10 mA No Input 1,7 1
6.8** VDD1 = 5.5 V
Input Supply Current,
25 MBd data rate
IDD1(25) 16 mA VDD1 = 3.3 V 12.5 MHz logic
signal
1,7 2
17 VDD1 = 5.0 V
Input Supply Current,
100 MBd data rate
IDD1(100) 30* 40 mA VDD1 = 3.6 V 50 MHz logic
signal
1,7 2
31** 40 VDD1 = 5.5 V
Output Supply Current,
No data
IDD2(0) 12* 16 mA No Input 2,8 3
13** VDD1 = 5.5 V
Output Supply Current,
25 MBd
IDD2(25) 15 mA VDD1 = 3.3 V 12.5 MHz logic
signal
2,8 4
17 VDD1 = 5.0 V
Output Supply Current,
100 MBd data rate
IDD2(100) 23* 32 mA VDD1 = 3.6 V 50 MHz logic
signal
2,8 4
30** 40 VDD1 = 5.5 V
Logic Input Current IIN -10 10 A
Logic High Output
Voltage
VOH VDD-0.1 VDD-0.02 V IOUT = -20 A, VIN = VDD1
0.8*VDD VDD-0.25 V IOUT = -4 mA, VIN = VDD1
Logic Low Output
Voltage
VOL 0.02 0.1 V IOUT = 20 A, VIN = 0 V
0.25 0.8 V IOUT = 4 mA, VIN = 0 V
* Typical data based on 3.3 V supply, ** Typical data based on 5.0 V supply
The following speci cations apply to ACML-7410 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C,
input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2 ≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V.
All typical speci cations at TA = +25° C.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes
Input Supply Current,
No data
IDD1(0) 8.4* 11.5 mA No Input 3,7 1
9.4** VDD1 = 5.5 V
Input Supply Current,
25 MBd data rate
IDD1(25) 15.5* mA VDD1 = 3.3 V 12.5 MHz logic
signal
3,7 2
17** VDD1 = 5.0 V
Input Supply Current,
100 MBd data rate
IDD1(100) 28.5* 38 mA VDD1 = 3.6 V 50 MHz logic
signal
3,7 2
30.5** 40 VDD1 = 5.5 V
Output Supply Current,
No data
IDD2(0) 9.5* 14.5 mA No Input 4,8 3
10.4** VDD1 = 5.5 V
Output Supply Current,
25 MBd
IDD2(25) 15* mA VDD1 = 3.3 V 12.5 MHz logic
signal
4,8 4
17** VDD1 = 5.0 V
Output Supply Current,
100 MBd data rate
IDD2(100) 25* 34 mA VDD1 = 3.6 V 50 MHz logic
signal
4,8 4
30** 40 VDD1 = 5.5 V
Logic Input Current IIN -10 10 A
Logic High Output
Voltage
VOH VDD-0.1 VDD-0.02 V IOUT = -20 A, VIN = VDD1
0.8*VDD VDD-0.25 V IOUT = -4 mA, VIN = VDD1
Logic Low Output
Voltage
VOL 0.02 0.1 V IOUT = 20 A, VIN = 0 V
0.25 0.8 V IOUT = 4 mA, VIN = 0 V
* Typical data based on 3.3 V supply, ** Typical data based on 5.0 V supply
7
The following speci cations apply to ACML-7420 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C,
input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2 ≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V.
All typical speci cations at TA = +25° C.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes
Input Supply Current,
No data
IDD1(0) 9.0* 13 mA No Input 5,7 1
9.9** VDD1 = 5.5 V
Input Supply Current,
25 MBd data rate
IDD1(25) 15* mA VDD1 = 3.3 V 12.5 MHz logic
signal
5,7 2
17** VDD1 = 5.0 V
Input Supply Current,
100 MBd data rate
IDD1(100) 27* 36 mA VDD1 = 3.6 V 50 MHz logic
signal
5,7 2
30** 40 VDD1 = 5.5 V
Output Supply Current,
No data
IDD2(0) 9.0* 13 mA No Input 6,8 3
9.9** VDD1 = 5.5 V
Output Supply Current,
25 MBd
IDD2(25) 15* mA VDD1 = 3.3 V 12.5 MHz logic
signal
6,8 4
17** VDD1 = 5.0 V
Output Supply Current,
100 MBd data rate
IDD2(100) 27* 36 mA VDD1 = 3.6 V 50 MHz logic
signal
6,8 4
30** 40 VDD1 = 5.5 V
Logic Input Current IIN -10 10 A
Logic High Output
Voltage
VOH VDD-0.1 VDD-0.02 V IOUT = -20 A, VIN = VDD1
0.8*VDD VDD-0.25 V IOUT = -4 mA, VIN = VDD1
Logic Low Output
Voltage
VOL 0.02 0.1 V IOUT = 20 A, VIN = 0 V
0.25 0.8 V IOUT = 4 mA, VIN = 0 V
* Typical data based on 3.3 V supply, ** Typical data based on 5.0 V supply
8
Switching Speci cations
The following speci cations apply to ACML-7400, ACML-7410 and ACML-7420 and are applicable to ambient tempera-
ture of -40° C ≤ TA ≤ 105° C, input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2
≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V, unless further speci ed. All typical speci cations are at TA = +25° C.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes
Maximum Data Rate 100 MBd 50 MHz Logic Signal
Minimum Pulse Width 10 ns 50 MHz Logic Signal
Propogation Delay Time
to Logic Low Output
tPHL 18 27 32 ns 4.5 V ≤ VDD1 = VDD2 ≤ 5.5 V,
CL = 15 pF
95
Propogation Delay Time
to Logic High Output
tPLH 18 27 32 ns 9 5
Pulse Width Distortion PWD -2 0 2 ns 11 6
Propagation Delay
Channel Skew
tCSK 0 3 ns 12 7
Propagation Delay
Part Skew
tPSK 1 5 ns 8
Propogation Delay Time
to Logic Low Output
tPHL 20 28 36 ns CL = 15 pF 9,10 5
Propogation Delay Time
to Logic High Output
tPLH 20 27.5 36 ns 9,10 5
Pulse Width Distortion PWD -3 0.5 3 ns 11 6
Propagation Delay
Channel Skew
tCSK 0 4 ns 12 7
Propagation Delay
Part Skew
tPSK 1 8 ns 8
Output Rise Time (10% – 90%) tR3nsC
L = 15 pF
Output Fall Time (90% - 10%) tF3nsC
L = 15 pF
Output Enable time tENABLE 10 ns VIN = 0 V or VDD 9
Output Disable time tDISABLE 10 ns VIN = 0 V or VDD 10
Common Mode Transient
Immunity at Logic
High Output
| CMH | 25 >40 kV/sVCM = 1000 V, TA = 25° C,
VIN = VDD VO > 0.8 x VDD
11
Common Mode Transient
Immunity at Logic
Low Output
| CML | 25 >40 kV/sVCM = 1000 V, TA = 25° C,
VIN = 0 V, VO < 0.8 V
11
9
Package Characteristics
All Typicals at TA = 25° C.
Parameters Symbol Min. Typ. Max. Unit Test Conditions Notes
Input-Output Momentary
With-stand Voltage
VISO 5600 VRMS RH ≤ 50%, t = 1 min,
TA = 25°C
12, 13,
14
Input-Output Resistance RI-O 1014 VI-O = 500 V dc 12
Input-Output Capacitance CI-O 1.9 pF f = 1 MHz 12
Input Capacitance CI4.3 pF 15
Package Power Dissipation PPD 750 mW TA = 25° C
Notes:
1. IDD1(0) is the supply current consumption at VDD1 of ACML-7400, ACML-7410 and ACML-7420 when there is no signal to all inputs.
2. IDD1(F) is the supply current consumption at VDD1 of ACML-7400, ACML-7410 and ACML-7420 when inputs are switching at the speci ed data rate,
and outputs are switching at same data rate with no load.
3. IDD2(0) is the supply current consumption at VDD2 of ACML-7400, ACML-7410 and ACML-7420 when there is no signal to all inputs.
4. IDD2(F) is the supply current consumption at VDD2 of ACML-7400, ACML-7410 and ACML-7420 when inputs are switching at the speci ed data rate,
and outputs are switching at same data rate with no load.
5. tPHL propagation delay is measured from the 50% level on the falling edge of the VIN signal to the 50% level of the falling edge of the VOUT signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VIN signal to the 50% level of the rising edge of the VOUT signal.
6. PWD is de ned as tPHL -tPLH.
7. tCSK is equal to the magnitude of the worst case di erence in tPHL and/or tPLH that will be seen between channels of the same unit at any given
temperature and supply voltages within the recommended operating conditions.
8. tPSK is equal to the magnitude of the worst case di erence in tPHL and/or tPLH that will be seen between units at any given temperature and supply
voltages within the recommended operating conditions.
9. tENABLE is the duration when VOE is set to High state and output is restored per input signal (VO = VIN).
10. tDISABLE is the duration when VOE is set to Low and VO is switched to high impedance state.
11. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDD2. CML is the maximum common
mode input voltage that can be sustained while maintaining VOUT < 0.8 V. The common mode voltage slew rates apply to both rising and falling
common mode voltage edges.
12. Device considered a two-terminal device: pins 1, 2, 3, 4, 5, 6, 7, 8 shorted together and pins 9, 10, 11, 12, 13, 14, 15 and 16 shorted together.
13. In accordance with UL1577, each ACML-7400, ACML-7410 AND ACML-7420 device is proof tested by applying an insulation test voltage 6800 VRMS
for 1 second.
14. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refers to your equipment level safety speci cation.
15. CI is the capacitance measured at input pin.
10
Figure 1. Typical IDD1 of ACML-7400 vs Temperature Figure 2. Typical IDD2 of ACML-7400 vs Temperature
Figure 3. Typical IDD1 of ACML-7410 vs Temperature Figure 4. Typical IDD2 of ACML-7410 vs Temperature
Figure 5. Typical IDD1 of ACML-7420 vs Temperature
Characteristic Curves
Figure 6. Typical IDD2 of ACML-7420 vs Temperature
0
5
10
15
20
25
30
35
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
IDD1 - SUPPLY CURRENT - mA
IDD2 - SUPPLY CURRENT - mA
Idd1 5 V (0)
Idd1 5 V (25)
Idd1 5 V (100)
Idd1 3.3 V (0)
Idd1 3.3 V (25)
Idd1 3.3 V (100)
0
5
10
15
20
25
30
35
-40 -20 0 20 40 60 80 100
0
5
10
15
20
25
30
35
-40 -20 0 20 40 60 80 100
IDD1 - SUPPLY CURRENT - mA
Idd1 5 V (0)
Idd1 5 V (25)
Idd1 5 V (100)
Idd1 3.3 V (0)
Idd1 3.3 V (25)
Idd1 3.3 V (100)
Idd2 5 V (0)
Idd2 5 V (25)
Idd2 5 V (100)
Idd2 3.3 V (0)
Idd2 3.3 V (25)
Idd2 3.3 V (100)
0
5
10
15
20
25
30
35
-40 -20 0 20406080100
TA - TEMPERATURE - °C
IDD2 - SUPPLY CURRENT - mA
0
5
10
15
20
25
30
35
-40 -20 0 20406080100
TA - TEMPERATURE - °C
IDD1 - SUPPLY CURRENT - mA
0
5
10
15
20
25
30
35
-40 -20 0 20406080100
TA - TEMPERATURE - °C
IDD2 - SUPPLY CURRENT - mA
Idd2 5V(0)
Idd2 5V(25)
Idd2 5V(100)
Idd2 3.3V(0)
Idd2 3.3V(25)
Idd2 3.3V(100)
Idd2 5V(0)
Idd2 5V(25)
Idd2 5V(100)
Idd2 3.3V(0)
Idd2 3.3V(25)
Idd2 3.3V(100)
Idd1 5 V (0)
Idd1 5 V (25)
Idd1 5 V (100)
Idd1 3.3 V (0)
Idd1 3.3 V (25)
Idd1 3.3 V (100)
11
Figure 7. Typical Supply Current per Transmit Channel vs Data Rate Figure 8. Typical Supply Current per Receive Channel vs Data Rate
Figure 9. Typical Propagation Delay vs Temperature Figure 10. Typical Propagation Delay vs Temperature
Figure 11. Typical Pulse Width Distortion vs Temperature Figure 12. Typical Channel-Channel Delay Skew vs Temperature
0
2
4
6
8
10
0 20406080100
DATA RATE - MBd
ITX - SUPPLY CURRENT - mA
0
2
4
6
8
10
0 20 40 60 80 100
DATA RATE - MBd
IRX - SUPPLY CURRENT - mA
24
26
28
30
32
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
TP - PROPAGATION DELAY - ns
24
26
28
30
32
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
TP - PROPAGATION DELAY - ns
-0.5
-0.25
0
0.25
0.5
0.75
1
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
PWD - PULSE WIDTH DISTORTION - ns
0
0.5
1
1.5
2
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
TPSK - PROPAGATION DELAY SKEW - ns
Tpsk (5 V)
Tpsk (3.3 V)
Tpsk (5 V/3.3 V)
Tpsk (3.3 V/5 V)
Vdd (5 V)
Vdd (3.3 V)
Vdd (5 V)
Vdd (3.3 V)
Tphl (5 V)
Tplh (5 V)
Tphl (3.3 V)
Tplh (3.3 V)
Tphl (5 V/3.3 V)
Tplh (5 V/3.3 V)
Tphl (3.3 V/5 V)
Tplh (3.3 V/5 V)
PWD (5 V)
PWD (3.3 V)
PWD (5 V/3.3 V)
PWD (3.3 V/5 V)
12
Supply Current Consumption
It should be noted that the output supply current is
speci ed under no load conditions. Additional supply
current consumption from board or components loading
can be computed based on:
IDD = CVF
Where IDD is the additional supply current consumption
per output channel, C is the load capacitance, V is the
supply voltage and F is the frequency of the signal
Bypassing and PC Board Layout
The ACML-7400 series digital isolators are extremely easy
to use. No external interface circuitry is required because
ACML-7400 series use high speed CMOS IC technology
allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 13, the only external components
required for proper operation are two bypass capacitors
for decoupling the power supply. Capacitor values should
typically be 0.1 F. For each capacitor, the total lead length
between both ends of the capacitor and the power supply
pins should be as short as possible.
GND2
VOE2
GND2
VDD1 VDD2
GND1
VIN1
VIN2
VIN3
VO4
VO1
VO2
VO3
VIN4
VOE1
GND1
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
0.1 F 0.1 F
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
1
2
3
4
16
15
14
13
Galvanic Isolation
5
6
7
8
12
11
10
9
Figure 13. Typical Schematic of ACML-7410 on PC Board
Propagation Delay, Pulse-Width Distortion and
Propagation Delay Skew
Propagation Delay is a gure of merit which describes
how quickly a logic signal propagates through a system.
The propagation delay from a low to high (tPLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(tPHL) is the amount of time required for the input signal
to propagate to the output, causing the output to change
from high to low. Please see Figure 14.
Figure 14. Threshold Levels of AC Parameters
tPLH tPHL
50%
VOL
VOH
50%
VDD
0 V
VIN
INPUT
OUTPUT
VOUT
90%90%
10%10%
Figure 15. Illustration of TPSK
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2675EN - May 16, 2011
Pulse-width distortion (PWD) is the di erence between
tPHL and tPLH and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse
width is tolerable. The PWD speci cation for ACML-7400
series is 3 ns maximum across recommended operating
conditions.
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is sent through a group of isolators, dif-
ferences in propagation delays will cause the data to
arrive at the outputs of the isolators at di erent times. If
this di erence in propagation delay is large enough it will
determine the maximum rate at which parallel data can
be sent through the isolators.
Propagation delay skew is de ned as the di erence
between the minimum and maximum propagation
delays, either tPLH or tPHL for any given group of optocou-
plers which are operating under the same conditions (i.e.,
the same drive current, supply voltage, output load, and
operating temperature). As illustrated in Figure 15, if the
inputs of a group of isolators are switched either ON or
OFF at the same time, tPSK is the di erence between the
shortest propagation delay, either tPLH or tPHL and the
longest propagation delay, either tPLH and tPHL.
The ACML-7400 series isolators o er the advantage of
guaranteed speci cations for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
tPSK
50%
50%
VDD2
50% VDD2
50%
VIN
VOUT
VIN
VOUT
