74HC/HCT74 flip-flops DUAL D-TYPE FLIP-FLOP WITH SET AND RESET; POSITIVE-EDGE TRIGGER FEATURES @ Output capability: standard Icc category: flip-flops GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL {LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive- edge triggered, D-type flip-flops with individual data {D) inputs, clock (CP) inputs, set (Sp) and reset (Rp) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the @ output on the LOW- to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the ciock input makes the circuit highly tolerant to slower clock rise and fall times. | TYPICAL SYMBOL | PARAMETER CONDITIONS UNIT | He | HCT | | propagation delay | tpHt/ | nCP to nQ, nO 14 15 fons teLH np to nQ, nQ Cy = 15 pF | 15; 18 ns | Rp tond, nd Veco =8V 18 | 18 | as fmax |_ maximum clock frequency (76 i 59 MHz cy [input capacitance | | 3s | 3.5 pF | . : 1 power dissipation Cep capacitance per flip-flop notes T and 2 24 | 29 pF | GND = 0 V; Tamb = 28 C: ty = tf = Ens Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in #W): Po =Cppx Vee x ff +2 (CL x Vcc x fol where: fj = input frequency in MHz CL = output toad capacitance in pF fo = output frequency in MHz Vec supply voltage in V E (Ci x Vec? x fo) = sum of outputs 2. For HC the condition is V} = GND to Vcc For HCT the condition is V} = GND to V7c 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION [ Pin NO. | SYMBOL NAME AND FUNCTION an yo a | 1,13 | 1Rp, 2Ro | asynchronous reset-direct input (active LOW) 2,12 | 10, 2D | data inputs | 3,11 1CP, 2CP | clock input {LOW-to-HIGH, edge-triggered} | 4,10 | 189, 28p | asynchronous set-direct input (active LOW) 1 | 5,9 14, 20 | true flip-flop outputs | 6,8 10, 20 complement flig-flop outputs 7 GND ground (0 V} 14 Veco positive supply voltage _ T tA LJ u [4] Vee 4] 10 102] [3] 2% 159 4285 1ce (3 | fiz] 20 Feu, a 1a 5 yi} 74 iy] 2cP a1? | oe ge 708 ale 3) 28 11 2P 5 Gs 208 By rs} 2a uw aa Rofo ono {| | 8) 20 7z9a117 via P29ITAD T2936 Fig. 1 Pin confiquration. Fig. 2 Lagic symbol. Fig. 3 IEC logic symbol. September 1993 187 74HC/HCT74 flip-flops Fj g. 4 Functional diagram, FUNCTION TABLE INPUTS OUTPUTS 3 Sp Rp ce D a a 6 L 4 x x H L H L Xx xX L H L L x x H H INPUTS OUTPUTS a 5p Ro cP a Qn+1 One s H H t L L H H H t H H L H = HIGH voltage level rraane L = LOW voltage level x = don't care t = LOW-to-HIGH CP transition Qn+1 = State after the next LOW-to-HIGH CP transition Fig. 5 Logic diagram (one flip-flop). >-- 7293120.9 Qa a 188 September 1993 Dual D-type flip-flop with set and reset; positive-edge trigger J4HC/HCT74 flip-flops DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: flip-flops AC CHARACTERISTICS FOR 74HC GND = 0 V; t, = t = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Veg | WAVEFORMS {_ +25 40 ta +85 | 401t0 +125 Vv | min. | typ. | max. [min max. | min. | max. . 47 1175 | 220 265 2.0 PHL! _|_ Propagation delay 17 | 36 44 53 | os 45 | Fig. 6 tPLH ACP to nQ, nQ 14 | 30 | | 37 | 45 6.0 | if | von del | 50 | 200 | 250 | 300 2.0 PHL! _]_ Propagation delay | 118 | 40 | 50 60 }ns | 45 | Fig.7 tPLH nS tonQ, nQ L [14 } 34 (43 51 6.0 | on del 52 [200 | | 250 | 300 2.0 | "PHL! propagation delay 19 | 40 | 50 60 | ns 45 | Fig 7 | tPLH nRp to Qn is faa | fas 51 | 60 | T / | | 19 175 | | 95 110 2.0 | 'THL! | output transition time 15 19 22 | ns 45 | Fig 6 TLR [ 6 {13 16 19 6.0 mat go | 19 | 100 | 120 2.0 tw clock puise width 16 7 / 20 | 24 ns 45 Fig, 6 L HIGH or LOW 114 [6 | 17 20. | 6.0 | . go | 19 100 | 120 20 | tw | set or reset pulse width 16 7 20 24 ns 45 Fig. 7 LOW 14/6 17 | 20 6.0 | 30 |3 40 | 45 | 2.0 t removal time 6 1 8 9 ns 45 Fig. 7 rem set or reset 5 1 7 8 6.0 setup time | 60 78 90 | | 2.0 et 18 ns 45 | Fig. 6 Mofo Bat LE) EL ie [eee T hold ti | 3. | -6 3 3 | 2.0 ord time 2 3 3 ns 45 | Fig 6 th nD to nCP | 3 a 3 3 | 60 a eo | 23 48 lag | | 2.0 f maximum clack pulse 30 | 69 24 20 MHz | 4.5 | Fig.6 max frequency 35 32 28 24 | 6.0 September 1993 189 74HC/HCT74 flip-flops DC CHARACTERISTICS FOR 74HCT For the OC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: flip-flops Note to HCT types The value of additional quiescent supply current (Alcc) for a unit load of 1 is given in the family specifications. To determine Alec per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT COEFFICIENT nD 0,70 nip 0.70 np 0.80 ncP 0.80 AC CHARACTERISTICS FOR 74HCT GND = 0 V: ty = te = Gas; CL = 50 pF Tamb (C} TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT! Veco] WAVEFORMS +25 40 to +85 | 40to +125 Vv min. | typ. | max. | min.| max. | min, | max. tpHe/ Propagation detay 1 44 5 45 Fig. 6 tPLH nCP to nQ, n@ 8 | 35 3 ns 9 tPHL/ | Propagation delay 23 | 40 50 60 | ns 4.5 | Fig? tPLH np to nd, na tpHL/ | Propagation delay 24 | 40 50 60 Jos | 45 | Fig? tPLH nRo tond, nO tH! output transition time 7 | 18 19 22 | ns 4.5 | Fig.6 'TLH ww clock pulse wan 18 | 9 23 27 ns 45 | Fig. 6 tw set pulse width 16 9 20 24 as 45 Fig. ? removal time 9 ns 45 Fig. 7 trem set or reset 6 ; 8 teu ee 12/5 15 18 ns 4.5 | Fig. 6 n hold time -3 3 3 ns 4.5 | Fig.6 th nD to nCP 3 f maximum clock pulse 27 | 54 22 18 MHz | 45 | Fig.6 max frequency 190 September 1993 74HC/HCT74 flip-flops Dual D-type flip-flop with set and reset; positive-edge trigger AC WAVEFORMS aD INPUT | | | | ncP INPUT Fig. 6 Waveforms showing the clock (nCP) to output (nQ, nO) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP tonD hold times, the output transition times and the maximum clock pulse frequency. nQ OUTPUT ad OUTPUT Note to Fig. 6 The shaded areas indicate when the input is permitted to change for predictable output | I ! | | 7293122.1 performance. | ACP INPUT Vigil | | all | | nS INPUT val? | | nip INPUT | | nQ@ OUTPUT | Fig. 7 Waveforms showing the set (nSp) and reset _ (nAip) input to output (nQ, nO} propagation delays, | nd OUTPUT the set and reset pulse widths and the nRo to nCP 7222116 removal time. | Note to AC waveforms (1) HC : Vi = 50%; V) = GND to Voc. HCT: Vy = 1.3V; V,} = GND to 3V. September 1993