MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features 1/3-Inch CMOS Digital Image Sensor MT9M021/MT9M031 Datasheet, Rev. G For the latest datasheet revision, please visit www.onsemi.com Features * * * * * * * * * * Table 1: Superior low-light performance HD video (720p60) Global shutter Video/Single Frame mode Flexible row-skip modes On-chip AE and statistics engine Parallel and serial output Support for external LED or flash Auto black level calibration Context switching Parameter Typical Value Optical format Active pixels Pixel size 1/3-inch (6 mm) 1280 x 960 = 1.2 Mp 3.75m RGB Bayer or Color filter array Monochrome Shutter type Global shutter Input clock range 6 - 50 MHz 74.25 MHz Output pixel clock (maximum) Serial HiSPi (iBGA package only) Output Parallel 12-bit Full resolution 45 fps Frame rate 720p 60 fps Responsivity (Monochrome) 6.1 V/lux-sec Responsivity (Color) 5.3 V/lux-sec 38 dB SNRMAX Dynamic range 64 dB I/O 1.8 or 2.8 V Digital 1.8 V Supply voltage Analog 2.8 V HiSPi 0.4 V Power consumption <400 mW Operating temperature (ambient) -30C to +70C 9 x 9 mm 64-pin iBGA Package options 10x10mm 48-pin iLCC Applications * Scene processing * Scanning and machine vision * 720p60 video applications General Description The ON Semiconductor MT9M021/MT9M031 is a 1/3inch CMOS digital image sensor with an active-pixel array of 1280H x 960V. It includes sophisticated camera functions such as auto exposure control, windowing, scaling, row skip mode, and both video and single frame modes. It is designed for low light performance and features a global shutter for accurate capture of moving scenes. It is programmable through a simple two-wire serial interface. The MT9M021/MT9M031 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including scanning and HD video. MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN Key Parameters 1 (c)Semiconductor Components Industries, LLC,2015 MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Ordering Information Ordering Information Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description MT9M021IA3XTC-DPBR 1.2 MP 1/3" GS CIS Dry Pack with Protective Film, Double Side BBAR Glass MT9M021IA3XTC-DRBR 1.2 MP 1/3" GS CIS Dry Pack without Protective Film, Double Side BBAR Glass MT9M021IA3XTM-DPBR 1.2 MP 1/3" GS CIS Dry Pack with Protective Film, Double Side BBAR Glass MT9M021IA3XTM-DRBR 1.2 MP 1/3" GS CIS Dry Pack without Protective Film, Double Side BBAR Glass MT9M021IA3XTMZ-DPBR 1.2 MP 1/3" GS CIS Dry Pack with Protective Film, Double Side BBAR Glass MT9M021IA3XTMZ-DRBR 1.2 MP 1/3" GS CIS Dry Pack without Protective Film, Double Side BBAR Glass MT9M021IA3XTMZ-TPBR 1.2 MP 1/3" GS CIS Tape & Reel with Protective Film, Double Side BBAR Glass MT9M031D00STMC24BC1-200 1 MP 1/6" SOC Die Sales, 200 m Thickness MT9M031I12STC-DPBR 1 MP 1/6" SOC Dry Pack with Protective Film, Double Side BBAR Glass MT9M031I12STC-DRBR 1.2 MP 1/3" GS CIS Dry Pack without Protective Film, Double Side BBAR Glass MT9M031I12STM-DPBR 1.2 MP 1/3" GS CIS Dry Pack with Protective Film, Double Side BBAR Glass MT9M031I12STM-DRBR 1.2 MP 1/3" GS CIS Dry Pack without Protective Film, Double Side BBAR Glass MT9M031I12STMZ-DRBR 1.2 MP 1/3" GS CIS Dry Pack without Protective Film, Double Side BBAR Glass MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 2 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Ordering Information MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 3 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Ordering Information MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 4 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 5 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 9x9mm 64-Ball iBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 48 iLCC Package, Parallel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Differential Output Voltage for Clock or Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Eye Diagram for Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Skew Within the PHY and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Quantum Efficiency - Monochrome Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Quantum Efficiency - Color Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 64-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 48-pin iLCC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 6 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Descriptions - 64-Ball iBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Descriptions - 48 iLCC Package, Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 I/O Timing Characteristics1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 I/O Rise Slew Rate (2.8V VDD_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 I/O Fall Slew Rate (2.8V VDD_IO)1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 I/O Rise Slew Rate (1.8V VDD_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 I/O Fall Slew Rate (1.8V VDD_IO)1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Operating Current Consumption for Parallel Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Standby Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Input Voltage and Current (HiSPi Power Supply 0.4 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 7 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor General Description General Description The ON Semiconductor MT9M021/MT9M031 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a full-resolution image at 45 frames per second (fps). It outputs 12-bit raw data, using either the parallel or serial (HiSPi) output ports. The device may be operated in video (master) mode or in frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock. A dedicated FLASH pin can be programmed to control external LED or flash exposure illumination. The MT9M021/MT9M031 includes additional features to allow application-specific tuning: windowing, adjustable auto-exposure control, auto black level correction, on-board temperature sensor, and row skip and digital binning modes. The sensor is designed to operate in a wide temperature range (-30C to +70C). Functional Overview The MT9M021/MT9M031 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 MHz. The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: Block Diagram Active Pixel Sensor (APS) Array Power Temperature OTPM sensor Timing and Control (Sequencer) PLL External Clock Auto Exposure and Stats Engine Pixel Data Path (Signal Processing) Analog Processing and A/D Conversion Serial Output Parallel Output Flash Trigger Two-Wire Serial Interface Memory Control Registers User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 1.2 Mp Active- Pixel Sensor array. The MT9M021/MT9M031 features global shutter technology for accurate capture of moving images. The exposure of the entire array is controlled by programming the integration time by register setting. All rows simultaneously integrate light prior to readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to- digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 8 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview processing signal chain (which provides further data path corrections and applies digital gain). The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization signals. Features Overview The MT9M021/MT9M031 Global Sensor shutter has a wide array of features to enhance functionality and to increase versatility. A summary of features follows. Please refer to the MT9M021/MT9M031 Developer Guide for detailed feature descriptions, register settings, and tuning guidelines and recommendations. * Operating Modes The MT9M021/MT9M031 works in master (video), trigger (single frame), or Auto Trigger modes. In master mode, the sensor generates the integration and readout timing. In trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. The exposure time is programmed through the twowire serial interface for both modes. Note: Trigger mode is not compatible with the HiSPi interface. * Window Control Configurable window size and blanking times allow a wide range of resolutions and frame rates. Digital binning and skipping modes are supported, as are vertical and horizontal mirror operations. * Context Switching Context switching may be used to rapidly switch between two sets of register values. Refer to the MT9M021/MT9M031 Developer Guide for a complete set of context switchable registers. * Gain The MT9M021/MT9M031 Global Shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x. * Automatic Exposure Control The integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. Refer to the MT9M021/MT9M031 Developer Guide for more details. * HiSPi The MT9M021/MT9M031 Global Shutter image sensor supports two or three lanes of Streaming-SP or Packetized-SP protocols of ON Semiconductor's High-Speed Serial Pixel Interface. * PLL An on chip PLL provides reference clock flexibility and supports spread spectrum sources for improved EMI performance. * Reset The MT9M021/MT9M031 may be reset by a register write, or by a dedicated input pin. * Output Enable The MT9M021/MT9M031 output pins may be tri-stated using a dedicated output enable pin. * Temperature Sensor * Black Level Correction * Row Noise Correction * Column Correction * Test Patterns Several test patterns may be enabled for debug purposes. These include a solid color, color bar, fade to grey, and a walking 1s test pattern. MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 9 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview Typical Configuration: Serial Four-Lane HiSPi Interface VDD_IO 1.5k2, 3 1.5k2 Digital Digital I/O Core power1 power1 Master clock (6-50 MHz) VDD HiSPi power1 VDD_SLVS Figure 2: EXTCLK VDD_PLL VAA VAA_PIX SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N SDATA SCLK OE_BAR STANDBY RESET_BAR From controller Analog Analog PLL power1 power1 power1 SLVS3_P SLVS3_N SLVSC_P SLVSC_N To controller TEST FLASH VDD_IO VDD Notes: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN VDD_SLVS VDD_PLL VAA DGND AGND Digital ground Analog ground VAA_PIX 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The parallel interface output pads can be left unconnected if the serial output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the MT9M021/MT9M031 demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is minimized. 7. Although 4 serial lanes are shown, the MT9M021/MT9M031 supports only 2 or 3 lane HiSPi. 10 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview Figure 3: Typical Configuration: Parallel Pixel Data Interface 1.5k2, 3 1.5k2 Digital Digital core I/O power1 power1 Master clock (6-50 MHz) VDD_IO PLL Analog Analog power1 power1 power1 VDD VDD_PLL VAA DOUT [11:0] EXTCLK PIXCLK LINE_VALID FRAME_VALID SDATA SCLK TRIGGER OE_BAR STANDBY RESET_BAR From Controller VAA_PIX To controller FLASH TEST DGND VDD_IO VDD VDD_PLL VAA VAA_PIX Digital ground Notes: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN AGND Analog ground 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The serial interface output pads can be left unconnected if the parallel output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the MT9M021/MT9M031 demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is minimized. 11 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview Figure 4: 9x9mm 64-Ball iBGA Package 1 A 2 3 4 5 6 7 8 SLVS0N SLVS0P SLVS1N SLVS1P VDD VDD STANDBY SLVS2N SLVS2P VDD VAA VAA VDD AGND AGND VAA_PIX VAA_PIX B VDD_PLL SLVSCN SLVSCP C EXTCLK VDD_ SLVS SLVS3N SLVS3P DGND D SADDR SCLK SDATA DGND DGND E LINE_ VALID FRAME_ VALID PIXCLK FLASH DGND VDD_IO RESERVED RESERVED F DOUT8 DOUT9 DOUT10 DOUT11 DGND VDD_IO TEST RESERVED G DOUT4 DOUT5 DOUT6 DOUT7 DGND VDD_IO TRIGGER OE_BAR H DOUT0 DOUT1 DOUT2 DOUT3 DGND VDD_IO VDD_IO RESET _BAR VDD Top View (Ball Down) MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 12 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview Table 3: Pin Descriptions - 64-Ball iBGA Package Name iBGA Pin Type Description SLVS0_N A2 Output HiSPi serial data, lane 0, differential N. SLVS0_P A3 Output HiSPi serial data, lane 0, differential P. SLVS1_N A4 Output HiSPi serial data, lane 1, differential N. SLVS1_P A5 Output HiSPi serial data, lane 1, differential P. STANDBY A8 Input Standby-mode enable pin (active HIGH). VDD_PLL B1 Power PLL power. SLVSC_N B2 Output HiSPi serial DDR clock differential N. SLVSC_P B3 Output HiSPi serial DDR clock differential P. SLVS2_N B4 Output HiSPi serial data, lane 2, differential N. SLVS2_P B5 Output HiSPi serial data, lane 2, differential P. VAA B7, B8 Power Analog power. External input clock. EXTCLK C1 Input VDD_SLVS C2 Power HiSPi power. SLVS3_N C3 Output HiSPi serial data, lane 3, differential N. SLVS3_P C4 Output HiSPi serial data, lane 3, differential P. DGND Power Digital GND. VDD C5, D4, D5, E5, F5, G5, H5 A6, A7, B6, C6, D6 Power Digital power. AGND C7, C8 Power Analog GND. SADDR D1 Input Two-Wire Serial address select. SCLK D2 Input Two-Wire Serial clock input. SDATA D3 I/O Two-Wire Serial data I/O. VAA_PIX D7, D8 Power Pixel power. LINE_VALID E1 Output Asserted when DOUT line data is valid. FRAME_VALID E2 Output Asserted when DOUT frame data is valid. PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock. FLASH E4 Output Control signal to drive external light sources. VDD_IO E6, F6, G6, H6, H7 Power I/O supply power. DOUT8 F1 Output Parallel pixel data output. DOUT9 F2 Output Parallel pixel data output. DOUT10 F3 Output Parallel pixel data output. DOUT11 F4 Output Parallel pixel data output (MSB) TEST F7 Input Manufacturing test enable pin (connect to DGND). DOUT4 G1 Output Parallel pixel data output. DOUT5 G2 Output Parallel pixel data output. DOUT6 G3 Output Parallel pixel data output. DOUT7 G4 Output Parallel pixel data output. TRIGGER G7 Input Exposure synchronization input. OE_BAR G8 Input Output enable (active LOW). DOUT0 H1 Output Parallel pixel data output (LSB) DOUT1 H2 Output Parallel pixel data output. DOUT2 H3 Output Parallel pixel data output. DOUT3 H4 Output Parallel pixel data output. MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 13 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview Table 3: Pin Descriptions (continued)- 64-Ball iBGA Package Name iBGA Pin RESET_BAR H8 Reserved E7, E8, F8 7 Description Input Asynchronous reset (active LOW). All settings are restored to factory default. n/a Reserved (do not connect). 6 5 4 3 2 1 48 47 46 45 44 43 E X T C LK V DD_P LL DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 DGND NC 48 iLCC Package, Parallel Output D GND Figure 5: Type DOUT7 NC 42 8 DOUT8 NC 41 9 DOUT9 V AA 40 10 DOUT10 AGND 39 11 DOUT11 VAA_PIX 38 12 V DD_IO VAA_PIX 37 13 PIXCLK VAA 36 14 V DD AGND 15 S CLK VAA 34 16 S DATA Reserved 33 17 RESET _BAR Reserved 32 Reserved 31 MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN FLASH T R IG G E R FRAME_VALID LINE_VALID 22 23 24 25 26 27 28 29 14 D GND TEST 21 S ADDR 20 OE_BAR NC 19 STANDBY NC V DD_IO V DD 18 35 30 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Features Overview Table 4: Pin Descriptions - 48 iLCC Package, Parallel Pin Number Name Type Description 1 DOUT4 Output Parallel pixel data output. 2 DOUT5 Output Parallel pixel data output. 3 DOUT6 Output Parallel pixel data output. 4 VDD_PLL Power PLL power. 5 EXTCLK Input External input clock. 6 DGND Power Digital ground. 7 DOUT7 Output Parallel pixel data output. 8 DOUT8 Output Parallel pixel data output. Output Parallel pixel data output. 9 DOUT9 10 DOUT10 Output Parallel pixel data output. 11 DOUT11 Output Parallel pixel data output (MSB). 12 VDD_IO Power I/O supply power. 13 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. 14 VDD Power Digital power. 15 SCLK Input Two-Wire Serial clock input. 16 SDATA I/O 17 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default. 18 VDD_IO Power I/O supply power. 19 VDD Power 20 NC Two-Wire Serial data I/O. Digital power. No connection. 21 NC 22 STANDBY Input No connection. Standby-mode enable pin (active HIGH). 23 OE_BAR Input Output enable (active LOW). 24 SADDR Input Two-Wire Serial address select. Manufacturing test enable pin (connect to DGND). 25 TEST Input 26 FLASH Output Flash output control. 27 TRIGGER Input 28 FRAME_VALID Output Asserted when DOUT frame data is valid. Exposure synchronization input. 29 LINE_VALID Output Asserted when DOUT line data is valid. 30 DGND Power Digital ground 31 Reserved n/a Reserved (do not connect). 32 Reserved n/a Reserved (do not connect). 33 Reserved n/a 34 VAA Power 35 AGND Power Analog ground. 36 VAA Power Analog power. 37 VAA_PIX Power Pixel power. 38 VAA_PIX Power Pixel power. Reserved (do not connect). Analog power. 39 AGND Power Analog ground. 40 VAA Power Analog power. 41 NC No connection. 42 NC No connection. MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 15 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 4: Pin Descriptions (continued)- 48 iLCC Package, Parallel Pin Number Name Type Description 43 NC 44 DGND Power No connection. Digital ground. 45 DOUT0 Output Parallel pixel data output (LSB) 46 DOUT1 Output Parallel pixel data output. 47 DOUT2 Output Parallel pixel data output. 48 DOUT3 Output Parallel pixel data output. Electrical Specifications Unless otherwise stated, the following specifications apply to the following conditions: VDD = 1.8V - 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V 0.3V; VDD_SLVS = 0.4V - 0.1/+0.2; TA = -30C to +70C; output load = 10pF; PIXCLK frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 6 and Table 5. Figure 6: Two-Wire Serial Bus Timing Parameters SDATA tLOW tf tSU;DAT tr tf tHD;STA tr tBUF SCLK S tHD;STA Note: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN tHD;DAT tHIGH tSU;STA Sr tSU;STO P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. 16 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 5: Two-Wire Serial Bus Characteristics f EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; TA = 25C Standard-Mode Parameter Symbol Fast-Mode Min Max Min Max Unit SCL 0 100 0 400 KHz HD;STA 4.0 - 0.6 - S 4.7 - 1.3 - S f SCLK Clock Frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated t LOW period of the SCLK clock t HIGH period of the SCLK clock t LOW HIGH 4.0 - 0.6 - S Set-up time for a repeated START condition tSU;STA 4.7 - 0.6 - S Data hold time: tHD;DAT 04 3.455 06 0.95 S Data set-up time tSU;DAT 250 - 1006 - nS Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7 300 nS Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7 300 nS tSU;STO 4.0 - 0.6 - S tBUF 4.7 - 1.3 - S Cb - 400 - 400 pF Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Serial interface input pin capacitance SDATA max load capacitance SDATA pull-up resistor Notes: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN CIN_SI - 3.3 - 3.3 pF CLOAD_SD - 30 - 30 pF RSD 1.5 4.7 1.5 4.7 K This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 1. 2. Two-wire control is I2C-compatible. 3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. 4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. 17 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications I/O Timing By default, the MT9M021/MT9M031 launches pixel data, FV and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV and LV using the rising edge of PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028. See Figure 7 below and Table 6 on page 18 for I/O timing (AC) characteristics. Figure 7: I/O Timing Diagram tR t RP tF t FP 90% 90% 10% 10% t EXTCLK EXTCLK PIXCLK t PD Data[11:0] Pxl _0 LINE_VALID/ FRAME_VALID Table 6: Pxl _1 Pxl _2 Pxl _n t PLH t PFL t PFH t PLL FRAME_VALID trails LINE_VALID by 6 PIXCLKs. FRAME_VALID leads LINE_VALID by 6 PIXCLKs. I/O Timing Characteristics1 Parallel Output VDD_IO=2.8V Symbol Definition fEXTCLK Input clock frequency Condition Min 6 tEXTCLK Input clock period 20 Typ VDD_IO=1.8V Max Min 50 6 166 20 Typ Max Unit 50 MHz 166 ns PLL enabled 3 4 3 4 ns Input clock fall time PLL enabled 3 4 3 4 ns tRP PIXCLK rise time Slew setting = 4 (default) 2.3 4.6 2.3 4.6 ns tFP PIXCLK fall time Slew setting = 4 (default) 3 4.4 3 4.4 ns 60 40 60 % 74.25 6 74.25 MHz 4 -3 4.5 ns tR Input clock rise time tF 40 PIXCLK duty cycle fPIXCLK PIXCLK frequency2 Nominal voltages, PLL Enabled 6 Nominal voltages, PLL Enabled -3 PIXCLK to data valid tPD MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 18 50 2.3 50 2.3 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 6: I/O Timing Characteristics1 (continued) Parallel Output VDD_IO=2.8V Symbol Definition Condition tPFH VDD_IO=1.8V Min Typ Max Min Typ Max Unit Nominal voltages, PLL Enabled -3 1.5 4 -3 1.5 4.5 ns PIXCLK to FV HIGH Nominal voltages, PLL Enabled -3 2.3 4 -3 2.3 4.5 ns PIXCLK to LV HIGH Nominal voltages, PLL Enabled -3 1.5 4 -3 1.5 4.5 ns PIXCLK to FV LOW Nominal voltages, PLL Enabled -3 2 4 -3 2 4.5 ns PIXCLK to LV LOW tPLH tPFL tPLL Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70C ambient at 90% of VDD_IO, and -30C at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20pF. 2. Jitter from PIXCLK is already taken into account as the data of all the output parameters. I/O Rise Slew Rate (2.8V VDD_IO)1 Table 7: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 1.08 0.77 0.58 0.44 0.32 0.23 0.16 0.10 1.77 1.26 0.95 0.70 0.51 0.37 0.25 0.15 2.72 1.94 1.46 1.08 0.78 0.56 0.38 0.22 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Note: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70C ambient at 90% of VDD_IO, and -30C at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20pF. 19 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications I/O Fall Slew Rate (2.8V VDD_IO)1 Table 8: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 1.00 0.76 0.60 0.46 0.35 0.25 0.17 0.11 1.62 1.24 0.98 0.75 0.56 0.40 0.27 0.16 2.41 1.88 1.50 1.16 0.86 0.61 0.41 0.24 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Note: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70C ambient at 90% of VDD_IO, and -30C at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20pF. I/O Rise Slew Rate (1.8V VDD_IO)1 Table 9: Parallel Slew Rate (R0x306E[15:13]) Conditions 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default Note: Min Typ Max Units 0.41 0.30 0.24 0.19 0.14 0.10 0.07 0.04 0.65 0.47 0.37 0.28 0.21 0.15 0.10 0.06 1.10 0.79 0.61 0.46 0.34 0.24 0.16 0.10 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70C ambient at 90% of VDD_IO, and -30C at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20pF. I/O Fall Slew Rate (1.8V VDD_IO)1 Table 10: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 0.42 0.32 0.26 0.20 0.16 0.12 0.08 0.05 0.68 0.51 0.41 0.32 0.24 0.18 0.12 0.07 1.11 0.84 0.67 0.52 0.39 0.28 0.19 0.11 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Notes: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70C ambient at 90% of VDD_IO, and -30C at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20pF. 20 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications DC Electrical Characteristics The DC electrical characteristics are shown in Table 11, Table 12, Table 13, and Table 14. Table 11: DC Electrical Characteristics Symbol Definition Condition Min Typ Max Unit VDD Core digital voltage 1.7 1.8 1.95 V VDD_IO I/O digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 V VAA Analog voltage 2.5 2.8 3.1 V VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V VDD_PLL PLL supply voltage 2.5 2.8 3.1 V VDD_SLVS HiSPi supply voltage 0.3 0.4 0.6 V VIH Input HIGH voltage VDD_IO * 0.7 - - V - - V 20 - VDD_IO * 0.3 - A VDD_IO - 0.3 - - V VIL Input LOW voltage IIN Input leakage current VOH Output HIGH voltage VOL Output LOW voltage VDD_IO = 2.8V - - 0.4 V IOH Output HIGH current At specified VOH -22 - - mA IOL Output LOW current At specified VOL - - 22 mA Caution Table 12: No pull-up resistor; VIN = VDD_IO or DGND Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Symbol VSUPPLY Power supply voltage (all supplies) -0.3 4.5 V VSUPPLY ISUPPLY IGND Total power supply current - 200 mA ISUPPLY Total ground current - 200 mA IGND VIN VOUT DC input voltage -0.3 VDD_IO + 0.3 V VIN DC output voltage -0.3 VDD_IO + 0.3 V TSTG1 VOUT Storage temperature -40 +85 C TSTG1 Note: Table 13: 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Current Consumption for Parallel Output VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V; VDD= 1.8V; PLL Enabled and PIXCLK = 74.25 MHz; TA = 25C; CLOAD = 10pF Condition Digital operating current Symbol Parallel, Streaming, Full resolution 45 fps Typ Max Unit IDD1 Min 45 55 mA I/O digital operating current Parallel, Streaming, Full resolution 45 fps IDD_IO 501 - mA Analog operating current Parallel, Streaming, Full resolution 45 fps IAA 45 50 mA Pixel supply current Parallel, Streaming, Full resolution 45 fps IAA_PIX 6 10 mA PLL supply current Parallel, Streaming, Full resolution 45 fps IDD_PLL 6 8 mA Note: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 1. IDD_IO operating current is specified with image at 1/2 saturation level. 21 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 14: Standby Current Consumption Analog - VAA + VAA_PIX + VDD_PLL; Digital - VDD + VDD_IO; TA = 25C Definition Hard standby (clock off, driven low) Hard standby (clock on, EXTCLK = 20 MHz) Soft standby (clock off, driven low) Soft standby (clock on, EXTCLK = 20 MHz) Condition Min Typ Max Unit Analog, 2.8V Digital, 1.8V Analog, 2.8V Digital, 1.8V Analog, 2.8V Digital, 1.8V Analog, 2.8V Digital, 1.8V - - - - - - - - 3 8 12 0.87 3 8 12 0.87 10 75 20 1.3 10 75 20 1.3 A A A mA A A A mA HiSPi Electrical Specifications The ON Semiconductor MT9M021/MT9M031 sensor supports SLVS mode only, and does not have a DLL for timing adjustments. Refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The HiSPi transmitter electrical specifications are listed at 700 MHz. Table 15: Input Voltage and Current (HiSPi Power Supply 0.4 V) Measurement Conditions: Max Freq 700 MHz Parameter Symbol Min Typ Max Unit IDD_SLVS - 10 15 mA HiSPi common mode voltage (driving 100 load) VCMD VDD_SLVS x 0.45 VDD_SLVS/2 VDD_SLVS x 0.55 V HiSPi differential output voltage (driving 100 load) |VOD| VDD_SLVS x 0.36 VDD_SLVS/2 VDD_SLVS x 0.64 V Change in VCM between logic 1 and 0 VCM 25 mV Change in |VOD| between logic 1 and 0 |VOD| 25 mV Supply current (PWRHiSPi) (driving 100 load) Vod noise margin 30 % Difference in VCM between any two channels |VCM| 50 mV Difference in VOD between any two channels |VOD| 100 mV Common-mode AC voltage (pk) without VCM cap termination VCM_ac 50 mV Common-mode AC voltage (pk) with VCM cap termination VCM_ac 30 mV Max overshoot peak |VOD| VOD_ac 1.3 x |VOD| V Max overshoot Vdiff pk-pk Vdiff_pkpk 2.6 x |VOD| V 70 20 % Eye Height Single-ended output impedance Output impedance mismatch MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN NM - Veye 1.4 x VOD Ro 35 Ro 22 50 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Figure 8: Differential Output Voltage for Clock or Data Pairs VDIFFmax VDIFFmin 0V Diff) Output Signal is 'Cp - Cn' or 'Dp - Dn' Table 16: Rise and Fall Times Measurement Conditions: HiSPi Power Supply 0.4V, Max Freq 700 MHz Parameter Symbol Min Typ Max Unit Data Rate 1/UI 280 - 700 Mb/s Max setup time from transmitter TxPRE 0.3 - - UI1 Max hold time from transmitter TxPost 0.3 - - UI Rise time (20% - 80%) RISE - 0.25UI - Fall time (20% - 80%) FALL 150ps 0.25 UI - 50 Clock duty PLL_DUTY 45 Bitrate Period tpw 1.43 Eye Width teye 0.3 55 % 3.57 ns1 UI1, 2 ttotaljit 0.2 UI1, 2 Clock Period Jitter(RMS) tckjit 50 ps2 Clock cycle to cycle jitter (RMS) tcyjit 100 ps2 0.1 UI1, 2 2.1 UI1, 5 100 ps6 Data Total jitter (pk pk)@1e-9 Clock to Data Skew tchskew PHY-to-PHY Skew t|PHYskew| Mean diferential skew tDIFFSKEW Notes: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN -0.1 -100 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from 0V crossing point w/ DLL off. 3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. 23 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Figure 9: Eye Diagram for Clock and Data Signals RISE 80% D A T A M A SK V d i ff 20% T x Pr e T x Po s t FALL UI/ 2 UI/ 2 V d i ff M a x V d i ff C L O C K M A SK T r i g ge r/ R efe re nce C L K JIT T ER Figure 10: Skew Within the PHY and Output Channels V C MD t C M PSK EW MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN t C HSKEW1 PHY 24 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Power-On Reset and Standby Timing Power-Up Sequence The recommended power-up sequence for the MT9M021/MT9M031 is shown in Figure 11. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply. 2. After 0-10s, turn on VAA and VAA_PIX power supply. 3. After 0-10s, turn on VDD_IO power supply. 4. After the last power supply is stable, enable EXTCLK. 5. Assert RESET_BAR for at least 1ms. 6. Wait 150000 EXTCLKs (for internal initialization into software standby. 7. Configure PLL, output, and image settings to desired values. 8. Wait 1ms for the PLL to lock. 9. Set streaming mode (R0x301a[2] = 1). Figure 11: Power Up VDD_PLL (2.8) VAA_PIX VAA (2.8) VDD_IO (1.8/2.8) t0 t1 t2 VDD (1.8) t3 VDD_SLVS (0.4) EXTCLK t4 RESET_B tx t5 Internal Initialization Hard Reset Table 17: t6 Software Standby PLL Lock Streaming Power-Up Sequence Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX t0 0 10 - s VAA/VAA_PIX to VDD_IO t1 0 10 - s VDD_IO to VDD t2 0 10 - s VDD to VDD_SLVS t3 0 10 - s Xtal settle time tx - 301 - ms Hard Reset t4 12 - - ms Internal Initialization t5 150000 - - EXTCLKs PLL Lock Time t6 1 - - ms Notes: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 1. Xtal settling time is component-dependent, usually taking about 10 - 100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after 25 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing other supplies then the sensor may have functionality issues and will experience high current draw on this supply. Power-Down Sequence The recommended power-down sequence for the MT9M021/MT9M031 is shown in Figure 12. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. Figure 12: Power Down VDD_SLVS (0.4) t0 VDD (1.8) t1 V DD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until next Power up cycle Table 18: Power-Down Sequence Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD VDD to VDD_IO VDD_IO to VAA/VAA_PIX VAA/VAA_PIX to VDD_PLL t0 t1 t2 t3 0 0 0 0 - - - - - - - - S S S S MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 26 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Table 18: Power-Down Sequence Definition Symbol Minimum Typical Maximum Unit PwrDn until Next PwrUp Time t4 100 - - mS Note: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. 27 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Figure 13: Quantum Efficiency - Monochrome Sensor 80 70 Quantum Efficiency (%) 60 50 40 30 20 10 0 350 450 550 650 750 850 950 1050 1150 Wavelength (nm) MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 28 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Figure 14: Quantum Efficiency - Color Sensor MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 29 (c)Semiconductor Components Industries, LLC,2015. 64-Ball iBGA Package Outline Drawing Figure 15: MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN Package Dimensions MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Package Dimensions 30 All dimensions in millimeters. (c)Semiconductor Components Industries, LLC,2015 Note: 48-pin iLCC Package Drawing MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN Figure 16: (c)Semiconductor Components Industries, LLC,2015 MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Package Dimensions 31 MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Revision History Revision History Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15 * Updated "Ordering Information" on page 2 Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/4/12 * Converted to ON Semiconductor template * Removed Confidential marking Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/4/12 * Updated to Production * Updated Table 1, "Key Parameters," on page 1 * Updated Table 2, "Available Part Numbers," on page 2 * Updated "General Description" on page 8 * Updated Figure 2: "Typical Configuration: Serial Four-Lane HiSPi Interface," on page 10 * Updated Figure 3: "Typical Configuration: Parallel Pixel Data Interface," on page 11 * Updated Table 5, "Two-Wire Serial Bus Characteristics," on page 17 * Updated Figure 7: "I/O Timing Diagram," on page 18 * Updated Table 6, "I/O Timing Characteristics1," on page 18 * Added Table 7, I/O Rise Slew Rate (2.8V Vdd_IO)1 and Table 8, "I/O Fall Slew Rate (2.8V Vdd_IO)1," on page 20 * Added Table 9, I/O Rise Slew Rate (1.8V Vdd_IO)1 and Table 10, "I/O Fall Slew Rate (1.8V Vdd_IO)1," on page 20 * Updated Table 13, "Operating Current Consumption for Parallel Output," on page 21 * Updated Table 14, "Standby Current Consumption," on page 22 Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/17/12 * Added MT9M031 * Updated Table 1, "Key Parameters," on page 1 * Updated Table 2, "Available Part Numbers," on page 2 * Updated "LV Format Options" on page 14 * Updated "HiSPi Physical Layer" on page 15 * Added Figure 5: "48 iLCC Package, Parallel Output," on page 14 * Added Table 4, "Pin Descriptions - 48 iLCC Package, Parallel," on page 15 * Updated Figure 7: "I/O Timing Diagram," on page 18 * Updated Table 6, "I/O Timing Characteristics1," on page 18 * Updated "HiSPi Electrical Specifications" on page 22 * Added Table 15, "Input Voltage and Current (HiSPi Power Supply 0.4 V)," on page 22 * Added Figure 8: "Differential Output Voltage for Clock or Data Pairs," on page 23 * Added Table 16, "Rise and Fall Times," on page 23 * Added Figure 9: "Eye Diagram for Clock and Data Signals," on page 24 * Added Figure 10: "Skew Within the PHY and Output Channels," on page 24 * Added Figure 16: "48-pin iLCC Package Drawing," on page 31 * Deleted the following major sections and their sub-sections. Refer to the Developer Guide: - Pixel Data Format - Output Data Format - Two-Wire Serial Register Interface MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 32 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Revision History - Real-Time Context Switching * Replaced "Feature Description" with "Functional Overview" on page 8 and "Features Overview" on page 9 Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/14/11 * Updated to Preliminary * Updated operating temperature in Table 1, "Key Parameters," on page 1 and in "General Description" on page 8 * Updated Figure 6: "Two-Wire Serial Bus Timing Parameters," on page 16 * Updated Table 5, "Two-Wire Serial Bus Characteristics," on page 17 * Updated Figure 7: "I/O Timing Diagram," on page 18 * Added Table 6, "I/O Timing Characteristics1," on page 18 * Updated Table 6, "DC Electrical Characteristics," on page 14 * Replaced Table 10, Power Consumption with Table 13, "Operating Current Consumption for Parallel Output," on page 21 * Added Table 14, "Standby Current Consumption," on page 22 * Updated Table 14, Power Supply and Operating Temperatures * Deleted Table 14, "Input Voltage and Current," on page 39 * Added Table 15, "SLVS Electrical DC Specification," on page 40 * Updated Table 16, "SLVS Electrical Timing Specification," on page 40 * Updated Table 17, "Power-Up Sequence," on page 25 * Updated Figure 13: "Quantum Efficiency - Monochrome Sensor," on page 28 Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/16/09 * Updated the following parameters in Table 1, "Key Parameters," on page 1 - input clock range - responsivity - dynamic range * Updated Table 2, "Available Part Numbers," on page 2 * Replaced "scaling" with "digital binning" in third paragraph of "General Description" on page 8 * Updated master clock range in Figure 2 on page 10 and Figure 3 on page 11 * Updated number of rows in first sentence of first paragraph in "Pixel Array Structure" on page 10 * Updated array pixel coordinates in Figure 6 on page 12 * Added "Default Readout Order" on page 12 * Updated "Output Data Format" on page 13 * Added "Readout Sequence" on page 13 * Replaced "Parallel Data Timing" section with "Parallel Output Data Timing" on page 14 * Moved Figure 13, Line Timing and FRAME_VALID/LINE_VALID Signals and Table 5, Frame Time: Long Integration Time to new section "Frame Time" on page 17; added Table 4, "Frame Time (Example Based on 1280 x 960, 45 Frames Per Second)," on page 17 * Updated first paragraph of "Real-Time Context Switching" on page 19 * Updated Table 6, "Real-Time Context-Switchable Registers," on page 19 * Updated "Features" section as follows: - Updated "Trigger Mode" on page 20 - Moved "Hard Reset of Logic" and Soft Reset of Logic" to "Reset" on page 21 MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 33 (c)Semiconductor Components Industries, LLC,2015. MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor Revision History * * * * - Added "Readout Modes" on page 25; "Mirror" on page 27, "Maintaining a Constant Frame Rate" on page 28, "Synchronizing Register Writes to Frame Boundaries" on page 28; "Restart" on page 29, "Automatic Exposure Control" on page 29,and "Test Patterns" on page 32 - Deleted "Pixel Integration Control," "Pixel Clock Speed," "Statistics and Settings Readout," "Read Mode Options," and "Line_Valid" Updated "Electrical Specifications" on page 16 Moved "Power-On Reset and Standby Timing" on page 25 from appendix to main body of document Replaced Figure 13: "Quantum Efficiency - Monochrome Sensor," on page 28 with placeholder Updated Figure 15: "64-Ball iBGA Package Outline Drawing," on page 30 Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/18/09 * Initial release ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN 34 (c)Semiconductor Components Industries, LLC,2015 . Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: MT9M021IA3XTCH-GEVB MT9M021IA3XTMH-GEVB MT9M021IA3XTMZH-GEVB MT9M031I12STCH-GEVB MT9M031I12STMD3-GEVK MT9M031I12STMH-GEVB MT9M031I12STMZD3-GEVK MT9M031I12STMZH-GEVB