General Description
The MAX1889 provides the three regulated output volt-
ages required for active matrix, thin-film transistor liquid
crystal displays (TFT LCDs). It combines a high-perfor-
mance step-up regulator with two linear-regulator con-
trollers and multiple levels of protection circuitry for a
complete power-supply system.
The main DC-DC converter is a high-frequency
(500kHz/1MHz), current-mode step-up regulator with
an integrated N-channel power MOSFET that allows the
use of ultra-small inductors and ceramic capacitors.
With its high closed-loop bandwidth performance, the
MAX1889 provides fast transient response to pulsed
loads while operating with efficiencies over 85%. The
positive and negative linear-regulator controllers post-
regulate charge-pump outputs for TFT gate-on and
gate-off supplies.
The MAX1889 has a unique input switch control that
can replace the typical input fuse by disconnecting the
load from the input supply when a fault is detected.
The fault detector monitors all three regulated output
voltages and can monitor current from the input supply
as well. Additionally, the MAX1889 enters thermal shut-
down when its overtemperature threshold is reached.
The MAX1889 undervoltage lockout is set at 2.5V (max)
to allow the input supply to droop under pulsed load
conditions while avoiding any unexpected behavior
when its input voltage dips momentarily. Also, the built-
in soft-start and cycle-by-cycle current limiting prevent
input surge currents during power-up.
The MAX1889 is available in a 16-pin thin QFN pack-
age with a maximum thickness of 0.8mm for ultra-thin
LCD panel design.
Applications
Notebook Computer Displays
LCD Monitors
Car Navigation Displays
Features
♦High-Performance Step-Up Regulator
Fast Transient Response
Current-Mode Control Architecture
Built-In High-Efficiency N-Channel Power
MOSFET
Current-Limit Comparator
>85% Efficiency
Selectable Switching Frequency
(500kHz/1MHz)
Internal Soft-Start
♦Positive Linear-Regulator Controller
♦Negative Linear-Regulator Controller
♦Triple-Level Protection Against Smoke or Fire
Input Switch Replaces Input Fuse
Output Overload Detection with Timer Latch
Thermal Shutdown
♦2.7V to 5.5V Input Operating Range
♦Ultra-Small External Components
♦1µA Shutdown Current (max)
♦1mA Quiescent Current (max)
♦Ultra-Thin 16-Pin QFN Package
(0.8mm Maximum Thickness)
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
16
1
2
3
4
12
11
10
9
15 14 13
5678
IN
GATE
OCP
OCN
TGND
LX
FREQ
FBP
PGND
GND
REF
FB
FBN
DRVN
DRVP
SHDN
TOP VIEW
MAX1889
THIN QFN
(5mm x 5mm)
Pin Configuration
19-2485; Rev 1; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-PACKAGE
MAX1889ETE
- 40°C to + 85° C
16 Thi n Q FN ( 5m m ✕ 5m m )
MAX1889EGE*
- 40°C to + 85° C
16 QFN ( 5m m ✕ 5m m )
* Future product—Contact factory for availability.
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = 3V, SHDN = IN, CREF = 0.22µF, PGND = GND, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, SHDN, OCN, OCP,
FB, FBP, FBN, FREQ to GND ...............................-0.3V to +6V
PGND to GND.....................................................................±0.3V
LX to PGND ............................................................-0.3V to +14V
DRVP to GND .........................................................-0.3V to +30V
REF, GATE, TGND to GND..........................-0.3V to (VIN + 0.3V)
DRVN to GND .....................................(VIN - 28V) to (VIN + 0.3V)
Continuous Power Dissipation (TA= +70°C)
16-Pin QFN (derate 19.2mW/°C above +70°C) .........1538mW
Operating Temperature Range
MAX1889EGE ..................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
IN Supply Range VIN 2.7 5.5 V
VIN rising
2.55
2.7
2.85
IN Undervoltage Lockout
(UVLO) Threshold
VUVLO
350mV typical
hysteresis VIN falling 2.2
2.35
2.5 V
IN Quiescent Current IIN VFB = VFBP = 1.5V, VFBN = 0V (Note 1) 1.0 mA
IN Shutdown Current V
SHDN = 0, VIN = 5V 0.1 1.0 µA
REF Output Voltage VREF -2µA < IREF < 50µA
1.231 1.250 1.269
V
Thermal Shutdown
160
°C
MAIN STEP-UP REGULATOR
Main Output Voltage Range
VMAIN
VIN 13 V
VFREQ = VIN
0.85
1
1.15
MHz
Operating Frequency fOSC VFREQ = 0V
500
kHz
Oscillator Maximum Duty Cycle 80 85 90 %
FB Regulation Voltage VFB ILX = 200mA, slope = 0 (Note 2)
1.229 1.242 1.254
V
FB Fault Trip Level VFB falling
0.95
1.0
1.05
V
Load Regulation IMAIN = 0 to full load
-1.6
%
Line Regulation VIN = 2.7V to 5.5V 0.2
%/V
FB Input Bias Current IFB VFB = 1.5V
-100 +100
nA
LX Switch On-Resistance
RLX
ON
250 450
mΩ
LX Leakage Current ILX VLX = 13V
0.01
20 µA
LX Current Limit ILIM 1.6 2.1 2.8 A
LX RMS Current Rating Not tested 1.4 A
Soft-Start Period tSS 4096 /
fOSC
s
Soft-Start Step Size
VREF /32
V
POSITIVE LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 0.2mA
1.213 1.25 1.288
V
FBP Fault Trip Level VFBP falling
0.96
1.0
1.04
V
FBP Input Bias Current IFBP VFBP = 1.25V -50
+50
nA
FBP Effective Transconductance
VDRVP = 10V, IDRVP = 0.1mA to 2mA 75 mS
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, SHDN = IN, CREF = 0.22µF, PGND = GND, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FBP Line Regulation IDRVP = 0.2mA, VIN = 2.7V to 5.5V 1 mV
Bandwidth (Note 3)
200
kHz
DRVP Sink Current
IDRVP
VFBP = 1.1V, VDRVP = 10V 5 mA
DRVP Off-Leakage Current VFBP = 1.1V, VDRVP = 28V 0.1 10 µA
NEGATIVE LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 0.2mA 95
125 155
mV
FBN Fault Trip Level VFBN rising
325 400 475
mV
FBN Input Bias Current IFBN VFBN = 0V -50
+50
nA
FBN Effective Transconductance
VDRVN = -10V, IDRVN = 0.1mA to 2mA 75 mS
FBN Line Regulation IDRVN = 0.2mA, VIN = 2.7V to 5.5V 1 mV
Bandwidth (Note 2)
200
kHz
DRVN Sink Current
IDRVN
VFBN = 200mV, VDRVN = -10V 5 mA
DRVN Off-Leakage Current VFBP = -0.1V, VDRVN = -20V 0.1 10 µA
LOGIC SIGNAL (SHDN)
Input Low Voltage
100mV typical hysteresis, VIN = 2.7V to 5.5V
0.4 V
Input High Voltage VIN = 2.7V to 5.5V 1.6 V
Input Current
I
SHDN 0.01
1µA
LOGIC SIGNAL (FREQ)
Input Low Voltage 0.15 x VIN typical hysteresis 0.3 x
VIN V
Input High Voltage 0.7 x
VIN V
Input Current IFREQ
0.01
1µA
OVERCURRENT COMPARATOR
Input Offset Voltage -5 +5 mV
Input Bias Current IOCN,
IOCP VOCN = VOCP = VIN -50
+50
nA
OCN, OCP Input
Common-Mode Range 1.5 0.8 x
VIN V
FAULT TIMER AND GATE DRIVER
VFREQ = 0V, 32768/fOSC 64
Fault Timer Period
tFAULT
VFREQ = VIN, 65536/fOSC 64 ms
GATE Output Sink Current
During Slew IGATE VGATE = 1.5V, during turn-on transition 6 12 18 µA
GATE Output
Pulldown Resistance VGATE < 0.5V
200
Ω
GATE Output Pullup Resistance
200
Ω
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VIN = 3V, SHDN = IN, CREF = 0.22µF, PGND = GND, TA= -40°C to +85°C.) (Note 4)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
IN Supply Range VIN 2.7 5.5 V
VIN rising
2.55 2.85
IN ULVO Threshold
VUVLO
VIN falling 2.2 2.5 V
IN Quiescent Current IIN VFB = VFBP = 1.5V, VFBN = 0V (Note 1) 1.0 mA
IN Shutdown Current V SHDN = 0, VIN = 5V 1.0 µA
REF Output Voltage VREF -2µA < IREF < 50µA
1.231 1.269
V
MAIN STEP-UP REGULATOR
Main Output Voltage Range
VMAIN
VIN 13 V
Operating Frequency fOSC VFREQ = VIN
0.75 1.25
MHz
Oscillator Maximum Duty Cycle 78 92 %
FB Regulation Voltage VFB ILX = 200mA, slope = 0 (Note 2)
1.215 1.260
V
FB Fault Trip Level VFB falling
0.96 1.04
V
Line Regulation VIN = 2.7V to 5.5V
0.45
%/V
FB Input Bias Current IFB VFB = 1.5V
-100 +100
nA
LX Switch On-Resistance
RLX
ON
450
mΩ
LX Current Limit ILIM 1.6 2.8 A
POSITIVE LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage VFBP IDRVP = 0.2mA
1.213 1.288
V
FBP Fault Trip Level VFBP falling
0.96 1.04
V
FBP Input Bias Current IFBP VFBP = 1.25V -50
+50
nA
FBP Effective Transconductance
VDRVP = 10V, IDRVP = 0.1mA to 2mA 60 mS
Bandwidth (Note 2)
200
kHz
DRVP Sink Current
IDRVP
VFBP = 1.1V, VDRVP = 10V 5 mA
NEGATIVE LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage VFBN IDRVN = 0.2mA 95
155
mV
FBN Fault Trip Level VFBN rising
325 475
mV
FBN Input Bias Current IFBN VFBN = 0V -50
+50
nA
FBN Effective Transconductance
VDRVN = -10V, IDRVN = 0.1mA to 2mA 60 mS
Bandwidth (Note 2)
200
kHz
DRVN Sink Current
IDRVN
VFBN = 200mV, VDRVN = -10V 5 mA
LOGIC SIGNAL (SHDN)
Input Low Voltage 100mV typical hysteresis 0.4 V
Input High Voltage 1.6 V
Input Current ISHDN 1µA
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, SHDN = IN, CREF = 0.22µF, PGND = GND, TA= -40°C to +85°C.) (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC SIGNAL (FREQ)
Input Low Voltage 0.15 x VIN typical hysteresis
0.3 x VIN
V
Input High Voltage
0.7 x VIN
V
Input Current IFREQ 1µA
OVERCURRENT COMPARATOR
Input Offset Voltage -5 +5 mV
Input Bias Current IOCN,
IOCP VOCN = VOCP = VIN -50
+50
nA
OCN, OCP Input
Common-Mode Range 1.5 0.8 x
VIN V
FAULT TIMER AND GATE DRIVER
GATE Output Sink Current IGATE VGATE = 1.5V, during turn-on transition 6 18 µA
GATE Output
Pulldown Resistance VGATE < 0.5V
200
Ω
GATE Output Pullup Resistance
200
Ω
Note 1: Quiescent current does not include switching losses.
Note 2: FB regulation voltage is tested with no slope compensation ramp. Slope compensation needs to be included when selecting
resisitors for setting the output voltage (see Main Step-Up Regulator and Output Voltage Selection sections).
Note 3: Guaranteed by design. Not production tested.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA= +25°C, unless
otherwise noted.)
50
1 100010010
STEP-UP REGULATOR EFFICENCY
vs. LOAD CURRENT (VMAIN = 9V)
100
70
60
90
80
MAX1889 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
A
BC
A: VIN = 2.7V
B: VIN = 3.3V
C: VIN = 5.5V
1 10 100 1000
STEP-UP REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT (VMAIN = 9V)
MAX1889 toc02
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
9.1
8.5
8.6
8.7
8.8
8.9
9.0
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
100
50
110
100 1000
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT (VMAIN = 13V)
60
MAX1889 toc03
LOAD CURRENT (mA)
EFFICIENCY (%)
70
80
90
A: VIN = 2.7V
B: VIN = 3.3V
C: VIN = 5.5V
AB
C
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA= +25°C, unless
otherwise noted.)
1 10 100 1000
STEP-UP REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT (VMAIN = 13V)
MAX1889 toc04
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
13.1
12.5
12.6
12.7
12.8
12.9
13.0
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
500
700
600
900
800
1000
1100
STEP-UP REGULATOR SWITCHING
FREQUENCY vs. INPUT VOLTAGE
MAX1889 toc05
INPUT VOLTAGE (V)
FREQUENCY (kHz)
2.5 3.5 4.03.0 4.5 5.0 5.5
VIN = 3.3V
VMAIN = 9V
IMAIN = 200mA
10µs/div
STEP-UP REGULATOR LOAD-TRANSIENT
RESPONSE (0 TO 200mA)
A
B
9V
1A
MAX1889 toc06
C
500mA
0
8.9V
0
200mA
A: INDUCTOR CURRENT, 500mA/div
B: VMAIN = 9V, 100mV/div, AC-COUPLED
C: IMAIN = 0 TO 200mA, 200mA/div
10µs/div
STEP-UP REGULATOR LOAD-TRANSIENT
RESPONSE (0 TO 1A, 2µs PULSE)
A
B
9V
2A
MAX1889 toc07
C
1A
0
8.9V
0
1A
A: INDUCTOR CURRENT, 1A/div
B: VMAIN = 9V, 100mV/div, AC-COUPLED
C: IMAIN = 0 TO 1A, 1A/div
8.8V
1ms/div
STEP-UP REGULATOR SOFT-START
(10mA LOAD) FROM
SLOW-RISING INPUT SUPPLY
A
B
5V
5V
MAX1889 toc08
C
0
5V
0
0
5V
A: VIN, 5V/div
B: VGATE, 5V/div
C: VC2, 5V/div
D: VMAIN = 9V, 5V/div
10V
D
0
1ms/div
STEP-UP REGULATOR SOFT-START
(200mA LOAD) FROM
SLOW-RISING INPUT SUPPLY
A
B
5V
5V
MAX1889 toc09
C
0
5V
0
0
5V
A: VIN, 5V/div
B: VGATE, 5V/div
C: VC2, 5V/div
D: VMAIN = 9V, 5V/div
10V
D
0
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA= +25°C, unless
otherwise noted.)
2ms/div
POWER-UP SEQUENCE FROM
SLOW-RISING INPUT SUPPLY
A
B
20V
5V
MAX1889 toc10
C
0
5V
10V
-10V
0
A: VIN, 5V/div
B: VMAIN = 9V, 5V/div
C: VPL = 20V, 10V/div
D: VNL = -7V, 10V/div
0
D
0
1ms/div
STEP-UP REGULATOR SOFT-START
(10mA LOAD) USING SHDN CONTROL
A
B
5V
5V
MAX1889 toc11
C
0
5V
0
0
5V
A: VSHDN, 5V/div
B: VGATE, 5V/div
C: VC2, 5V/div
D: VMAIN = 9V, 5V/div
10V
D
0
1ms/div
STEP-UP REGULATOR SOFT-START
(200mA LOAD) USING SHDN CONTROL
A
B
5V
5V
MAX1889 toc12
C
0
5V
0
0
5V
A: VSHDN, 5V/div
B: VGATE, 5V/div
C: VC2, 5V/div
D: VMAIN = 9V, 5V/div
10V
D
0
2ms/div
POWER-UP SEQUENCE
USING SHDN CONTROL
A
B
20V
5V
MAX1889 toc13
C
0
5V
10V
-10V
0
A: VSHDN, 5V/div
B: VMAIN = 9V, 5V/div
C: VPL = 20V, 10V/div
D: VNL = -7V, 10V/div
0
D
0
1µs/div
STEP-UP REGULATOR NORMAL OPERATION
(200mA LOAD)
A
B
9.05V
MAX1889 toc14
C
10V
5V
9V
500mA
A: VLX, 5V/div
B: VMAIN = 9V, 50mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 500mA/div
1A
0
0
0.1 110
POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1889 toc15
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
26.2
25.0
25.2
25.4
25.6
25.8
26.0
VIN = 3.3V
IMAIN = 200mA
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA= +25°C, unless
otherwise noted.)
100
50
0.1 1 10
POSITIVE CHARGE-PUMP INCREMENTAL
EFFICIENCY vs. LOAD CURRENT
60
55
MAX1889 toc16
LOAD CURRENT (mA)
EFFICIENCY (%)
70
65
80
85
75
90
95
EFF = (VOUT ✕ IOUT) /
(PIN(LOAD) - PIN(NOLOAD))
-8.2
-8.7
0.1 1 10
NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. LOAD CURRENT
-8.6
MAX1889 toc17
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
-8.5
-8.4
-8.3
VIN = 3.3V
IMAIN = 200mA
100
50
0.1 1 10
NEGATIVE CHARGE-PUMP INCREMENTAL
EFFICIENCY vs. LOAD CURRENT
60
55
MAX1889 toc18
LOAD CURRENT (mA)
EFFICIENCY (%)
70
65
80
85
75
90
95
EFF = (VOUT ✕ IOUT) /
(PIN(LOAD) - PIN(NOLOAD))
-0.15
-0.12
-0.09
-0.06
-0.03
0
0.1 1 10
POSITIVE LINEAR-REGULATOR
LOAD REGULATION
MAX1889 toc19
LOAD CURRENT (mA)
OUTPUT VOLTAGE VARIATION (%)
2ms/div
POSITIVE LINEAR-REGULATOR
LOAD-TRANSIENT RESPONSE
A
B
19.95V
MAX1889 toc20
10mA
0
A: VPL = 20V, 50mV/div, AC-COUPLED
B: IPL = 0 TO 10mA, 10mA/div
20V
-0.40
-0.32
-0.16
-0.24
0
0.1 1 10
NEGATIVE LINEAR-REGULATOR
LOAD REGULATION
MAX1889 toc21
LOAD CURRENT (mA)
OUTPUT VOLTAGE VARIATION (%)
-0.08
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA= +25°C, unless
otherwise noted.)
400µs/div
NEGATIVE LINEAR-REGULATOR
LOAD-TRANSIENT RESPONSE
A
B
MAX1889 toc22
-10mA
0
A: VNL = -7V, 50mV/div, AC-COUPLED
B: INL = 0 TO -10mA, 10mA/div
-6.95V
-7V
20ms/div
OVERCURRENT PROTECTION RESPONSE
TO OVERLOAD DURING STARTUP
B
D
10V
MAX1889 toc23
-10V
0
A: VGATE, 5V/div
B: VMAIN, 5V/div; IMAIN = 1.5A
C: VPL, 10V/div; IPL = 10mA
D: VNL, 10V/div; INL = 10mA
5V
0
A
C
5V
0
0
1.245
1.246
1.247
1.248
1.249
1.250
0405020 3010 60 70 80 90 100
REFERENCE VOLTAGE vs. LOAD CURRENT
MAX1889 toc25
LOAD CURRENT (µA)
REFERENCE VOLTAGE (V)
2.4
2.3
2.2
2.1
2.0
2.5 4.03.0 3.5 4.5 5.0 5.5
LX CURRENT LIMIT vs. INPUT VOLTAGE
MAX1889 toc26
INPUT VOLTAGE (V)
CURRENT LIMIT (A)
20ms/div
OVERCURRENT PROTECTION RESPONSE
TO OVERLOAD DURING NORMAL OPERATION
B
D
10V
MAX1889 toc24
-10V
0
A: VGATE, 5V/div
B: VMAIN = 9V, 5V/div; IMAIN = 200mA TO 1.5A
C: VPL = 20V, 10V/div; IPL = 10mA
D: VNL = -7V, 10V/div; INL = 10mA
5V
0
A
C
5V
0
0
20V
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1SHDN
Active-Low Shutdown Control Input. Pull SHDN below the 0.4V logic-low level to turn off all sections
of the device and pull the GATE pin high. Pull SHDN above the 1.6V logic-high level to enable the
device. Do not leave SHDN floating.
2 PGND Power Ground. PGND is the source of the N-channel power MOSFET. Connect PGND to the analog
ground (GND) at the device’s pins.
3 GND Analog Ground. Connect GND to the power ground (PGND) at the device’s pins.
4 REF Internal Reference Bypass Terminal. Connect a 0.22µF ceramic capacitor from REF to the analog
ground (GND). External load capability is at least 50µA.
5FB
Main Step-Up Regulator Feedback Input. FB regulates to 1.25V nominal. Connect FB to the center of
a resistive voltage-divider between the main output (VMAIN) and the analog ground (GND) to set the
main step-up regulator output voltage. Place the resistive voltage-divider close to the pin.
6 FBN
Negative Linear-Regulator Feedback Input. FBN regulates to 125mV nominal. Connect FBN to the
center of a resistive voltage-divider between the negative output (VNEG) and the REF to set the
negative linear-regulator output voltage. Place the resistive voltage-divider close to the pin.
7 DRVN
Negative Linear-Regulator Base Drive. Open drain of an internal P-channel MOSFET. Connect DRVN
to the base of the external linear-regulator NPN pass transistor (see Pass Transistor Selection
section).
8 DRVP
Positive Linear-Regulator Base Drive. Open drain of an internal N-channel MOSFET. Connect DRVP
to the base of the external linear-regulator PNP pass transistor (see Pass Transistor Selection
section).
9 FBP
Positive Linear-Regulator Feedback Input. FBP regulates to 1.25V nominal. Connect FBP to the
center of a resistive voltage-divider between the positive output (VPOS) and the analog ground (GND)
to set the positive linear-regulator output voltage. Place the resistive voltage-divider close to the pin.
10 FREQ
Frequency Select Input. Pull FREQ above logic-high level (0.7 × VIN) to set the frequency to 1MHz
and pull FREQ below logic-low level (0.3 × VIN) to set the frequency to 500kHz. Do not leave FREQ
floating.
11 LX Switching Node. Drain of the internal N-channel power MOSFET for the main step-up regulator.
12 TGND Internal connection. Connect this pin to ground.
13 OCN
Overcurrent Comparator Inverting Input. OCN connects to the center tap of a resistive voltage-
divider connected to the drain of the input protection P-channel MOSFET (see the Input Overcurrent
Protection section). If unused, connect OCN to REF.
14 OCP
Overcurrent Comparator Noninverting Input. OCP is connected to the center tap of a resistive
voltage-divider that sets the input overcurrent threshold (see the Input Overcurrent Protection
section). If unused, connect OCP to GND.
15 GATE Gate Driver Output to the External P-Channel MOSFET (see the Input Overcurrent Protection section).
If unused, leave GATE open.
16 IN
Supply Input. The supply voltage powers all the control circuitry. The input voltage range is from 2.7V
to 5.5V. Bypass with a 0.1µF ceramic capacitor between IN and GND, as close to the pins as
possible.
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 11
MAX1889
VIN
2.7V TO 5.5V P1
L1
4.7µH
LX
D1
C2
3.3µF
6.3V
C3
3.3µF
6.3V
C4
4.7µF
10V
C5
4.7µF
10V
C6
4.7µF
10V
R1
10Ω
R2
51.1kΩ
1%
R4
1MΩ
R5
1MΩ
VMAIN
9V
C1
0.47µF
R3
150kΩ
1%
R6
75kΩ
1%
R7
12.1kΩ
1%
REF
C7
0.22µF
LX
C8
0.1µF
D2
C9
0.15µF
C10
1µF
R8
3kΩ
R9
150kΩ
1%
R10
24.3kΩ
1%
R14
221kΩ
Q1
VNL
-7V
REF
VMAIN
LX
C11
0.1µF
C12
0.1µF
D3 D4
C13
0.15µF
C15
1µF
C14
0.1µF
R11
3kΩ
R12
301kΩ
1%
R13
20kΩ
1%
Q2
VPL
+20V
OPTIONAL
ANALOG GROUND
(GND)
POWER GROUND
(PGND)
OPTIONAL
EXTERNAL LOGIC SIGNAL
(ENABLE = LOW)
EXTERNAL LOGIC SIGNAL
(ENABLE = LOW)
15
14
16
1
10
7
6
GATE
OCP
IN
FREQ
DRVN
FBN
SHDN
13 11
OCN LX
5
FB
12
TGND
4
REF
3
GND
2
PGND
8
DRVP
9
FBP
C22
1000pF
R20
51kΩ
C20
470pF
C21
1000pF
C16
0.01µF
C17
220pF
R18
10kΩ
R17
1MΩ
C23
100pF
R15
43.2kΩ
1%
R16
150kΩ
1%
R19
15kΩ
C24
2200pF
C19
1000pF
Figure 1. Standard Application Circuit
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
12 ______________________________________________________________________________________
MAX1889
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
REFERENCE
1.25V
EN
REF
REF
REFOK
SHDN FREQ IN
2.70V
2.35V
UVLO
COMPARATOR
SEQUENCE
AND FAULT
DETECTOR
THERMAL
SHUTDOWN
ONP ONMN
GATE
DRIVER
EN GATE
OCN
OCP
LX
FB
PGND
DRVP
FBP
DRVN
FBN
VIN
OVERCURRENT
COMPARATOR
OSCILLATOR
EN
OSC SLOPE_COMP
MAIN STEP-UP
WITH SOFT-START
SSDONE
FAULTM
EN
VPL
VMAIN
VNL
ANALOG
GAIN BLOCK
ANALOG
GAIN BLOCK
FAULT
COMPARATOR
FAULT
COMPARATOR
0.125V
0.35V
REF
Figure 2. MAX1889 System Functional Diagram
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 13
Standard Application Circuit
The standard application circuit (Figure 1) of the
MAX1889 generates +9V, +20V, and -7V outputs for
TFT LCD displays. The input voltage is from 2.7V to
5.5V. Table 1 lists the recommended component
options and Table 2 lists the component suppliers.
Detailed Description
The MAX1889 contains a high-performance, step-up
switching regulator, two low-cost linear-regulator con-
trollers, and multiple levels of protection circuitry. Figure
2 shows the system functional diagram of the device.
The output voltage of the main step-up converter (VMAIN)
can be set from VIN to 13V with an external resistive volt-
age-divider. The high switching frequency (500kH/1MHz)
of the main step-up converter and current-mode control
provide fast transient response and allow the use of low-
profile inductors and ceramic capacitors. The internal
power MOSFET minimizes the external component count
while achieving high efficiency by incorporating a loss-
less current-sensing technology.
The switching node (LX) can generate both positive
and negative voltage supplies by driving charge-pump
stages of capacitors and diodes. The user can use as
many charge-pump stages as needed to generate sup-
ply voltages of more than +30V and -15V. The positive
and negative linear-regulator controllers postregulate
the charge-pump supply voltages and allow users to
program power-up sequencing as well.
The unique input switch control of the MAX1889 senses
the current drawn from the input power supply by moni-
toring the voltage drop across the input P-channel
MOSFET and latches off if an overcurrent condition
lasts for more than the fault timer period. In addition, all
three outputs are monitored for fault conditions that last
longer than the fault latch timer. If the junction tempera-
ture of the IC exceeds +160°C, the device goes into a
latched shutdown state.
Main Step-Up Regulator
The main step-up regulator switches at 1MHz (or 500kHz)
and employs a current-mode control architecture to
maximize loop bandwidth to provide fast-transient
response to pulsed loads found in source drivers for TFT
LCD panels. Also, the high switching frequency allows
the use of low-profile inductors and capacitors to
minimize the thickness of LCD panel designs. The
integrated high-efficiency MOSFET and the IC’s built-in
soft-start function reduce the number of external com-
ponents required while controlling inrush current.
DESIGNATION
DESCRIPTION
C2, C3
3.3µF, 6.3V X5R ceramic capacitors (0805)
Taiyo Yuden JMK212BJ335MG
C4, C5, C6 4.7µF, 10V X7R ceramic capacitors (1210)
Taiyo Yuden LMK352BJ475MF
D1 1.0A, 30V Schottky diode (S-flat)
Toshiba CRS02
D2, D3, D4
200mA, 25V dual-series Schottky diodes
(SOT23)
Fairchild BAT54S
D5 250mA, 75V switching diode (SOT23)
Central Semiconductor CMPD914
L1 6.8µH, 1.3A inductor
Coilcraft LPO2506IB-682
P1
2.4A, 20V P-channel MOSFET
(3-pin SuperSOT)
Fairchild FDN304P
Q1
200mA, 40V NPN bipolar transistor (SOT23)
Fairchild MMBT3904
Q2
200mA, 40V PNP bipolar transistor (SOT23)
Fairchild MMBT3906
Table 1. Component List
SUPPLIER PHONE FAX WEBSITE
Coilcraft 847-639-6400 847-639-1469 www.coilcraft.com
Fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com
Taiyo Yuden 800-348-2496 847-925-0899 www.t-yuden.com
Toshiba 949-455-2000 949-859-3963 www.toshiba.com
Table 2. Component Suppliers
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
14 ______________________________________________________________________________________
Depending on the input-to-output voltage ratio, the reg-
ulator controls the output voltage and the power deliv-
ered to the output by modulating the duty cycle (D) of
the power MOSFET in each switching cycle. The duty
cycle of the MOSFET is approximated by:
On the rising edge of the internal clock, the controller
sets a flip-flop, which turns on the N-channel MOSFET
(Figure 3). The input voltage is applied across the
inductor. The inductor current ramps up linearly, storing
energy in a magnetic field. Once the sum of the feed-
back voltage error-amplifier output, slope-compensa-
tion, and current-feedback signals trip the multi-input
PWM comparator, the MOSFET turns off, and the flip-
flop resets. Since the inductor current is continuous, a
transverse potential develops across the inductor that
turns on the diode (D1). The voltage across the inductor
becomes the difference between the output voltage and
the input voltage. This discharge condition forces the
current through the inductor to ramp back down, trans-
ferring the energy to the output capacitor and the load.
The MOSFET remains off for the rest of the clock cycle.
DVV
V
MAIN IN
MAIN
≈-
+
-
+
-
+
-
+
-
+
-
ILIM
CURRENT
SENSE
OSC
ILIM
COMPARATOR
RESET DOMINANT
+
-
+
-
Σ
S
RQ
SSDONE
SOFT-START
REFOUT
SSOK
REFIN
CLK
ONMN
REF
FB
SLOPE_COMP
PGND
LX
FAULT M
EN
MAX1889
Figure 3. Main Step-Up Regulator Functional Diagram
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 15
Positive Linear-Regulator Controller
The positive linear regulator provides the positive high
voltage for the TFT LCD gate drivers. The high voltage
can be produced using a charge-pump circuit as shown
in Figure 1. Use as many stages as necessary to obtain
the required output voltage (see the Selecting the
Number of Charge-Pump Stages section). The positive
linear-regulator controller is an analog gain block with an
open-drain N-channel output. It drives an external PNP
pass transistor with a 3kΩbase-to-emitter resistor to
post-regulate the charge-pump output (Figure 1). The
regulator controller is designed to be stable with an out-
put capacitor of 0.1µF or more.
To enable the regulator using an external control signal,
apply the logic-control input in series with a signal
diode (Figure 1). Additional delay can be added with
external circuitry.
Note that the voltage rating of the DRVP output is 28V.
If higher voltages are present, an external cascode
NPN transistor should be used with the emitter con-
nected to DRVP, the base to VMAIN, and the collector to
the base of the PNP.
Negative Linear-Regulator Controller
The negative linear regulator provides the negative volt-
age required to supply gate drivers in TFT LCD panels.
The negative voltage can be produced using a charge
pump circuit as shown in Figure 1. Use as many stages
as necessary to obtain the required output voltage (see
the Selecting the Number of Charge-Pump Stages sec-
tion). The negative linear-regulator controller is an ana-
log gain block with an open-drain P-channel output. It
drives an external NPN pass transistor with a 3kΩbase-
to-emitter resistor to postregulate the charge-pump out-
put (Figure 1). The regulator controller is designed to
be stable with an output capacitor of 0.1µF or more.
The negative linear regulator is enabled as soon as the
main step-up regulator is enabled. To enable the regula-
tor using an external control signal, apply the logic-control
input through an open-drain output or an N-channel MOS-
FET (Figure 1). Additional delay can be added with exter-
nal circuitry (see the Applications Information section).
Note that the voltage rating of the DRVN output is
VIN - 28V. If higher voltages are present, an external
cascode PNP transistor should be used with the emitter
connected to DRVN, the base to GND, and the collec-
tor to the base of the NPN.
Undervoltage Lockout (UVLO)
The UVLO comparator of the MAX1889 compares the
input voltage at the IN pin with the UVLO threshold (2.7V
rising, 2.35V falling, typ) to ensure that the input voltage is
high enough for reliable operation. The 350mV (typ) hys-
teresis prevents supply transients from causing a restart.
Once the input voltage exceeds the UVLO threshold, the
controller enables the reference block. Once the refer-
ence is above 1.05V, an internal 12µA current source
pulls the GATE pin low and turns on an external P-chan-
nel MOSFET switch (P1, Figure 1) that connects the input
supply to the regulator. When the input voltage falls below
the UVLO threshold, the controller sets the fault latch and
pulls GATE high with an internal 100Ωswitch to turn off
P1 quickly (Figure 4).
Reference Voltage (REF)
The reference output is nominally 1.25V, and can
source at least 50µA (see the Typical Operating
Characteristics). Bypass REF with a 0.22µF ceramic
capacitor connected between REF and GND.
Oscillator Frequency (FREQ)
The internal oscillator frequency is pin programmable.
Connect FREQ to ground for 500kHz operation and to VIN
for 1MHz operation. Note that the soft-start period scales
with the oscillator frequency (see the Soft-Start section).
Shutdown (
SHDN
)
A logic-low signal on the SHDN pin disables all device
functions including the reference. When shut down, the
supply current drops to 0.1µA (typ) to maximize battery
life. The output capacitance, feedback resistors, and load
current determine the rate at which each output voltage
decays. A logic-high signal on the SHDN pin activates the
MAX1889 (see the Power-Up Sequencing section). Do not
leave the pin floating. If unused, connect SHDN to IN.
Toggling SHDN or cycling IN clears the fault latch.
+
-
+
-
0.625V
12µA
GATE
IN
EN
L
CIN
Figure 4. External Input P-Channel MOSFET Switch Control
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
16 ______________________________________________________________________________________
Power-Up Sequencing and
Inrush Current Control
Once SHDN is high, the MAX1889 enables the UVLO
circuitry and compares the input voltage with the UVLO
rising threshold (2.7V, typ). If the input voltage exceeds
the UVLO rising threshold, the reference is enabled.
When the reference voltage ramps up above 1.05V
(typ), the MAX1889 enables the oscillator and turns on
the external P-channel MOSFET P1 (Figure 1) by
pulling GATE low. GATE is pulled down with a 12µA
current source. Add a capacitor from the gate of P1 to
its drain to slow down the turn-on rate of the MOSFET,
and reduce inrush current. Once GATE reaches around
0.6V, an internal N-channel MOSFET turns on and pulls
GATE to ground in order to maximize the enhancement
of the external P-channel MOSFET. As P1 fully turns on,
the main step-up regulator powers up with soft-start
(see the Soft-Start section). The negative linear regula-
tor is enabled at the same time as the main step-up
regulator. The positive linear regulator is enabled after
the soft-start routine is completed. The fault detection
timer begins after the main step-up regulator has fin-
ished its soft-start period.
Soft-Start
The soft-start of the main step-up regulator (Figure 3) is
achieved by ramping up the reference voltage of the
multi-input PWM comparator in 4096 oscillator clock
cycles. The 4096 clock cycles correspond to 4.096ms
for 1MHz operation and 8.192ms for 500kHz operation.
The reference of the PWM comparator comes from a
5-bit DAC that generates 32 steps when the reference
ramps up from 0V to its final value. This soft-start
method allows a gradual increase of the output voltage
to reduce the input surge current (see the startup
waveforms in the Typical Operating Characteristics).
The average input current is given as:
where VMAIN is the main step-up regulator output volt-
age, VIN is the input voltage, COUT is the main step-up
regulator output capacitor, ηis the efficiency of the
step-up regulator, and tSS is the soft-start period
(4.096ms for 1MHz operation and 8.192ms for 500kHz
operation).
Input Overcurrent Protection
The high-side overcurrent comparator of the MAX1889
provides input overcurrent protection when it is used
together with the external P-channel MOSFET switch P1
(Figure 1). Connect resistive voltage-dividers from the
source and drain of P1 to GND to set the overcurrent
threshold. The center taps of the dividers are connected
to the overcurrent comparator inputs (OCN and OCP)
See the Setting the Input Overcurrent Threshold section
for information on calculating resistor values. An overcur-
rent event activates the fault-protection circuitry.
Fault Protection
Once the soft-start routine is completed, if the output of
the main regulator or either linear regulator is below its
respective fault-detection threshold, or the input overcur-
rent comparator pulls high, the MAX1889 activates the
fault timer. If the fault condition still exists after the 64ms
fault-timer duration, the MAX1889 sets the fault latch,
which shuts down all the outputs except the reference,
which remains active. After removing the fault condition,
toggle SHDN (below 0.4V) or cycle the input voltage
(below 2.2V) to clear the fault latch and reactivate the
device.
Thermal Shutdown
The thermal shutdown feature limits total power dissipa-
tion in the MAX1889. When the junction temperature
(TJ) exceeds +160°C, a thermal sensor sets the fault
latch (Figure 2), which shuts down all the outputs
except the reference, allowing the device to cool down.
Once the device cools down by 15°C, toggle SHDN
(below 0.4V) or cycle the input voltage (below 2.2V) to
clear the fault latch and reactivate the device.
Design Procedure
Main Step-Up Regulator
Output Voltage Selection
Adjust the output voltage by connecting a resistive volt-
age-divider from the output (VMAIN) to GND with the
center tap connected to FB (Figure 1). Select R7 in the
10kΩto 50kΩrange. Calculate R6 with the following
equations:
where
For example, at VIN = 3V, VMAIN = 9V, D ≈0.66, and VFB
= 1.229V.
VMAIN can range from VIN to 13V.
RRV V
MAIN FB
67 1=
[]
(/)-
IVC
Vt
IN AVG MAIN OUT
IN SS
_=×
××
2
η
V V D mV and D VV
V
FB MAIN IN
MAIN
=−× ≈
−
1 242 20.( )
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 17
Inductor Selection
The minimum inductance value, peak current rating,
series resistance, and size are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient response time, and output voltage ripple. For
most applications, values between 3.3µH and 20µH
work best with the MAX1889’s switching frequencies.
The maximum load current, input voltage, output volt-
age, and switching frequency determine the inductor
value. For a given load current, higher inductor value
results in lower peak current and, thus, less output rip-
ple, but degrades the transient response and possibly
increases the size of the inductor. The equations pro-
vided here include a constant defined as LIR, which is
the ratio of the peak-to-peak inductor current ripple to
the average DC inductor current. For a good compro-
mise between the size of the inductor, power loss, and
output voltage ripple, select an LIR of 0.3 to 0.5. The
inductance value is then given by:
where ηis the efficiency, fOSC is the oscillator frequency
(see the Electrical Characteristics), and IMAIN includes
the primary load current and the input supply currents
for the charge pumps. Considering the typical applica-
tion circuit, the maximum average DC load current
(IMAIN(MAX)) is 200mA with a 9V output. Based on the
above equations, and assuming 85% efficiency and a
switching frequency of 1MHz, the inductance value is
9.4µH for an LIR of 0.3. The inductance value is 5.6µH
for an LIR of 0.5. The inductance in the standard appli-
cation circuit is chosen to be 6.8µH.
The inductor’s peak current rating should be higher than
the peak inductor current throughout the normal operat-
ing range. The peak inductor current is given by:
Under fault conditions, the inductor current can reach the
internal LX current limit (see the Electrical Characteristics).
However, soft saturation inductors and the controller’s fast
current-limit circuitry protect the device from failure during
such a fault condition.
The inductor’s DC resistance can significantly affect
efficiency due to conduction losses in the inductor.
The power loss due to the inductor’s series resistance
(PLR) can be approximated by the following equation:
where IL(AVG) is the average inductor current and RLis
the inductor’s series resistance. For best performance,
select inductors with resistance less than the internal
N-channel MOSFET’s on-resistance (0.25Ωtyp). To
minimize radiated noise in sensitive applications, use a
shielded inductor.
Output Capacitor
The output capacitor affects the circuit stability and out-
put voltage ripple. A 10µF ceramic capacitor works well
in most applications. Depending on the output capaci-
tor chosen, feedback compensation may be required
or desirable to increase the loop-phase margin or
increase the loop bandwidth for transient response
(see the Feedback Compensation section).
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohm ripple due to
the capacitor’s equivalent series resistance (ESR):
where IPEAK is the peak inductor current (see the Inductor
Selection section). For ceramic capacitors, the output volt-
age ripple is typically dominated by VRIPPLE(C). The volt-
age rating and temperature characteristics of the output
capacitor must also be considered.
Step-Up Regulator Compensation
The loop stability of a current-mode step-up regulator
can be analyzed using a small-signal model. In continu-
ous conduction mode (CCM), the loop-gain transfer
function consists of a dominant pole, a high-frequency
pole, a right-half-plane (RHP) zero, and an ESR zero. In
the case of ceramic output capacitors, the ESR zero is at
a very high frequency.
VV V
V I R and
VI
C
VV
Vf
RIPPLE RIPPLE ESR RIPPLE C
RIPPLE ESR PEAK ESR COUT
RIPPLE C MAIN
OUT
MAIN IN
MAIN OSC
=+
≈
≈
() ()
() ( ),
()
-
PI R IV
VR
LR LAVG L MAIN MAIN
IN L
=≅
×
()
2
2
IIV
V
LIR
PEAK MAIN MAX MAIN
IN MIN
=
+
()
()
12
1
η
LV
V
VV
I f LIR
IN TYP
MAIN
MAIN IN TYP
MAIN MAX OSC
=
() ()
()
2
1
-η
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
18 ______________________________________________________________________________________
Therefore, the dominant pole and the RHP zero deter-
mine the loop response of the step-up regulator. The fre-
quency of the dominant pole is:
where RLis the load resistance and C is the output
capacitor. The frequency of the RHP zero is:
where D is the duty cycle, L is the inductance, and the
DC gain is given by:
where RCS is the internal current-sense resistor, and R1
and R2 are the feedback divider resistors in Figure 5.
However, adding lead or lag compensation (Figure 5)
can be useful to adjust the trade-off between stability
and transient response. If greater phase margin is need-
ed for stability, and lower bandwidth is acceptable, add
a pole-zero pair by connecting an RC network from the
FB pin to ground (lag compensation). Conversely, if
higher bandwidth is required for faster transient
response, and lower phase margin is acceptable, add a
zero-pole pair to the loop by connecting an RC network
from the FB pin to the main output (lead compensation).
The frequencies of the pole and zero for the lag com-
pensation are:
The frequencies of the zero and pole for the lead com-
pensation are:
The compensation resistors R3 and R4 change the AC
gain affecting the loop bandwidth and phase margin at
crossover. Reducing the bandwidth too much (FB com-
pensation) harms the transient response, while increas-
ing it too much harms phase margin and stability. As a
rule, start with R3 (or R4) approximately equal to half of
R1 (or R2). In a typical application, the compensation
capacitors C1 and C2 can be in the range between
100pF to 1000pF. Then, check the stability by monitoring
the transient response waveform when a pulsed load is
applied to the output.
Using Compensation for Improved Soft-Start
The digital soft-start of the main step-up regulator limits
the average input current during startup. In order to
smooth out each step of the digital soft-start, add a low-
frequency lead compensation network (Figure 5). The
network effectively spreads out the switching pulses
and lowers the peak inductor currents.
The smoothing network is active only during soft-start
when the output voltage rises. Positive changes in the
output are instantaneously coupled to the FB pin
through D1 and feed-forward capacitor C2. This
arrangement generates a smoothly rising output volt-
age. When the output voltage reaches regulation, C2
charges up through R3 and D1 turns off. In most appli-
cations, the lead compensation is not needed and can
be disabled by making R3 large. With R3 > R2, the
pole and the zero in the compensation network are very
close to one another and cancel out.
f
RR C
f
RRR
RR
C
ZFF
PFF
_
_
=+
()
×
=
+×
+
1
223 2
1
2312
12
2
π
π
f
RRR
RR
C
f
RC
PFB
ZFB
_
_
=×
+
=×
1
24
12
12
1
1
24 1
π
π
AR
RR
D
RR
DC
CS
L
=+×−×
20 1
12
1
log ()
fD
R
L
Z RHP L
_=
()
12
2
-π
fRC
P DOMINANT
L
_=1
2π
MAX1889
VIN
LD
VMAIN
RL
C
C2
C1
R1
R2
R3
R4
LX
FB
GND
PGND
D1
Figure 5. External Compensation
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 19
Input Capacitor
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injection
into the device. Two 3.3µF ceramic capacitors are used
in the standard application circuit (Figure 1) because of
the high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator typically runs
directly from the output of another regulated supply.
Typically, CIN can be reduced below the values used in
the standard applications circuit. Ensure a low noise sup-
ply at the IN pin by using adequate CIN. Alternatively,
greater voltage variation can be tolerated on CIN if IN is
decoupled from CIN using an RC lowpass filter (see R1,
C1 in Figure 1).
Rectifier Diode
The MAX1889’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 1A Schottky
diode complements the internal MOSFET well.
Input P-Channel MOSFET
Select the input P-channel MOSFET based on the cur-
rent rating, voltage rating, gate threshold, and on-resis-
tance. The MOSFET must be able to handle the peak
input current (see the Inductor Selection section). The
drain-to-source voltage rating of the input MOSFET
should be higher than the maximum input voltage.
Because the MOSFET conducts the full input current,
the on-resistance should be low enough for higher effi-
ciency. Use a low-threshold MOSFET to ensure that the
switch is fully enhanced at lowest input voltages.
Setting the Input Overcurrent Threshold
The high-side comparator of the MAX1889 provides
input overcurrent protection when used in conjunction
with an external P-channel MOSFET P1. The accuracy
of the overcurrent threshold is affected by many fac-
tors, including comparator offset, resistor tolerance,
input voltage range, and variations in MOSFET
RDS(ON). The input overcurrent comparator is only
intended to protect against catastrophic failures. This
function is similar to an input fuse.
To minimize the impact of the comparator’s input offset
on the current-sense accuracy, the sense voltage
should be close to the upper limit of the common-mode
range, which extends up to 80% of the input voltage.
The resistive voltage-divider (R3/R4), combined with
the on-state resistance of P1, sets the overcurrent
threshold. The center of R3/R4 is connected to the
inverting input (OCN) as shown in Figure 6.
If the comparator and resistors are ideal, the threshold
is at the current where both inputs are equal:
IL(MAX) is the average inductor current at maximum load
condition and minimum input voltage, and given by:
where ηis the efficiency of the main step-up regulator.
If the step-up regulator’s minimum input voltage is 2.7V,
output voltage is 9V and maximum load current is 0.3A.
Assuming 80% efficiency, the maximum average induc-
tor current is:
RDS(MAX) is the maximum on-state drain-to-source
resistance of P1. The maximum RDS(ON) at +25°C can
be found in the MOSFET data sheet, but that number
does not include the temperature coefficient.
Since the temperature coefficient for the resistance is
0.5%/°C, RDS(MAX) can be calculated with the following
equation:
where TJis the actual MOSFET junction temperature in
normal operation due to ambient temperature rise and
self-heating caused by power dissipation. As an exam-
ple, consider Fairchild FDN304P, which has a maxi-
mum RDS(ON) at room temperature of 70mΩ.
RR T
DS MAX DS C J() _ .=×+×
()
[]
°25 1 0 005 25-
IV
V
AA
L MAX()..
..=××=
9
08 27
03 125
IV
V
I
L MAX OUT
IN MIN
LOAD MAX()
()
()
=××
η
VR
RR VI R R
RR
IN IN L MAX DS MAX
×+=×
()
×+
2
12
4
34
-() ()
VIN
RDS(ON)
R1
R2
R3
R4
OCP
OCN
OC COMP
Figure 6. Setting the Overcurrent Threshold
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
20 ______________________________________________________________________________________
If the junction temperature is +100°C, the maximum on-
state resistance overtemperature is:
For given R1 and R2 values, the ideal ratio of R3/R4
can be determined:
To consider the effect of resistor tolerance, comparator
offset, and input voltage variation, the minimum threshold
equation is:
where VIN(MIN) is the minimum expected value of the
input voltage, εis the tolerance of the resistors and the
5mV is the worst-case input offset voltage of the com-
parator. To simplify the equation, define a constant k as
follows:
The minimum threshold equation becomes:
Solving for R3/R4 yields:
The R3/R4 ratio guarantees the required minimum level
for IL(MAX). The typical overcurrent threshold is given by:
The following example shows how to apply the above
equations in the design. If 1% resistors are used, then
ε= 0.01. To set VOCP to be around 75% of VIN, select
R1 = 51.1kΩand R2 = 150kΩ. Assume that the mini-
mum input voltage is 2.7V and the typical input voltage
is 3.3V, the average inductor current at maximum load
is 1.25A, and the maximum RDS(ON) of P1 is 100mΩ:
If R4 =150kΩ, then R3 = 39.2kΩ. The typical overcurrent
threshold is:
Charge Pumps
Selecting the Number of
Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meets the output
requirement.
The number of positive charge-pump stages is given by:
where NPOS is the number of positive charge-pump
stages, VPL is the positive linear-regulator output,
VMAIN is the main step-up regulator output, VDis the
forward voltage drop of the charge-pump diode, and
VDROPOUT is the dropout margin for the linear regula-
tor. Use VDROPOUT = 2V.
NVV V
VV
POS PL DROPOUT MAIN
MAIN D
=+
×
-
-2
IVkkk
kkk
A
TH TYP_
.
.
.
.
.
=× ×+
()
×+
()
=
33
0 047 1150 39 2 150
150 51 1 150
415
Ω
ΩΩΩ
ΩΩΩ
-
k
R
R
VA
Vk
kk
V
=+=
=× ×
×+×+
=
1001
1001 0 9802
3
40 9802 27 125 01
27 150
150 0 9802 51 1 0 005
1
0 2637
-
--
.
..
... .
...
.
.
Ω
Ω
ΩΩ
IV
R
RRR
RRR
TH TYP IN TYP
DS TYP
_()
()
=×
×+
()
×+
()
1234
412
-
R
RkVI R
VR
RkR mV
IN MIN L MAX DS MAX
IN MIN
3
42
21
5
1=× ×
×+× +
()() ()
()
--
VR
kR R mV
VI R kR
RkR
IN MIN
IN MIN L MAX DS MAX
()
()() ()
××+ +=
×
()
××
+×
2
12
5
4
34
-
k=+
1
1
-ε
ε
VR
RR mV
VI R R
RR
IN MIN
IN MIN L MAX DS MAX
()
()() ()
××+
()
×
()
+×+
()
+=
×
()
××
()
×+
()
+×
()
21
11 2 1 5
41
31 41
ε
εε
ε
εε
-
--
-
R
R
RR
R
VI R
V
IN PEAK MAX DS MAX
IN
3
4
12
21=+××--
() ()
Rm m
DS MAX() .=×+×
()
[]
=70 1 0 005 100 25 100ΩΩ-
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 21
The number of negative charge-pump stages is given by:
where NNEG is the number of negative charge-pump
stages, VNL is the negative linear-regulator output,
VMAIN is the main step-up regulator output, VDis the
forward voltage drop of the charge-pump diode, and
VDROPOUT is the dropout margin for the linear regulator.
Use VDROPOUT = 2V.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to VMAIN and the first stage of the
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
stage to VIN or another available supply.
If the first charge-pump stage is powered from VIN,
then the above equations become:
Flying Capacitor
Increasing the flying capacitor (CX) value increases the
output current capability. Increasing the capacitance
indefinitely has a negligible effect on output current
capability because the internal switch resistance and
the diode impedance limit the source impedance. A
0.1µF ceramic capacitor works well in most low-current
applications. The flying capacitor’s voltage rating must
exceed the following:
where N is the stage number in which the flying capaci-
tor appears, and VMAIN is the main output voltage. For
example, the two-stage positive charge pump in the
typical application circuit (Figure 1) where VMAIN = 9V
contains two flying capacitors. The flying capacitor in
the first stage (C14) requires a voltage rating over 9V.
The flying capacitor in the second stage (C13) requires
a voltage rating over 18V.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where VRIPPLE is the peak-to-peak value of the output
ripple.
Charge-Pump Rectifier Diodes
Use Schottky diodes with a current rating equal to or
greater than two times the average charge-pump input
current.
Linear-Regulator Controllers
Output Voltage Selection
Adjust the positive linear-regulator output voltage by
connecting a resistive voltage-divider from VPL to GND
with the center tap connected to FBP (Figure 1). Select
R13 in the range of 10kΩto 30kΩ.
Calculate R12 with the following equation:
R12 = R13 [(VPL / VFBP) - 1]
where VFBP = 1.25V.
Adjust the negative linear-regulator output voltage by
connecting a resistive voltage-divider from VNL to REF
with the center tap connected to FBN (Figure 1). Select
R10 in the range of 10kΩto 30kΩ. Calculate R9 with the
following equation:
R9 = R10 [(VFBN - VNL) / (VREF - VFBN)]
where VFBN = 125mV, VREF = 1.25V. Note that REF is
only guaranteed to source 50µA. Using a resistor less
than 20kΩfor R10 results in higher bias current than
REF can supply. Connecting another resistor (R14)
from VMAIN to REF (Figure 1) can solve this problem
because the main output can supply part of the resis-
tor’s (R10) bias current. Use the following equation to
determine the value of R14:
Drawing only 40µA from REF leaves the remaining
10µA for other purposes.
Pass Transistor Selection
The pass transistor must meet specifications for current
gain (β), input capacitance, collector-emitter saturation
voltage, and power dissipation.
RVV
VV
RA
MAIN REF
REF FBN
14
10 40
=
µ
-
--
CI
fV
OUT LOAD
OSC RIPPLE
≥2
VNV
CX MAIN
>×
NVV V
VV
NVV V
VV
POS PL DROPOUT IN
MAIN D
NEG NL DROPOUT IN
MAIN D
=+
×
=++
×
-
-
-
-
2
2
NVV
VV
NEG NL DOPOUT
MAIN D
=+
×
-
-2
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
22 ______________________________________________________________________________________
The transistor’s current gain limits the guaranteed maxi-
mum output current to:
where IDRV is the minimum base-drive current, and RBE
is the pullup resistor connected between the transis-
tor’s base and emitter. Furthermore, the transistor’s cur-
rent gain increases the linear regulator’s DC loop gain
(see the Stability Requirements section), so excessive
gain destabilizes the output. Therefore, transistors with
current gain over 100 at the maximum output current
are not recommended. The transistor’s input capaci-
tance and input resistance also create a second pole,
which could be low enough to make the output unsta-
ble when heavily loaded.
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator supports.
Alternatively, the package’s power dissipation could limit
the usable maximum input-to-output voltage differential.
The maximum power dissipation capability of the transis-
tor’s package and mounting must exceed the actual
power dissipation in the device. The power dissipation
equals the maximum load current times the maximum
input-to-output voltage differential:
During startup, the LDO outputs are below their respec-
tive setpoints, and the base drive to the pass transis-
tors is a maximum. The large drive currents can cause
the charge-pump outputs to collapse. If the charge-
pump loading is objectionable, base resistors can be
added between the drive outputs (DRVN and DRVP)
and the pass transistors (Figure 7). These resistors limit
the maximum drive current and prevent discharging the
charge pump’s output capacitors. Select the minimum
base drive current to meet the maximum required LDO
output current:
The resistance required to guarantee this base current is:
As a consequence of adding the base resistors, a volt-
age change at DRVN and DRVP accompanies changes
in drive current. This voltage change can be coupled
through parasitic capacitance to the LDO feedback
pins. If the rate of voltage change is sufficiently large, it
can cause instability.
RVV
I
VV
I
BASE LDOIN MAX BE
DRIVE MIN
MIN LDOIN MAX BE
LDOOUT MAX
≤
=
()
()
()
()
()
-
-β
II
DRIVE MIN
LDOOUT MAX
MIN
()
()
=β
PI V V
IV
LOAD MAX LDOIN LDOOUT
LOAD MAX CE
==
()
()
()-
II
V
R
LOAD MAX DRV BE
BE MIN()
=
-β
DRVP
FBP
DRVN
FBN
Q1 Q2
VPL
7
6
8
9
REF
R20
51kΩ
R19
15kΩ
C24
2200pF
C20
470pF
VNL
VNVP
MAX1889
Figure 7. Limiting LDO Drive Current During Startup
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________________________ 23
To avoid excessive voltage coupling, a small capacitor
can be added in parallel with the base resistor. The
resulting RC time constant should be between 5µs to
50µs.
Stability Requirements
The MAX1889 linear-regulator controllers use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, the
pass transistor, the base-emitter resistor, and the out-
put capacitor determine the loop stability. If the output
capacitor and pass transistor are not properly selected,
the linear regulator can be unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
where VTis 26mV at room temperature, and IBIAS is the
current through the base-to-emitter resistor (RBE). This
bias resistor is typically 3kΩ, providing 0.23mA of cur-
rent, biasing the LDO near its regulation voltage setpoint.
The output capacitor and the load resistance create the
dominant pole in the system. The pass transistor’s input
capacitance creates a second pole in the system.
Additionally, the output capacitor’s ESR generates a zero.
To achieve stable operation, use the following equations
to verify that the linear regulator is properly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
The unity gain crossover of the linear regulator is:
fCROSSOVER = AV(LDO) fPOLE(CLDO)
2) Next, determine the second pole set by the base-
to-emitter capacitance (including the transistor’s
input capacitance), the transistor’s input resistance,
and the base-to-emitter pullup resistor:
3) A third pole is set by the linear regulator’s feedback
resistance and the capacitance (including stray
capacitance) between FB_ and GND (for the posi-
tive LDO) and FBN and GND (for the negative LDO)
(Figure 8):
4) If the second and third poles occur well after unity-
gain crossover, the linear regulator remains stable:
However, if the ESR zero occurs before the unity-gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
A capacitor connected between the output and the
feedback node improves the transient response,
reduces the noise coupled into the feedback loop, and
maintains the correct regulation point (Figure 8).
Output Capacitor Selection
Typically, more output capacitance provides the best
solution, since this also reduces the output voltage drop
immediately after a load transient. Connect at least a
0.1µF capacitor between the linear regulator’s output and
ground, as close to the external pass transistor as possi-
ble. Depending on the selected pass transistor, larger
capacitor values may be required for stability (see the
Stability Requirements section). Furthermore, the output
capacitor’s ESR affects stability. Use output capacitors
with an ESR less than 200mΩto ensure stability and opti-
mum transient response. Once the minimum capacitor
value for stability is determined, verify that the linear regu-
lator’s output does not contain excessive noise. Although
adequate for stability, small capacitor values can provide
too much bandwidth, making the linear regulator sensitive
to noise. Larger capacitor values reduce the bandwidth,
thereby reducing the regulator’s noise sensitivity. If noise
on the ground reference causes the design to be margin-
ally stable for the negative linear regulator, bypass the
negative output back to its reference voltage. This tech-
nique reduces the differential noise on the output.
f
CR
POLE FB
OUT ESR
()
≈1
2π
ffA
POLE CBE POLE CLDO V LDO() ( )()
>2
f
C R II R
f
C R II R
POLE FB POS
FB
POLE FB NEG
FB
()_
()_
()
()
=
=
1
21213
1
2910
π
π
fC R II R
RI Vh
CRVh
POLE CBE BE BE IN
BE LOAD T FE
BE BE T FE
() ()
=
=+
1
2
2
π
π
f
CR
I
CV
POLE CLDO
LDO LOAD
LOAD MAX
LDO LDO
()
()
==
1
22ππ
A
V
Ih
I
V
V LDO
T
BIAS FE
LOAD
REF()
.
=
+
55 1
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
24 ______________________________________________________________________________________
Applications Information
PC Board Layout
Careful PC board layout is extremely important for
proper operation. Use the following guidelines for good
PC board layout:
1) Minimize the area of high-current loops by placing
the input capacitors, inductor, output diode, and
output capacitors less than 0.2in (5mm) from the LX
and PGND pins. Connect these components with
traces as wide as possible. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
2) Create islands for the analog ground (GND), power
ground (PGND), and linear regulator ground. Star-
connect them to the backside pad of the device.
The REF bypass capacitor and both feedback
dividers should be connected to the analog ground
island (GND). The step-up regulator’s input and out-
put capacitors, and the charge-pump components
should be a wide power ground plane. The power
ground plane should be connected to the power
ground pin (PGND) with a wide trace. Maximizing
the width of the power ground traces improves effi-
ciency and reduces output voltage ripple and noise
spikes. All the other ground connections, such as
the IN pin bypass capacitor and the linear regulator
output capacitors, should be star-connected to the
backside of the device with wide traces. Make no
other connections between these separate ground
planes.
3) Place IN pin and REF pin bypass capacitors as
close to the device as possible.
4) Place all feedback voltage-divider resistors as close
to their respective feedback pins as possible. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near LX or the switching nodes in the charge
pumps.
5) Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
6) Minimize the size of LX node while keeping it wide
and short. Keep the LX node away from feedback
nodes (FB, FBP, and FBN) and analog ground. Use
DC traces as shield if necessary.
Refer to the MAX1889 evaluation kit for an example of
proper board layout.
DRVP
FBP
DRVN
FBN
Q1 Q2
VPL
7
6
8
9
REF
VNL
VNVP
MAX1889
C19
1000pF
R9
150kΩ
1%
R8
3kΩ
R10
24.3kΩ
1%
R13
20kΩ
1%
R12
301kΩ
1%
C21
1000pF
R11
3kΩ
Figure 8. LDO Compensation
Additional Application Circuits
Operation with Output Voltage >13V
The maximum output voltage of the step-up regulator is
13V, which is limited by the absolute maximum rating of
the internal power MOSFET. To achieve higher output
voltage, an external N-channel MOSFET can be cas-
coded with the internal FET (Figure 9). Since the gate of
the external FET is biased from the input supply, use a
logic-level FET to ensure that the FET is fully enhanced
at the minimum input voltage. The current rating of the
FET needs to be higher than the internal current limit.
Changing Power-Up Sequence
The power-up sequencing of the linear regulators can be
controlled using external delays. Figure 10 shows an
application where the negative linear-regulator output
powers up with a certain delay after the positive linear
regulator reaches regulation. The resistors R1, R2, and
the capacitor C form an RC network that provides the
power-up delay. The time constant of this RC network is:
Select the ratio of R1 and R2 so that:
or:
With this R1/R2 ratio, the power-up delay can be calcu-
lated as:
where VDis the forward voltage drop of the diode and
0.125V is the FBN regulation point.
As a design example, assume the positive linear-regu-
lator output VPL is +20V, the negative charge-pump
output VNis -9V, and the required power-up delay time
tDis 4ms:
The ratio of R1 and R2 should be:
The required RC time constant is:
Choose C = 0.1µF, then R1//R2 = 16.8kΩ. Use stan-
dard resistor values: R1 = 56kΩand R2 = 24kΩ.
Disabling Input MOSFET Switch
If the input protection MOSFET is not needed, disable
the input overcurrent comparator by connecting the
OCP pin to ground, the OCN pin to VIN. Leave the
GATE pin floating (Figure 11).
Generating Gamma Reference Voltage
The reference voltage for the Gamma correction resis-
tor string can be produced using the linear-regulator
controller. If the voltage difference between the main
boost voltage (VMAIN) and the Gamma reference volt-
age is 400mV or greater, the emitter of the PNP pass
transistor should be connected to VMAIN.
τ=
+
=
4
20 9
20 9
07 0125
168
ms ms
ln
..
.
-
R
R
1
2
9
20
=
ττ
D
PL
D
VR
RR
VV
=+
ln .
1
12
0 125-
R
R
V
V
N
PL
1
2=-
VR
RR VR
RR
NPL
2
12
1
12
0
+++=
τ= ×
+
RR
RR
C
12
12
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 25
STEP-UP
REGULATOR
LX
FB
PGND
MAX1889
VNVP
VMAIN
15V
VIN
Figure 9. Operation with Output Voltage >13V Using Cascoded
MOSFET
MAX1889
If the voltage difference is less than 400mV, then the
emitter of the PNP should be connected to a high sup-
ply voltage. The VPoutput has two charge-pump
stages added to VMAIN. The emitter of the PNP can be
connected to the output of the first stage as shown in
Figure 12. For higher efficiency, the first charge-pump
stage can be connected to VIN rather than VMAIN, as
this reduces the power loss.
Triple-Output TFT LCD Power Supply
with Fault Protection
26 ______________________________________________________________________________________
POSITIVE
REGULATOR
STEP-UP
REGULATOR
NEGATIVE
REGULATOR
REF
FB
PGND
DRVP
FBP
LX
DRVN
FBN
REF
GND
MAX1889
VN
VP
VMAIN
+9V
VN
VN
VNL
-7V
VPL
VP
VPL
+20V
R1
R2 C
VIN
Figure 10. Controlling Power-Up Sequence with External Delay
Chip Information
TRANSISTOR COUNT: 2396
PROCESS: BiCMOS
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 27
SWITCH
CONTROL STEP-UP
REGULATOR
REF
GATE
IN
OCP
LX
FB
PGND
REF
GND
MAX1889
VN
VP
VIN
3.3V OR 5V
VMAIN
9V
OCN
Figure 11. Disabling Input Protection MOSFET Switch
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
28 ______________________________________________________________________________________
POSITIVE
REGULATOR
STEP-UP
REGULATOR
NEGATIVE
REGULATOR
REF +8.9V
LX
FB
PGND
DRVP
FBP
REF
GND
DRVN
FBN
MAX1889
VN
VP
VMAIN
+9V
VN
VNL
-7V
VGAMMA
VIN
Figure 12. Generating Gamma Reference Voltage
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 29
32L QFN.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
30 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________ 31
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15 C B
0.15 C A
DOCUMENT CONTROL NO.
21-0140
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
PROPRIETARY INFORMATION
APPROVAL
TITLE:
C
REV.
2
1
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45
L
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
k
L
L
MAX1889
Triple-Output TFT LCD Power Supply
with Fault Protection
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
2
2
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
COMMON DIMENSIONS EXPOSED PAD VARIATIONS
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
C
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm