DS2433S+ - Maxim - Datasheet.Directory

AVAILABLE

Functional Diagrams

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

PRELIMINARY

19-5581; 10/10

DS2433

4Kb 1-Wire EEPROM

FEATURES

 4096 Bits Electrically Erasable Programmable

Read-Only Memory (EEPROM)

 Unique, Factory-Lasered and Tested 64-Bit

Registration Number (8-Bit Family Code +

48-Bit Serial Number + 8-Bit CRC Tester)

Assures Absolute Identity Because No Two

Parts Are Alike

 Built-In Multidrop Controller Ensures

Compatibility with Other MicroLAN

Products

 Memory Partitioned Into Sixteen 256-Bit

Pages for Packetizing Data

 256-Bit Scratchpad with Strict Read/Write

Protocols Ensures Integrity of Data Transfer

 Reduces Control, Address, Data, and Power

to a Single Data Pin

 Directly Connects to a Single Port Pin of a

Microprocessor and Communicates at Up to

16.3kbps

 Overdrive Mode Boosts Communication

Speed to 142kbps

 8-Bit Family Code Specifies DS2433

Communication Requirements to Reader

 Presence Detector Acknowledges When

Reader First Applies Voltage

 Low-Cost PR-35, SFN, Flip Chip, or 8-Pin

SO Surface-Mount Packages

 Reads and Writes Over a Wide Voltage

Range of 2.8V to 6.0V from -40°C to +85°C

PIN DESCRIPTION

PIN PR-35 SO SFN Flip

Chip

1 Ground NC Data Ground

2 Data NC Ground Data

3 NC Data — NC

4 — Ground — NC

5, 6 — NC — NC

7, 8 — NC — —

PIN CONFIGURATIONS

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2433+ -40°C to +85°C 3 PR-35

DS2433S+ -40°C to +85°C 8 SO

DS2433S+T&R -40°C to +85°C 8 SO

DS2433G+T&R -4 0° C t o +85 °C 2 SFN

DS2433X#T -40°C to +85°C 6 Flip Chip

(10k pieces)

DS2433X-S#T -40°C to +85°C 6 Flip Chip

(2.5k pieces)

+Denotes a lead(Pb)-free package.

#Denotes a RoHS-compliant device that may include lead(Pb) that is

exempt under the RoHS requirements.

T/T&R = Tape and reel.

DATA

GND

SO (208 mils)

BOTTOM VIEW

123

PR-35

TOP VIEW

Pin Configurations continued at end of data sheet.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

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DESCRIPTION

The DS2433 4Kb 1-Wire® EEPROM identifies and stores relevant information about the product to

which it is associated. This lot or product specific information can be accessed with minimal interface, for

example a single port pin of a microcontroller. The DS2433 consists of a factory-lasered registration

number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (23h) plus

4096 bits of user-programmable EEPROM. The power to read and write the DS2433 is derived entirely

from the 1-Wire communication line. The memory is organized as sixteen pages of 256 bits each. The

scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the

scratchpad where it may be read back for verification. A copy scratchpad command will then transfer the

data to memory. This process insures data integrity when modifying the memory. The 64-bit registration

number provides a guaranteed unique identity which allows for absolute traceability and acts as node

address if multiple DS2433s are connected in parallel to form a local network. Data is transferred serially

via the 1-Wire protocol which requires only a single data lead and a ground return. The PR-35 and SO

packages provide a compact enclosure that allows standard assembly equipment to handle the device

easily for attachment to printed circuit boards or wiring. Typical applications include storage of

calibration constants, board identification and product revision status.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS2433. The DS2433 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,

and 3) 4096-bit EEPROM. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The

bus master must first provide one of the six ROM Function Commands, 1) Read ROM, 2) Match ROM,

3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion

of an overdrive ROM command byte executed at regular speed, the device will enter Overdrive mode

where all subsequent communication occurs at a higher speed. The protocol required for these ROM

function commands is described in Figure 9. After a ROM function command is successfully executed,

the memory functions become accessible and the master may provide any one of the four memory

function commands. The protocol for these memory function commands is described in Figure 7. All data

is read and written least significant bit first.

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power

whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and

voltage requirements are met.

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

3 of 23

Figure 1. DS2433 BLOCK DIAGRAM

64-BIT LASERED ROM

Each DS2433 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family

code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See

Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and

XOR gates as shown in Figure 4. The polynomial is X8+ X5+ X4+ 1. Additional information about the

Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27.

The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,

one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number

is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC

value. Shifting in the eight bits of CRC should return the shift register to all zeros.

MEMORY

The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages

called memory. The DS2433 contains pages 0 through 15 that make up the 4096-bit EEPROM. The

scratch-pad is an additional page that acts as a buffer when writing to memory.

ADDRESS REGISTERS AND TRANSFER STATUS

Because of the serial data transfer, the DS2433 employs three address registers, called TA1, TA2 and E/S

(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be

written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte

counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,

the master only has read access to this register. The lower five bits of the E/S register indicate the address

of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the

E/S register, called PF, is set if the number of data bits sent by the master is not an integer multiple of 8 or

if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

4 of 23

the PF bit. Bit 6 has no function; it always reads 0. Note that the lowest five bits of the target address also

determine the address within the scratchpad, where intermediate storage of data will begin. This address

is called byte offset. If the target address (TA1) for a Write command is 03Ch for example, then the

scratchpad will store incoming data beginning at the byte offset 1Ch and will be full after only four bytes.

The corresponding ending offset in this example is 1Fh. For best economy of speed and efficiency, the

target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0. Thus

the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1Fh.

However, it is possible to write one or several contiguous bytes somewhere within a page. The ending

offset together with the Partial Flag support the master checking the data integrity after a Write command.

The highest valued bit of the E/S register, called AA is valid only if the PF flag reads 0. If PF is 0 and AA

is 1, a copy has taken place. The AA bit is cleared when the device receives a write scratchpad command.

WRITING WITH VERIFICATION

To write data to the DS2433, the scratchpad has to be used as intermediate storage. First the master issues

the Write Scratchpad command to specify the desired target address, followed by the data to be written to

the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an

inverted CRC16 of the command, address and data at the end of the write scratchpad command sequence.

Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the

communication was successful and proceed to the Copy Scratchpad command. If the master could not

receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to verify

data integrity. As preamble to the scratchpad data, the DS2433 repeats the target address TA1 and TA2

and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the

scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not

need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag

together with a cleared PF flag indicates that the Write command was not recognized by the device. If

everything went correctly, both flags are cleared and the ending offset indicates the address of the last

byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After

the master has verified the data, it has to send the Copy Scratchpad command. This command must be

followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the

contents of these registers by reading the scratchpad or derive it from the target address and the amount of

data to be written. As soon as the DS2433 has received these bytes correctly, it will copy the data to the

requested location beginning at the target address.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

5 of 23

Figure 2. HIERARCHCAL STRUCTURE FOR 1-Wire PROTOCOL

Figure 3. 64-BIT LASERED ROM

MSB LSB

8-BIT CRC CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (23h)

MSB LSB MSB LSB MSB LSB

Figure 4. 1-Wire CRC GENERATOR

X0X1X2X3X4X5X6X7X8

Polynomial = X8 + X5 + X4 + 1

1st

STAGE

2nd

STAGE

3rd

STAGE

4th

STAGE

6th

STAGE

5th

STAGE

7th

STAGE

8th

STAGE

INPUT DATA

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

6 of 23

MEMORY FUNCTION COMMANDS

The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory.

An example follows the flowchart. The communication between master and DS2433 takes place either at

regular speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive

Mode the DS2433 assumes regular speed.

WRITE SCRATCHPAD COMMAND [0Fh]

After issuing the write scratchpad command, the master must first provide the 2-byte target address,

followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at

the byte offset (T4:T0). The ending offset (E4:E0) will be the byte offset at which the master stops

writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be

ignored and the partial byte flag PF will be set.

When executing the Write Scratchpad command the CRC generator inside the DS2433 (see Figure 12)

calculates a CRC over the entire data stream, starting at the command code and ending at the last data

byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC

generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the Target

Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write

Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read

time slots and will receive the CRC generated by the DS2433.

The memory address range of the DS2433 is 0000h to 01FFh. If the bus master sends a target address

higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as

they are shifted into the internal address register. The Read Scratchpad command will reveal the target

address as it will be used by the DS2433. The master will identify such address modifications by

comparing the target address read back to the target address transmitted. If the master does not read the

scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the

target address the master sends will not match the value the DS2433 expects.

READ SCRATCHPAD COMMAND [AAh]

This command is used to verify scratchpad data and target address. After issuing the read scratchpad

command, the master begins reading. The first two bytes will be the target address. The next byte will be

the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:

T0). The master may read data until the end of the scratchpad after which the data read will be all logic

1s.

COPY SCRATCHPAD [55h]

This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad

command, the master must provide a 3-byte authorization pattern which can be obtained by reading the

scratchpad for verification. This pattern must exactly match the data contained in the three address

registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag

will be set and the copy will begin. Copy takes 5 ms maximum during which the voltage on the 1-Wire

bus must not fall below 2.8V. A pattern of alternating 1s and 0s will be received after the data has been

copied until a Reset Pulse is issued by the master.

The data to be copied is determined by the three address registers. The scratchpad data from the

beginning offset through the ending offset, will be copied to memory, starting at the target address.

Anywhere from 1 to 32 bytes may be copied to memory with this command.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

7 of 23

Figure 5. DS2433 MEMORY MAP

32-BYTE INTERMEDIATE STORAGE SCRATCHPAD

ADDRESS

0000h TO 001Fh PAGE 0

32-BYTE FINAL STORAGE EEPROM

PAGE 1

32-BYTE FINAL STORAGE EEPROM

0020h TO 003Fh

PAGE 2

FINAL STORAGE EEPROM

0040h TO 01DFh TO PAGE 14

32-BYTE FINAL STORAGE EEPROM PAGE 15

1FE0h TO 01FFh

Figure 6. ADDRESS REGISTER

READ MEMORY [F0h]

The read memory command may be used to read the entire memory. After issuing the command, the

master must provide the 2-byte target address. After the two bytes, the master reads data beginning from

the target address and may continue until the end of memory, at which point logic 1s will be read. It is

important to realize that the target address registers will contain the address provided. The ending

offset/data status byte is unaffected.

The hardware of the DS2433 provides a means to accomplish error-free writing to the memory section.

To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is

recommended to packetize data into data packets of the size of one memory page each. Such a packet

would typically store a 16-bit CRC with each page of data to insure rapid, error-free data transfers that

eliminate having to read a page multiple times to determine if the received data is correct or not. (Refer to

Application Note 114 for the recommended file structure.)

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0

T15

TARGET ADDRESS (TA2) T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

AA 1) PF E4 E3 E2 E1 E0

DATA STATUS (E/S)

(READ ONLY)

1) THIS BIT WILL ALWAYS BE 0.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

8 of 23

Figure 7. MEMORY FUNCTION FLOWCHART

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

9 of 23

Figure 7. MEMORY FUNCTION FLOWCHART (continued)

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

10 of 23

MEMORY FUNCTION EXAMPLE

Example: Write two data bytes to memory location 0026 and 0027. Read entire memory.

MASTER MODE DATA (LSB FIRST) COMMENTS

Tx Reset

Reset Pulse (480s to 960s)

Rx Presence Presence Pulse

Tx CCh Issue Skip ROM Command

Tx 0Fh Issue Write Scratchpad command

Tx 26h TA1, beginning offset = 26h

Tx 00h TA2, address = 0026h

Tx <2 data bytes> Write 2 bytes of data to scratchpad

Tx Reset Reset Pulse

Rx Presence Presence Pulse

Tx CCh Issue Skip ROM Command

Tx AAh Issue Read Scratchpad command

Rx 26h Read TA1, beginning offset = 26h

Rx 00h Read TA2, address = 0026h

Rx 07h Read E/S, ending offset = 7h, flags = 0h

Rx <2 data bytes> Read scratchpad data and verify

Tx Reset Reset Pulse

Rx Presence Presence Pulse

Tx CCh Issue Skip ROM Command

Tx 55h Issue Copy Scratchpad command

Tx 26h

Tx 00h

Tx 07h

TA1

TA2 AUTHORIZATION CODE

E/S

Tx <idle or strong pullup> Wait 5ms

Tx Reset Reset Pulse

Rx Presence Presence Pulse

Tx CCh Issue Skip ROM Command

Tx F0h Issue Read Memory command

Tx 00h TA1, beginning offset = 0

Tx 00h TA2, address = 0000h

Rx <512 bytes> Read entire memory

Tx Reset Reset Pulse

Rx Presence Presence Pulse, done

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

11 of 23

Figure 8. HARDWARE CONFIGURATION

RPU*

*5k IS ADEQUATE FOR READING THE DS2433. TO WRITE TO A SINGLE DEVICE, A 2.2k



RESISTOR AND VPUP OF AT LEAST 4.0V IS

SUFFICIENT. FOR WRITING MULTIPLE DS2433s SIMULTANEOUSLY OR OPERATION AT LOW VPUP, THE RPU SHOULD BE BYPASSED

BY A LOW-IMPEDANCE PULLUP TO VPUP WHILE THE DEVICE COPIES THE SCRATCHPAD TO EEPROM. DEPENDING ON THE 1-Wire

COMMUNICATION SPEED AND THE BUS LOAD CHARACTERISTICS, THE OPTIMAL PULLUP RESISTOR (RPU) VALUE WILL BE IN THE

1.5k TO 5k RANGE.

1-Wire BUS SYSTEM

The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the

DS2433 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system

is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling

(signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during

specific time slots that are initiated on the falling edge of sync pulses from the bus master.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open

drain or 3-state outputs. The 1-Wire port of the DS2433 is open drain with an internal circuit equivalent

to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At

regular speed the 1-Wire bus has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps

by activating the Overdrive Mode. The 1-Wire bus requires a pullup resistor of approximately 5k.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low

for more than 16s (Overdrive Speed) or more than 120s (regular speed), one or more devices on the

bus may be reset.

TRANSACTION SEQUENCE

The protocol for accessing the DS2433 via the 1-Wire port is as follows:

 Initialization

 ROM Function Command

 Memory Function Command

 Transaction/Data

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

12 of 23

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence

consists of a Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the

slave(s).

The Presence Pulse lets the bus master know that the DS2433 is on the bus and is ready to operate. For

more details, see the 1-Wire Signaling section.

ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the six ROM function commands. All

ROM function commands are eight bits long. A list of these commands follows (see the flowchart in

Figure 9).

READ ROM [33h]

This command allows the bus master to read the DS2433’s 8-bit family code, unique 48-bit serial

number, and 8-bit CRC. This command can only be used if there is a single DS2433 on the bus. If more

than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same

time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number

will result in a mismatch of the CRC.

MATCH ROM [55h]

The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a

specific DS2433 on a multidrop bus. Only the DS2433 that exactly matches the 64-bit ROM sequence

will respond to the following memory function command. All slaves that do not match the 64-bit ROM

sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the

bus.

SKIP ROM [CCh]

This command can save time in a single drop bus system by allowing the bus master to access the

memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus

and a read command is issued following the Skip ROM command, data collision will occur on the bus as

multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result).

SEARCH ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the

1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process

of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process

is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the

desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.

After one complete pass, the bus master knows the contents of the ROM in one device. The remaining

number of devices and their ROM codes may be identified by additional passes. Refer to Application

Note 187 for a comprehensive discussion of a search ROM, including an actual example.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

13 of 23

OVERDRIVE SKIP ROM [3Ch]

On a single-drop bus this command can save time by allowing the bus master to access the memory

functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive

Skip ROM sets the DS2433 in the Overdrive Mode (OD = 1). All communication following this

command has to occur at Overdrive Speed until a Reset Pulse of minimum 480s duration resets all

devices on the bus to regular speed (OD = 0).

When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive

mode. To subsequently address a specific Overdrive-supporting device, a Reset Pulse at Overdrive speed

has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the

time for the search process. If more than one slave supporting Overdrive is present on the bus and the

Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as

multiple slaves transmit simultaneously (open drain pulldowns will produce a wire-AND result).

OVERDRIVE MATCH ROM [69h]

The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive

Speed, allows the bus master to address a specific DS2433 on a multidrop bus and to simultaneously set it

in Overdrive Mode. Only the DS2433 that exactly matches the 64-bit ROM sequence will respond to the

subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive

Skip or Match command will remain in Overdrive mode. All overdrive-capable slaves will return to

regular speed at the next Reset Pulse of minimum 480s duration. The Overdrive Match ROM command

can be used with a single or multiple devices on the bus.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

14 of 23

Figure 9. ROM FUNCTIONS FLOWCHART (FIRST PART)

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

15 of 23

Figure 9. ROM FUNCTIONS FLOWCHART (SECOND PART)

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

16 of 23

1-Wire SIGNALING

The DS2433 requires strict protocols to insure data integrity. The protocol consists of four types of

signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read

Data. All these signals except Presence Pulse are initiated by the bus master. The DS2433 can

communicate at two different speeds, regular speed and Overdrive Speed. If not explicitly set into the

overdrive mode, the DS2433 will communicate at regular speed. While in Overdrive Mode the fast timing

applies to all wave forms.

The initialization sequence required to begin any communication with the DS2433 is shown in Figure 10.

A Reset Pulse followed by a Presence Pulse indicates the DS2433 is ready to send or receive data given

the correct ROM command and memory function command. The bus master transmits (Tx) a Reset Pulse

(tRSTL, minimum 480s at regular speed, 48s at Overdrive Speed). The bus master then releases the line

and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state via the pullup resistor. After

detecting the rising edge on the data pin, the DS2433 waits (tPDH, 15-60s at regular speed, 2-6s at

Overdrive speed) and then transmits the Presence Pulse (tPDL, 60-240s at regular speed, 8-24s at

Overdrive Speed).

A Reset Pulse of 480s or longer will exit the Overdrive Mode returning the device to regular speed. If

the DS2433 is in Overdrive Mode and the Reset Pulse is no longer than 80s the device will remain in

Overdrive Mode.

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the

master driving the data line low. The falling edge of the data line synchronizes the DS2433 to the master

by triggering a delay circuit in the DS2433. During write time slots, the delay circuit determines when the

DS2433 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS2433 will hold the data line low overriding the 1 generated by the master. If

the data bit is a “1,” the device will leave the read data time slot unchanged.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

17 of 23

Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES

*IN ORDER NOT TO MASK INTERRUPT SIGNALLING BY OTHER DEVICES ON THE 1-WIRE BUS, tRSTL + tR SHOULD ALWAYS BE LESS THAN 960µs.

**INCLUDES RECOVERY TIME.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

18 of 23

Figure 11. READ/WRITE TIMING DIAGRAM

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

19 of 23

CRC GENERATION

With the DS2433 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-

bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC

value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2433 to

determine if the ROM data has been received error-free by the bus master. The equivalent polynomial

function of this CRC is: X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (noninverted) form

when reading the ROM of the DS2433. It is computed at the factory and lasered into the ROM.

The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x16+

x15+x2+ 1. This CRC is used for fast verification of a data transfer when writing to the scratchpad. It is the

same type of CRC as is used with NV RAM based iButtons® for error detection within the iButton

Extended File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned or sent in the

complemented (inverted) form. A CRC-generator inside the DS2433 chip (Figure 12) will calculate a new

16-bit CRC as shown in the command flowchart of Figure 7. The bus master compares the CRC value

read from the device to the one it calculates from the data and decides whether to continue with an

operation.

With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then

shifting in the command code, the Target Addresses TA1 and TA2 and all the data bytes. The DS2433

will transmit this CRC only if the data bytes written to the scratchpad include scratchpad ending offset

11111b. The data may start at any location within the scratchpad.

For more details on generating CRC values including example implementations in both hardware and

software, refer to the Book of iButton Standards.

Figure 12. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL

(POLYNOMIAL X16+ X15+ X2+ 1)

iButton is a registered trademark of Maxim Integrated Products, Inc.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

20 of 23

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground ..................................................................... -0.5V to +7.0V

Operating Temperature Range ...............................................................................................-40C to +85C

Storage Temperature Range ................................................................................................-55C to +125C

Lead Temperature (PR-35, SOIC only, soldering 10s) ..................................................................... +300°C

Soldering Temperature (reflow)

PR-35, SOIC ................................................................................................................................. +260°C

Flip Chip ........................................................................................................................................ +240°C

SFN .....Refer to Application Note 4132: Attachment methods for the electro-mechanical SFN package

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device

reliability.

DC ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Pullup Voltage VPUP 2.8 6.0 V 1

Logic 1 VIH 2.2 V 2, 3

Logic 0 VIL -0.3 0.5 V 2

Output Logic-Low at 4mA VOL 0.4 V 2

Input Load Current IL 5

A 4

Programming Current ILPROG 500

A 5

CAPACITANCE

(TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

I/O (1-Wire) CIN/OUT 100 800 pF 6

EEPROM

(VPUP = 5.0V, TA = +25C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Write/Erase Cycles NCYCLE 50k 7

AC ELECTRICAL CHARACTERISTICS—REGULAR SPEED

(TA = -40C to +85C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Time Slot tSLOT 60 120

s

Write 1 Low Time tLOW1 1 15

s 8

Write 0 Low Time tLOW0 60 120

s

Read Low Time tLOWR 1 15

s 8

Read Data Valid tRDV 15

s 9

Release Time tRELEASE 0 15 45 s

Read Data Setup tSU 1

s 10

Recovery Time tREC 1

s

Reset Time High tRSTH 480 s 11

Reset Time Low tRSTL 480 960

s 12

Presence Detect High tPDHIGH 15 60 s

Presence Detect Low tPDLOW 60 240

s

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

21 of 23

AC ELECTRICAL CHARACTERISTICS—OVERDRIVE SPEED

(TA = -40C to +85C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Time Slot tSLOT 6 16

s

Write 1 Low Time tLOW1 1 2

s 8

Write 0 Low Time tLOW0 6 16

s

Read Low Time tLOWR 1 2 s 8

Read Data Valid tRDV 2

s 9

Release Time tRELEASE 0 1.5 4 s

Read Data Setup tSU 1

s 10

Recovery Time tREC 1

s

Reset Time High tRSTH 48 s 11

Reset Time Low tRSTL 48 80

s

Presence Detect High tPDHIGH 2 6 s

Presence Detect Low tPDLOW 8 24

s

NOTES:

1) VPUP = external pullup voltage. See Figure 8.

2) All voltages are referenced to ground.

3) VIH is a function of the external pullup resistor and VPUP.

4) Input load is to ground.

5) The Copy Scratchpad takes 5ms maximum during which the voltage on the 1-Wire bus must not fall

below 2.8V.

6) Capacitance on the data pin could be 800pF when power is first applied. If a 5kresistor is used to

pull up the data line to VPUP, 5s after power has been applied the parasite capacitance will not affect

normal communications.

7) During the execution of the Copy Scratchpad command the DS2433 automatically erases the memory

locations to be written to. No extra steps need to be taken by the bus master.

8) The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value

as short as possible to allow time for the pullup resistor to recover the line to a high level before the

1-Wire device samples in the case of a write-one time or before the master samples in the case of a

read-one time.

9) The optimal sampling point for the master is as close as possible to the end time of the tRDV period

without exceeding tRDV. For the case of a read-one time slot, this maximizes the amount of time for

the pullup resistor to recover to a high level. For a read-zero time slot, it ensures that a read will occur

before the fastest device(s) release the line.

10) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is

guaranteed to be valid within 1 s of this falling edge.

11) An additional reset or communication sequence cannot begin until the reset high time has expired.

12) The reset low time (tRSTL) should be restricted to a maximum of 960s, to allow interrupt signaling,

otherwise, it could mask or conceal interrupt pulses.

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

22 of 23

PIN CONFIGURATIONS (continued)

SFN (APPROX. 6.0mm x 6.0mm x 0.9mm)

BOTTOM VIEW SIDE VIEW

1 2

433

yywwrr

###xx

2 3 4

1 6 5

NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-

MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR

SOLDERING. FOR MORE INFORMATION, REFER TO

APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE

ELECTRO-MECHANICAL SFN PACKAGE.

FLIP CHIP

(TOP VIEW WITH LASER MARK,

CONTACTS NOT VISIBLE.)

“yywwrr” = DATE/REVISION

###xx = LOT NUMBER

PACKAGE INFORMATION

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a

different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

6 Flip Chip BF623#3 21-0291 See 21-0291

3 PR-35 D3+1 21-0247 —

2 SFN G266N+1 21-0390 —

8 SO (208 mils) W8+2 21-0262 90-0258

NOT RECOMMENDED FOR NEW DESIGNS

DS2433

REVISION HISTORY

REVISION

DATE DESCRIPTION PAGES

CHANGED

Added the flip chip package (Features, Ordering Information, Pin

Assignment), changing name from chip scale package; added SFN package

to Ordering Information/Features; updated Ordering Information with lead-

free packages.

3/07

In Figure 5, changed “32-BIT INTERMEDIATE STORAGE

SCRATCHPAD” TO “32-BYTE INTERMEDIATE STORAGE

SCRATCHPAD.”

In the SFN pin configuration, added information that the package is

qualified for electro-mechanical contact applications only, not for

soldering, and added reference to Application Note 4132.

In the Absolute Maximum Ratings section, removed the “A” from the

soldering temperature specification. 20

3/08

Added Package Information table. 22

In the Ordering Information table, removed the leaded parts for the PR-35

and SO packages and changed the flip chip packages from standard to

RoHS compliant.

5/08

In the flip chip pin configuration, changed the revision code format from

“rrr” to “rr.” 22

Corrected the clearing of PF, AA flags in the Write Scratchpad flow 8

Updated soldering temperatures, relocated VPUP from EC-table header to

EC-table DC section, changed VILMAX from 0.8V to 0.5V, deleted VOH

from the EC table, renumbered the EC table notes.

20, 21

10/10

Changed SOIC package code from W8+3 to W8+2, corrected SFN package

code (was G266+1), added land pattern information. 22

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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