Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8226
Rev. B
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FEATURES
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
Dual supplies: ±1.35 V to ±18 V
Bandwidth (G = 1): 1.5 MHz
CMRR (G = 1): 90 dB minimum for BR models
Input noise: 22 nV/√Hz
Typical supply current: 350 µA
Specified temperature: −40°C to +125°C
8-lead SOIC and MSOP packages
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
PIN CONFIGURATION
TOP VIEW
(Not t o Scal e)
07036-001
–IN 1
RG2
RG3
+IN 4
+VS
8
VOUT
7
REF
6
–V
S
5
AD8226
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220 AD8231 AD620 AD627 AD8250
AD8221 AD8290 AD621 AD623 AD8251
AD8222 AD8293 AD524 AD8223 AD8253
AD8224 AD8553 AD526 AD8226
AD8228 AD8556 AD624 AD8227
AD8295 AD8557 AD8235/
AD8236
1 Visit www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8226 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain
between 1 and 1000.
The AD8226 is designed to work with a variety of signal
voltages. A wide input range and rail-to-rail output allow the
signal to make full use of the supply rails. Because the input
range also includes the ability to go below the negative supply,
small signals near ground can be amplified without requiring dual
supplies. The AD8226 operates on supplies ranging from ±1.35 V
to ±18 V for dual supplies and 2.2 V to 36 V for single supply.
The robust AD8226 inputs are designed to connect to real-
world sensors. In addition to its wide operating range, the
AD8226 can handle voltages beyond the rails. For example,
with a ±5 V supply, the part is guaranteed to withstand ±35 V
at the input with no damage. Minimum as well as maximum
input bias currents are specified to facilitate open wire detection.
The AD8226 is perfect for multichannel, space-constrained
industrial applications. Unlike other low cost, low power
instrumentation amplifiers, the AD8226 is designed with
a minimum gain of 1 and can easily handle ±10 V signals.
With its MSOP package and 125°C temperature rating, the
AD8226 thrives in tightly packed, zero airflow designs.
The AD8226 is available in 8-lead MSOP and SOIC packages,
and is fully specified for −40°C to +125°C operation.
For a device with a similar package and performance as the
AD8226 but with gain settable from 5 to 1000, consider using
the AD8227.
AD8226
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 19
Architecture ................................................................................. 19
Gain Selection ............................................................................. 19
Reference Terminal .................................................................... 20
Input Voltage Range ................................................................... 20
Layout .......................................................................................... 20
Input Bias Current Return Path ............................................... 21
Input Protection ......................................................................... 22
Radio Frequency Interference (RFI) ........................................ 22
Applications Information .............................................................. 23
Differential Drive ....................................................................... 23
Precision Strain Gage ................................................................. 24
Driving an ADC ......................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
3/11—Rev. A to Rev. B
Added AD8235/AD8236 to Table 1 ............................................... 1
Changes to Endnote 1, Table 2 ........................................................ 4
Change Endnote 2 Placement in Total Noise Equation, Table 3 ...... 5
Added G > 1 BRZ, BRMZ Max Parameter .................................... 6
Changes to Endnote 1, Table 3 ........................................................ 6
Changes to Figure 18 ...................................................................... 11
Changes to Figure 37 ...................................................................... 14
Changes to Figure 42 ...................................................................... 15
Updated Outline Dimensions ....................................................... 25
7/09—Rev. 0 to Rev. A
Added BRZ and BRM Models .......................................... Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 1
Changes to General Description Section ...................................... 1
Changes to Gain vs. Temperature Parameter, Output Parameter,
and Operating Range Parameter, Table 2 .......................................... 4
Changes to Common-Mode Rejection Ratio (CMRR) Parameter
and to Input Offset, VOSO, Average Temperature Coefficient
Parameter, Table 3 ........................................................................ 5
Changes to Gain vs. Temperature Parameter, Table 3 ................. 6
Changes to Gain Selection Section............................................... 19
Changes to Reference Terminal Section and Input Voltage
Range Section .............................................................................. 20
Changes to Ordering Guide .......................................................... 25
1/09—Revision 0: Initial Version
AD8226
Rev. B | Page 3 of 28
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = −10 V to +10 V
CMRR with DC to 60 Hz
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
CMRR with DC at 5 kHz
G = 1 80 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 100 100 dB
NOISE Total noise: eN = √(eNI2 + (eNO/G)2)
Voltage Noise 1 kHz
Input Voltage Noise, eNI 22 24 22 24 nV/√Hz
Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2 2 µV p-p
G = 10 0.5 0.5 µV p-p
G = 100 to 1000 0.4 0.4 µV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI VS = ±5 V to ±15 V 200 100 µV
Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 µV/°C
Output Offset, VOSO VS = ±5 V to ±15 V 1000 500 µV
Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 µV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current1TA = +25°C 5 20 27 5 20 27 nA
TA = +125°C 5 15 25 5 15 25 nA
TA = −40°C 5 30 35 5 30 35 nA
Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 0.5 nA
TA = +125°C 1.5 0.5 nA
TA = −40°C 2 0.5 nA
Average Temperature Coefficient TA = −40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 100 100 kΩ
IIN 7 7 µA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1 1500 1500 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
AD8226
Rev. B | Page 4 of 28
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time 0.01% 10 V step
G = 1 25 25 µs
G = 10 15 15 µs
G = 100 40 40 µs
G = 1000 350 350 µs
Slew Rate G = 1 0.4 0.4 V/µs
G = 5 to 100 0.6 0.6 V/µs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error VOUT ±10 V
G = 1 0.04 0.01 %
G = 5 to 1000 0.3 0.1 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 10 RL ≥ 2 kΩ 10 10 ppm
G = 100 RL ≥ 2 kΩ 75 75 ppm
G = 1000 RL ≥ 2 kΩ 750 750 ppm
Gain vs. Temperature2
G = 1 TA = −40°C to +85°C 5 1 ppm/°C
TA = 85°C to 125°C 5 2 ppm/°C
G > 1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT VS = ±1.35 V to +36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Input Operating Voltage Range3 TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V
TA = +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V
TA = −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V
Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing
RL = 2 kΩ to Ground
TA = +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V
TA = +125°C −VS + 0.4 +VS – 1.0 −VS + 0.4 +VS – 1.0 V
TA = −40°C −VS + 1.2 +VS – 1.1 −VS + 1.2 +VS – 1.1 V
RL = 10 kΩ to Ground
TA = +25°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
TA = +125°C −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V
TA = −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
RL = 100 kΩ to Ground
TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V
Quiescent Current TA = +25°C 350 425 350 425 µA
TA = −40°C 250 325 250 325 µA
TA = +85°C 450 525 450 525 µA
TA = +125°C 525 600 525 600 µA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1 The input stage uses pnp transistors; therefore, input bias current always flows out of the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
AD8226
Rev. B | Page 5 of 28
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, T A = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = 0 V to 1.7 V
CMRR with DC to 60 Hz
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
CMRR with DC at 5 kHz
G = 1 80 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 100 100 dB
NOISE Total noise: eN = √(eNI2 + (eNO/G)2)
Voltage Noise 1 kHz
Input Voltage Noise, eNI 22 24 22 24 nV/√Hz
Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2.0 2.0 µV p-p
G = 10 0.5 0.5 µV p-p
G = 100 to 1000 0.4 0.4 µV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage: VOS = VOSI + (VOSO/G)
Input Offset, VOSI 200 100 µV
Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 µV/°C
Output Offset, VOSO 1000 500 µV
Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 µV/°C
Offset RTI vs. Supply (PSR) VS = 0 V to 1.7 V
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current1 TA = +25°C 5 20 27 5 20 27 nA
TA = +125°C 5 15 25 5 15 25 nA
TA = −40°C 5 30 35 5 30 35 nA
Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 0.5 nA
TA = +125°C 1.5 0.5 nA
TA = −40°C 1 0.1 nA
Average Temperature Coefficient TA =−40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 100 100 kΩ
IIN 7 7 µA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1 1500 1500 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
AD8226
Rev. B | Page 6 of 28
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time 0.01% 2 V step
G = 1 6 6 µs
G = 10 6 6 µs
G = 100 35 35 µs
G = 1000 350 350 µs
Slew Rate G = 1 0.4 0.4 V/µs
G = 5 to 100 0.6 0.6 V/µs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error
G = 1 VOUT = 0.8 V to 1.8 V 0.04 0.01% %
G = 5 to 1000 VOUT = 0.2 V to 2.5 V 0.3 0.1% %
Gain vs. Temperature2
G = 1 TA = −40°C to +85°C 5 1 ppm/°C
TA = +85°C to +125°C 5 2 ppm/°C
G > 1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT −VS = 0 V, +VS = 2.7 V to 36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Input Operating Voltage Range3 TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V
TA = −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V
TA = +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V
Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40
OUTPUT
Output Swing RL = 10 kΩ to 1.35 V,
TA = −40°C to +125°C
0.1 +VS − 0.1 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Single-supply operation 2.2 36 2.2 36 V
Quiescent Current TA = +25°C, −VS = 0 V, +VS = 2.7 V 325 400 325 400 µA
TA = −40°C, −VS = 0 V, +VS = 2.7 V 250 325 250 325 µA
TA = +85°C, −VS = 0 V, +VS = 2.7 V 425 500 425 500 µA
TA = +125°C, −VS = 0 V, +VS = 2.7 V 475 550 475 550 µA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1 Input stage uses pnp transistors; therefore, input bias current always flows out of the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
AD8226
Rev. B | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Maximum Voltage at −IN or +IN −VS + 40 V
Minimum Voltage at −IN or +IN +VS − 40 V
REF Voltage ±VS
Storage Temperature Range −65°C to +150°C
Specified Temperature Range −40°C to +125°C
Maximum Junction Temperature 140°C
ESD
Human Body Model 1.5 kV
Charge Device Model 1.5 kV
Machine Model 100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for a device in free air.
Table 5. Thermal Resistance
Package θJA Unit
8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W
8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W
ESD CAUTION
AD8226
Rev. B | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not t o Scal e)
07036-002
–IN
1
RG2
RG3
+IN 4
+VS
8
VOUT
7
REF
6
–VS
5
AD8226
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input.
2, 3 RG Gain-Setting Pins. Place a gain resistor between these two pins.
4 +IN Positive Input.
5 −VS Negative Supply.
6 REF Reference. This pin must be driven by low impedance.
7 VOUT Output.
8 +VS Positive Supply.
AD8226
Rev. B | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
160
140
120
100
80
60
40
20
0–900 –600 –300 0300 600 900
VOSO @ ±15V (µV)
HITS
07036-031
N: 2203
MEAN: 35.7649
SD: 229.378
Figure 3. Typical Distribution of Output Offset Voltage
240
210
180
150
120
90
60
30
0–9 –6 –3 0 3 6 9
V
OSO
DRIFT (µV)
HITS
07036-032
MEAN: –0.57
SD: 1.5762
Figure 4. Typical Distribution of Output Offset Voltage Drift
350
300
250
200
150
100
50
0–400 –200 0200 400
V
OSI
@ R
G
PINS @ ±15V (µV)
HITS
07036-033
MEAN: –3.67283
SD: 51.1
Figure 5. Typical Distribution of Input Offset Voltage
250
200
150
100
50
0–1.2 –0.9 –0.6 –0.3 00.3 0.6 0.9 1.2
V
OSI
DRIFT (µV)
HITS
07036-034
MEAN: 0.041
SD: 0.224
Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
180
150
120
90
30
60
018 20 22 24 26
POSIT I VE I
BIAS
CURRENT @ ±15V ( nA)
HITS
07036-035
MEAN: 21.5589
SD: 0.624
Figure 7. Typical Distribution of Input Bias Current
300
250
200
150
100
50
0–0.9 –0.6 –0.3 00.3 0.6 0.9
VOSI @ ±15V (nA)
HITS
07036-036
MEAN: 0.003
SD: 0.075
Figure 8. Typical Distribution of Input Offset Current
AD8226
Rev. B | Page 10 of 28
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 1
+0.02V, + 4.3V
+0.02V, –0.4V
+4.7V, + 1.9V
+2.5V, + 4.3V
+0.02V, + 3.0V
+0.02V, + 0.8V
+2.5V, –0.4V
+4.98V, + 0.8V
+4.98V, + 3.0V
–1
0
1
2
3
4
5
–0.5 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.55.0
COMMON-MODE VOLT AGE (V)
OUTPUT VOLTAGE (V)
V
REF
= 0V
07036-038
V
REF
= +1. 35V
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 1
0V, +4. 3V
–4.97V, + 1.8V
–4.97V, –3.0V
0V, –5.4V
+4.96V, –0.3V
+4.96V, + 1.8V
–6
–4
–2
0
2
4
6
–6 –4 –2 0 2 46
COMMON-MODE VOLT AGE (V)
OUTPUT VOLTAGE (V)
07036-039
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±5 V, G = 1
–0.5 00.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (V)
+0.02V, + 2.0V
+0.02V, –0.3V
+2.4V, + 0.8V
+1.35V, + 1.9V
+0.02V, + 1.3V
+0.02V, + 0.4V
+1.35, –0.3V
+2.67V, + 0.4V
+2.67V, + 1.3V
0
0.5
–0.5
1.0
1.5
2.0
2.5
COMMON-MODE VOLT AGE (V)
V
REF
= 0V
07036-040
V
REF
= +1. 35V
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 100
+0.02V, + 4.3V
+0.02V, –0.3V
+4.7V, + 1.9V
+2.5V, + 4.2V
+0.02V, + 3.0V
+0.02V, + 0.7V
+2.5V, –0.3.V
+4.96V, + 0.7V
+4.96V, + 3.0V
–1
0
1
2
3
4
5
–0.5 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.55.0
COMMON-MODE VOLT AGE (V)
OUTPUT VOLTAGE (V)
V
REF
= 0V
07036-041
V
REF
= +2. 5V
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 100
0V, +4. 2V
–4.96V, + 1.7V
–4.96V, –3.1V
0V, –5.3V
+4.96V, –3.1V
+4.96V, + 1.7V
–6
–4
–2
0
2
4
6
–6 –4 –2 0 2 46
OUTPUT VOLTAGE (V)
07036-042
COMMON-MODE VOLT AGE (V)
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±5 V, G = 100
AD8226
Rev. B | Page 11 of 28
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±15 V, G = 1
2.25 0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
INP UT CURRENT ( mA)
07036-044
VS = 2.7V
G = 1
–VIN = 0V
VOUT
IIN
Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V
16 0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
INP UT CURRENT ( mA)
07036-045
VS = ±15V
G = 1
–VIN = 0V VOUT
IIN
Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V
–14.95V, + 6.7V
–14.95V, –8.0V
+11.95V, + 5.2V
+11.95V, –6.5V
0V, +14. 2V
0V, +11. 2V
–11.95V, + 5.2V
–11.95V, –6.5V
0V, –15.4V
0V, –12.3V +14. 95V, –8.0V
+14.95V, + 6.7V
–20 –15 –10 –5 010515 20
COMMON-MODE VOLT AGE (V)
OUTPUT VOLTAGE (V)
VS = ±15V
07036-046
20
15
10
5
0
–5
–10
–20
–15
VS = ±12V
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±15 V, G = 100
2.25
2.50
2.75 0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
INP UT CURRENT ( mA)
07036-047
V
S
= 2.7V
G = 100
–V
IN
= 0V V
OUT
I
IN
Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V
16
0.5
0.6
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
INP UT CURRENT ( mA)
07036-048
VS = ±15V
G = 100
–VIN = 0V
VOUT
IIN
Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V
AD8226
Rev. B | Page 12 of 28
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
–0.5 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
COMMON-MODE VOLT AGE (V)
INP UT BIAS CURRE NT (nA)
07036-049
+4.22V
–0.15V
Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = +5 V
50
45
40
35
30
25
20
15
10
5
0
–5
–16 –12 –8 –4 04812 16
COMMON-MODE VOLT AGE (V)
INP UT BIAS CURRE NT (nA)
07036-050
–15.13V
+14.18V
Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V
160
140
120
100
80
60
40
20
0
0.1 110 100 1k 10k 100k 1M
FRE QUENCY (Hz )
POSIT I VE PSRR (dB)
07036-013
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 23. Positive PSRR vs. Frequency, RTI
160
140
120
100
80
60
40
20
0
0.1 110 100 1k 10k 100k 1M
FRE QUENCY (Hz )
NEGATIVE PSRR (dB)
07036-014
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 24. Negative PSRR vs. Frequency
70
60
50
40
30
20
10
0
–10
–20
–30
100 1k 10k 100k 1M 10M
FRE QUENCY (Hz )
GAIN (dB)
07036-015
V
S
= ±15V
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 25. Gain vs. Frequency, VS = ±15 V
70
60
50
40
30
20
10
0
–10
–20
–30
100 1k 10k 100k 1M 10M
FRE QUENCY (Hz )
GAIN (dB)
07036-016
V
S
= 2.7V
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 26. Gain vs. Frequency, 2.7 V Single Supply
AD8226
Rev. B | Page 13 of 28
160
140
120
100
80
60
40
20
0
0.1 110 100 1k 10k 100k
FRE QUENCY (Hz )
CMRR (dB)
07036-017
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
BANDWIDTH
LIMITED
Figure 27. CMRR vs. Frequency, RTI
120
100
80
60
40
20
0
0.1 110 100 1k 10k 100k
FRE QUENCY (Hz )
CMRR (dB)
07036-018
GAIN = 1000
GAIN = 1
GAIN = 100
GAIN = 10
BANDWIDTH
LIMITED
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0010 20 30 40 50 60 70 80 90 100 110 120
WARM-UP TIME (Seconds)
CHANGE IN INPUT OFFSET VOLTAGE (µV)
07036-011
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
35
30
25
20
15
10
150
125
100
75
50
25
0
5
–45 –30 –15 015 30 45 60 75 90 105 120 135
TEMPERATURE (°C)
INP UT BIAS CURRE NT (nA)
INP UT OF FSET CURRE NT (pA)
07036-012
V
S
= ±15V
V
REF
= 0V
–IN BIAS CURRENT
+IN BIAS CURRENT
OFFSE T CURRENT
Figure 30. Input Bias Current and Input Offset Current vs. Temperature
20
10
0
–10
–20
–30
–40
–50
–60
–70
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
GAIN ERROR ( µ V /V)
07036-051
NORM ALIZ E D AT 25°C
–0.4ppm/°C
–0.3ppm/°C
–0.6
ppm/°C
Figure 31. Gain Error vs. Temperature, G = 1
20
10
0
–10
–20
–30
–40
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
CMRR (µV/V)
07036-052
REPRESENTATIVE DATA
NORM ALIZ E D AT 25°C
0.2ppm/°C
–0.35ppm/°C
Figure 32. CMRR vs. Temperature, G = 1
AD8226
Rev. B | Page 14 of 28
+V
S
–0.2
–0.4
–0.6
–0.8
–V
S
–0.2
–0.4
–0.6
–0.82 4 6 8 10 12 14 16 18
SUPPLY VOLT AGE (±V
S
)
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VO L T AGES
07036-053
–40°C +25°C +85°C +105°C +125°C
Figure 33. Input Voltage Limit vs. Supply Voltage
+V
S
–0.1
–0.2
–0.3
–0.4
–V
S
+0.3
+0.2
+0.1
+0.4
2 4 6 8 10 12 14 16 18
SUPPLY VOLT AGE (±V
S
)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VO L T AGES
07036-054
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
+V
S
–0.8
–1.0
–1.2
–0.2
–0.4
–0.6
–V
S
+0.4
+0.2
+1.0
+0.8
+0.6
+1.2
2 4 6 8 10 12 14 16 18
SUPPLY VOLT AGE (±V
S
)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VO L T AGES
07036-055
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
15
10
5
0
–5
–10
–15
100 1k 10k 100k
LOAD RESI S TANCE (Ω)
OUTPUT VOLTAGE SWING (V)
07036-056
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 36. Output Voltage Swing vs. Load Resistance
+V
S
–V
S
–0.2
+0.2
–0.4
+0.4
–0.6
+0.6
–0.8
+0.8
10µ 100µ 1m 10m
OUTPUT CURRE NT (A)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VO L T AGES
07036-057
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 37. Output Voltage Swing vs. Output Current, G = 1
8G = 1
6
4
2
0
–2
–4
–6
–8
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
NONLINEARITY (2ppm/DIV)
07036-019
Figure 38. Gain Nonlinearity, G = 1, RL ≥ 2 kΩ
AD8226
Rev. B | Page 15 of 28
8
6
4
2
0
–2
–4
–6
–8
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
NONLINEARITY (2ppm/DIV)
07036-020
G = 10
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ
80
60
40
20
0
–20
–40
–60
–80
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
NONLINEARITY ( 20ppm/ DIV)
07036-021
G = 100
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ
800
600
400
200
0
–200
–400
–600
–800
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
NONLINEARITY ( 100ppm/ DIV)
07036-022
G = 1000
Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ
1k
100
10110 100 1k 10k 100k
FRE QUENCY (Hz )
NOISE (nV/ Hz)
07036-023
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
BANDWIDTH
LIMITED
Figure 42. Voltage Noise Spectral Density vs. Frequency
07036-024
1s/DIV
GAIN = 1000, 200nV/DIV
GAIN = 1, 1µ V /DIV
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
1k
100
10110 100 1k 10k
FRE QUENCY (Hz )
NOISE (fA/ Hz)
07036-058
Figure 44. Current Noise Spectral Density vs. Frequency
AD8226
Rev. B | Page 16 of 28
07036-025
1s/DIV
1.5pA/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise
0
3
6
9
12
15
18
21
24
27
30
1001k10k100k 1M
OUTPUT VOLTAGE (V p-p)
FREQUENCY (Hz)
V
S
= ±15V
V
S
= +5V
07036-059
Figure 46. Large-Signal Frequency Response
07036-060
40µs/DIV
25.38μs TO 0.01%
26.02µ s TO 0. 001%
0.002%/DIV
5V/DIV
Figure 47. Large-Signal Pulse Response and Settling Time,
G = 1, 10 V Step, VS = ±15 V
07036-061
40µs/DIV
15.46μs TO 0.01%
17.68µ s TO 0. 001%
0.002%/DIV
5V/DIV
Figure 48. Large-Signal Pulse Response and Settling Time,
G = 10, 10 V Step, VS = ±15 V
07036-062
100µs/DIV
39.64μs TO 0.01%
58.04µ s TO 0. 001%
0.002%/DIV
5V/DIV
Figure 49. Large-Signal Pulse Response and Settling Time,
G = 100, 10 V Step, VS = ±15 V
07036-063
400µs/DIV
349.6μs TO 0.01%
529.6µ s TO 0. 001%
0.002%/DIV
5V/DIV
Figure 50. Large-Signal Pulse Response and Settling Time,
G = 1000, 10 V Step, VS = ±15 V
AD8226
Rev. B | Page 17 of 28
07036-026
20mV/DIV 4µs/DIV
Figure 51. Small-Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF
07036-027
20mV/DIV 4µs/DIV
Figure 52. Small-Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF
07036-028
20mV/DIV 20µs/DIV
Figure 53. Small-Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF
07036-029
20mV/DIV 100µs/DIV
Figure 54. Small-Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF
AD8226
Rev. B | Page 18 of 28
07036-030
20mV/DIV
R
L
= 147pF
R
L
= 100pF
R
L
= 47pF
NO LOAD
4µs/DIV
Figure 55. Small-Signal Response with Various Capacitive Loads,
G = 1, RL = ∞
07036-064
2
60
50
40
30
20
10
046810
STEP SIZE (V)
SETTLING TIME (µs)
12 14 16 18 20
SETTLED TO 0.01%
SETTLED TO 0.001%
Figure 56. Settling Time vs. Step Size, VS = ±15 V Dual Supplies
340
330
320
310
300
2900 2 4 6 8 10 12 14 16 18
SUPPLY VOLT AGE (±V
S
)
SUPP LY CURRENT ( µ A)
07036-066
Figure 57. Supply Current vs. Supply Voltage
AD8226
Rev. B | Page 19 of 28
THEORY OF OPERATION
A3
R2
24.7kΩ
R1
24.7kΩ
A1 A2 Q2Q1 –IN
+IN
+V
S
–V
S
R3
50kΩ
R4
50kΩ
R5
50kΩ
R
B
R
B
+V
S
–V
S
V
OUT
REF
07036-003
NODE 1
NODE 2
R
G
V
BIAS
+V
S
–V
S
+V
S
–V
S
NODE 4NODE 3
R6
50kΩ
DIFFERENCE
AMPLIFIER STAGEGAIN STAGE
ESD AND
OVERVOLTAGE
PROTECTION
ESD AND
OVERVOLTAGE
PROTECTION
–V
S
Figure 58. Simplified Schematic
ARCHITECTURE
The AD8226 is based on the classic 3-op-amp topology. This
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Figure 58 shows a simplified schematic
of the AD8226.
The first stage works as follows: in order to maintain a constant
voltage across the bias resistor RB, A1 must keep Node 3 a con-
stant diode drop above the positive input voltage. Similarly, A2
keeps Node 4 at a constant diode drop above the negative input
voltage. Therefore, a replica of the differential input voltage is
placed across the gain-setting resistor, RG. The current that
flows across this resistance must also flow through the R1
and R2 resistors, creating a gained differential signal between
the A2 and A1 outputs. Note that, in addition to a gained
differential signal, the original common-mode signal, shifted
a diode drop up, is also still present.
The second stage is a difference amplifier, composed of A3 and
four 50 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The transfer function of the AD8226 is
VOUT = G(VIN+ − VIN−) + VREF
where:
G
R
GkΩ49.4
1+=
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8226, which can be calculated by referring to Table 7 or by
using the following gain equation:
1
kΩ49.4
−
=
G
RG
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω) Calculated Gain
49.9 k 1.990
12.4 k 4.984
5.49 k 9.998
2.61 k 19.93
1.00 k 50.40
499 100.0
249 199.4
100 495.0
49.9 991.0
The AD8226 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8226 specifications to determine the total gain accu-
racy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
If a gain of 5 is required and minimal gain drift is important,
consider using the AD8227. The AD8227 has a default gain of 5
that is set with internal resistors. Because all resistors are internal,
the gain drift is extremely low (<5 ppm/°C maximum).
AD8226
Rev. B | Page 20 of 28
REFERENCE TERMINAL
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8226 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For the best performance, source impedance to the REF
terminal should be kept below 2 Ω. As shown in Figure 58,
the reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2(50 kΩ + RREF)/(100 kΩ + RREF).
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
INCORRECT
V
CORRECT
AD8226
OP1177
+
–
V
07036-004
REF
AD8226
REF
Figure 59. Driving the Reference Pin
INPUT VOLTAGE RANGE
Figure 9 through Figure 15 and Figure 18 show the allowable
common-mode input voltage ranges for various output voltages
and supply voltages. The 3-op-amp architecture of the AD8226
applies gain in the first stage before removing common-mode
voltage with the difference amplifier stage. Internal nodes between
the first and second stages (Node 1 and Node 2 in Figure 58)
experience a combination of a gained signal, a common-mode
signal, and a diode drop. This combined signal can be limited
by the voltage supplies even when the individual input and
output signals are not limited.
For most applications, Figure 9 through Figure 15 and Figure 18
provide sufficient information to achieve a good design. For
applications where a more detailed understanding is needed,
Equation 1 to Equation 3 can be used to understand how the
gain (G), common-mode input voltage (VCM), differential input
voltage (VDIFF), and reference voltage (VREF) interact. The values for
the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, are shown in Table 8.
These three formulas, along with the input and output range
specifications in Table 2 and Table 3, set the operating boundaries
of the part.
LIMIT
S
DIFF
CM
VV
GV
V
−
+−>−
2
))((
(1)
LIMIT
S
DIFF
CM VV
GV
V+
−+<
+
2
))((
(2)
LIMITREF
S
REF
CM
DIFF
VV
VV
GV
_
2
2
))((
−+<
++
(3)
Table 8. Input Voltage Range Constants for Various
Temperatures
Temperature V
−LIMIT
V
+LIMIT
V
REF_LIMIT
−40°C −0.55 V 0.8 V 1.3 V
+25°C −0.35 V 0.7 V 1.15 V
+85°C −0.15 V 0.65 V 1.05 V
+125°C −0.05 V 0.6 V 0.9 V
Performance Across Temperature
The common-mode input range shifts upward with temper-
ature. At cold temperatures, the part requires extra headroom
from the positive supply, and operation near the negative supply
has more margin. Conversely, hot temperatures require less
headroom from the positive supply, but are the worst-case
conditions for input voltages near the negative supply.
Recommendation for Best Performance
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
If the application requirements exceed the boundaries, one
solution is to apply less gain with the AD8226, and then apply
additional gain later in the signal chain. Another option is to
use the pin-compatible AD8227.
LAYOUT
To ensure optimum performance of the AD8226 at the PCB
level, care must be taken in the design of the board layout.
The AD8226 pins are arranged in a logical manner to aid in
this task.
8
7
6
5
1
2
3
4
–IN
R
G
R
G
+V
S
V
OUT
REF
–V
S
+IN
TOP VIEW
(Not t o Scal e)
AD8226
07036-005
Figure 60. Pinout Diagram
AD8226
Rev. B | Page 21 of 28
Common-Mode Rejection Ratio Over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resistance
in the input path (for example, for input protection) should be
placed close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain-setting pins can also affect
CMRR over frequency. If the board design has a component
at the gain-setting pins (for example, a switch or jumper), the
part should be chosen so that the parasitic capacitance is as
small as possible.
Power Supplies
A stable dc voltage should be used to power the instrumentation
amplifier. Note that noise on the supply pins can adversely affect
performance. For more information, see the PSRR performance
curves in Figure 23 and Figure 24.
A 0.1 µF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 61, a 10 µF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
AD8226
+VS
+IN
–IN
LOAD
REF
0.1µF 10µF
0.1µF 10µF
–VS
VOUT
07036-006
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8226 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 62.
THERMOCOUPLE
+VS
REF
–VS
AD8226
CAPACITIVE LY COUP LED
+VS
REF
C
C
–VS
AD8226
TRANSFORMER
+VS
REF
–VS
AD8226
INCORRECT
CAPACITIVE LY COUP LED
+VS
REF
C
R
R
C
–VS
AD8226
1
fHIGH-PASS = 2πRC
THERMOCOUPLE
+VS
REF
–VS
10MΩ
AD8226
TRANSFORMER
+VS
REF
–VS
AD8226
CORRECT
07036-007
Figure 62. Creating an IBIAS Path
AD8226
Rev. B | Page 22 of 28
INPUT PROTECTION
The AD8226 has very robust inputs and typically does not
need additional input protection. Input voltages can be up to
40 V from the opposite supply rail. For example, with a +5 V
positive supply and a −8 V negative supply, the part can safely
withstand voltages from −35 V to 32 V. Unlike some other
instrumentation amplifiers, the part can handle large differen-
tial input voltages even when the part is in high gain. Figure 16,
Figure 17, Figure 19, and Figure 20 show the behavior of the
part under overvoltage conditions.
The rest of the AD8226 terminals should be kept within the
supplies. All terminals of the AD8226 are protected against ESD.
For applications where the AD8226 encounters voltages beyond
the allowed limits, external current-limiting resistors and low-
leakage diode clamps such as the BAV199L, the FJH1100s, or
the SP720 should be used.
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instru-
mentation amplifier, as shown in Figure 63. The filter limits the
input signal bandwidth according to the following relationship:
)2(π2
1
C
D
DIFF CCR
uencyFilterFreq +
=
C
CM
RC
uencyFilterFreq π2
1
=
where CD ≥ 10 CC.
R
R
AD8226
+V
S
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–V
S
R
G
C
D
10nF
C
C
1nF
C
C
1nF
4.02kΩ
4.02kΩ
07036-008
Figure 63. RFI Suppression
CD affects the difference signal and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the R × CC
at the negative input degrades the CMRR of the AD8226. By using
a value of CD that is one magnitude larger than CC, the effect of
the mismatch is reduced and performance is improved.
AD8226
Rev. B | Page 23 of 28
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE
+IN
–IN
REF
AD8226
V
BIAS
R
+
–
OP AMP
+OUT
–OUT
07036-009
R
RECO M M E NDE D OP AMPS: AD8515, AD8641, AD820.
RECO M M E NDE D R VAL UE S : 5kΩ to 20kΩ.
Figure 64. Differential Output Using an Op Amp
Figure 64 shows how to configure the AD8226 for differ-
ential output.
The differential output is set by the following equation:
VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−)
The common-mode output is set by the following equation:
VCM_OUT = (VOUT+ − VOUT−)/2= VBIAS
The advantage of this circuit is that the dc differential accuracy
depends on the AD8226, not on the op amp or the resistors. In
addition, this circuit takes advantage of the precise control that the
AD8226 has of its output voltage relative to the reference voltage.
Although the dc performance and resistor matching of the op amp
affect the dc common-mode output accuracy, such errors are
likely to be rejected by the next device in the signal chain and
therefore typically have little effect on overall system accuracy.
Tips for Best Differential Output Performance
For best ac performance, an op amp with at least a 2 MHz gain
bandwidth and a 1 V/µs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, and AD820.
Keep trace lengths from the resistors to the inverting terminal
of the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
For best linearity and ac performance, a minimum positive
supply voltage (+VS) is required. Table 9 shows the minimum
supply voltage required for optimum performance. In this mode,
VCM_MAX indicates the maximum common-mode voltage expected
at the input of the AD8226.
Table 9. Minimum Positive Supply Voltage
Temperature Equation
Less than −10°C +V
S
> (V
CM_MAX
+ V
BIAS
)/2 + 1.4 V
−10°C to 25°C +VS > (VCM_MAX + VBIAS)/2 + 1.25 V
More than 25°C +VS > (VCM_MAX + VBIAS)/2 + 1.1 V
AD8226
Rev. B | Page 24 of 28
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8226
make it an excellent candidate for performing bridge measure-
ments. The bridge can be connected directly to the inputs of the
amplifier (see Figure 65).
5V
2.5V
10µF 0.1µF
AD8226
+IN
–IN
R
G
350Ω
350Ω350Ω
350Ω
+
–
07036-010
Figure 65. Precision Strain Gage
DRIVING AN ADC
Figure 66 shows several methods for driving an ADC. The
ADuC7026 microcontroller was chosen for this example because it
contains ADCs with an unbuffered, charge-sampling architecture
that is typical of most modern ADCs. This type of architecture
typically requires an RC buffer stage between the ADC and
amplifier to work correctly.
Option 1 shows the minimum configuration required to drive
a charge-sampling ADC. The capacitor provides charge to the
ADC sampling capacitor while the resistor shields the AD8226
from the capacitance. To keep the AD8226 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 µs.
This circuit is mainly useful for lower frequency signals.
Option 2 shows a circuit for driving higher speed signals. It uses a
precision op amp (AD8616) with relatively high bandwidth and
output drive. This amplifier can drive a resistor and capacitor with
a much higher time constant and is therefore suited for higher
frequency applications.
Option 3 is useful for applications where the AD8226 needs to
run off a large voltage supply but drive a single-supply ADC.
In normal operation, the AD8226 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8226 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
the circuit, however, because the 10 kΩ resistor between the two
amplifiers limits the current into the AD8616 to a safe level.
AD8226
REF 100nF
100Ω
10kΩ
10Ω
10nF
ADC0
ADC1
ADC2
AGND
3.3V 3.3V
3.3V
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
OPTION 3: PROTECTINGADC FROM LARGE VOLTAGES
3.3V
AD8226 AD8616
ADuC7026
REF
3.3V
10Ω
10nF
AD8226 AD8616
REF
+15V
–15V
AV
DD
07036-065
Figure 66. Driving an ADC
AD8226
Rev. B | Page 25 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DES
IGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8226ARMZ −40°C to +125°C 8-Lead MSOP RM-8 Y18
AD8226ARMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y18
AD8226ARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y18
AD8226ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8226ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8226ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8226BRMZ −40°C to +125°C 8-Lead MSOP RM-8 Y19
AD8226BRMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y19
AD8226BRMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y19
AD8226BRZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8226BRZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8226BRZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1 Z = RoHS Compliant Part.
AD8226
Rev. B | Page 26 of 28
NOTES
AD8226
Rev. B | Page 27 of 28
NOTES
AD8226
Rev. B | Page 28 of 28
NOTES
©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07036-0-3/11(B)