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Interfacing the AD1890/AD1891 to AES/EBU Receivers and Digital Filters
by Hank Zumbahlen, Senior Field Applications Engineer
AN-399
APPLICATION NOTE
ONE TECHNOLOGY WAY
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NORWOOD, MASSACHUSETTS 02062-9106
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617/329-4700
ABSTRACT
The AES/EBU AES3-199X and the IEC-958 have become
the standard for interfacing digital audio components in
the digital domain. The AD1890/AD1891 Asynchronous
Sample Rate Converter (ASRC) is a device that pro-
vides a solution to sample rate interfacing and
compatibility issues. The practice of using oversampling
the digital signal before it goes to the digital-to-analog
converter has become standard as well. This paper
examines the issues with interfacing these components.
THE AES/EBU INPUT
Even though the resolution of commercial digital audio
sources, the Compact Disc (CD) and Digital Audio Tape
(DAT), is 16 bits, the AES/EBU interface has space for 20
bits of data, out of a total frame size of 32 bits. The
format for the subframe is shown in Figure 1. This
allows higher resolution in professional applications.
Therefore, since the data will not fill up the entire width
of the word, the data must be padded. This padding can
either be before or after the data word. If it is placed
before the data, the LSB (Least Significant Bit) is in the
32nd clock position. This is referred to as right-justified
data. If the padding is placed after the data, the MSB
(Most Significant Bit) is in the first clock position. This is
referred to as left-justified data.
PREAMBLE AUX
DATA AUDIO DATA VUCP
L
S
B
M
S
B
BIT 0 3 4 7 8
PREAMBLE – INDENTIFIES RIGHT OR LEFT CHANNEL AND START OF BLOCK
AUX DATA – AUDIO DATA IF DATA WORD GREATER THAN 20 BITS
– OPEN FOR OTHER APPLICATIONS IF DATA WORD IS
LESS THAN 20 BITS
V – VALIDITY BIT 0 = VALID DATA
U – USER DATA BIT UNDEFINED
C – CHANNEL STATUS BIT
P – PARITY BIT GENERATES EVEN PARITY
27 28 29 30 31
Figure 1a. Audio Subframe Format
The problem arises when you try to mate a component
that right justifies the data with one that expects left-
justified data. This is the case when trying to mate the
AD1890/AD1891 with the Yamaha YM3623B receiver
chip. The Crystal CS8412 allows the user to select which
data format is to be used. These two chips are by far the
most popular solutions at this point in time.
The standard digital audio signal set consists of the data,
which is alternated between the left and right channels,
a signal to indicate whether it is the left or right channel
(L/R), a bit clock and a word clock which indicates valid
data. It is by moving the L/R clock that we can change the
justification of the data.
Assume that we have 16 bits of right-justified data,
which is the case with the Yamaha part. That would
mean that we would have 16 leading zeros. By delaying
the L/R clock, outputted by the receiver chip, by the word
clock, also an output from the receiver chip, we delay the
L/R clock by a quarter cycle. The L/R signal will now
change state at the beginning of valid output data, which
in effect changes the data to left justification. This
delaying of the L/R clock is done simply with a D type
flip-flop (see Figure 2). The timing signals are given in
Figure 3.
ACH A
DATA BSB
CH B
DATA CH A
DATA CH B
DATA
END OF
STATUS BLOCK START OF
STATUS BLOCK
FRAME 191
PREAMBLE A – INDICATES CH A DATA
B – INDICATES CH B DATA
S – INDICATES CH A DATA AND START OF
STATUS BLOCK
PREAMBLE
SUB
FRAME
SUB
FRAME FRAME 0
Figure 1b. Audio Block Format