REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A Add vendor CAGE 75569. Technical changes throughout. - mbk 92-02-10 M. A. Frye
B Update the boilerplate to the current requirements of MIL-PRF-38535.
- JAK 07-12-17 Thomas M. Hess
C Correct test condition for total power supply current (ICC) and add
footnote 6/ in table I. Update boilerplate paragraphs to current
MIL-PRF-38535 requirements. – MAA. 10-08-11 Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS REV C C C C C C C C C C C C C C
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Monica L. Poelking
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 4321 8-3990
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Monica L. Poelking
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Wm J. Johnson
MICROCIRCUIT, DIGITAL, FAST CMOS,
8-BIT LATCHED TRANSCEIVER,
MONOLITHIC SILICON
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
90-03-13
AMSC N/A
REVISION LEVEL
C
SIZE
A
CAGE CODE
67268
5962-89730
SHEET 1 OF 14
DSCC FORM 2233
APR 97 5962-E276-10
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-89730 01 K A
Drawing number Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01 54FCT543 8-bit octal latched transceiver, non-inverting,
with three-state outputs, TTL compatible
02 54FCT543A 8-bit octal latched transceiver, non-inverting,
with three-state outputs, TTL compatible
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
K GDIP1-T24 or CDIP2-T24 24 Dual-in-line
L GDFP1-F24 or CDFP2-F24 24 Flat pack
3 CQCC1-N28 28 Square leadless chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings. 1/
Supply voltage range (VCC) ..................................................................... -0.5 V dc to +7.0 V dc
input voltage range (VIN) ......................................................................... -0.5 V dc to VCC + 0.5 V dc
Output and I/O voltage range (VOUT) ....................................................... -0.5 V dc to VCC + 0.5 V dc 2/
DC input diode current (IIK) ..................................................................... 20 mA
DC output diode current (IOK) .................................................................. 50 mA
DC output current ................................................................................... 100 mA
Maximum power dissipation (PD) ............................................................ 500 mW 3/
Storage temperature range (TSTG) .......................................................... -65C to +150C
Lead temperature (soldering, 10 seconds) ............................................. +300C
Thermal resistance, junction-to-case (JC) .............................................. See MIL-STD-1835
Junction temperature (TJ) ....................................................................... +175C
1.4 Recommended operating conditions.
Supply voltage range (VCC) ..................................................................... +4.5 V dc to +5.5 V dc
Maximum low level input voltage (VIL)..................................................... 0.8 V dc
Minimum high level input voltage (VIH) .................................................... 2.0 V dc
Output voltage range (VOUT) .................................................................... 0.0 V to VCC
Case operating temperature range (TC) .................................................. -55C to +125C
1/ All voltages are referenced to ground.
2/ For VCC ≥ 6.5 V dc, the upper bound is limited to VCC.
3/ Must withstand the added PD due to short circuit test, IOS.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 3
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to
MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and
qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management
(QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the
device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with
MIL-PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 4
DSCC FORM 2234
APR 97
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full (case or ambient) operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD
PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test Symbol Conditions
-55C TC +125C
unless otherwise specified 1/
Group A
subgroups
Device
types Limits Unit
Min Max
High level output
voltage
VOH
VCC = 4.5 V, VIL = 0.8 V
VIH = 2.0 V
IOH = -300 A 1, 2, 3 All 4.3 V
IOH = -12 mA 2.4
Low level output
voltage
VOL
VCC = 4.5 V, VIL = 0.8 V
VIH = 2.0 V
IOH = 300 A 1, 2, 3 All 0.2 V
IOH = 48 mA 0.55
Input clamp voltage VIK V
CC = 4.5 V, IIN = -18 mA 1 All -1.2 V
High level input
current
IIH1 V
CC = 5.5 V, VIN = 5.5 V, (except I/O pins) 1, 2, 3 All 5.0 A
I
IH2 V
CC = 5.5 V, VIN = 5.5 V, (I/O pins only) 1, 2, 3 All 15.0 A
Low level input
current
IIL1 V
CC = 5.5 V, VIN = 5.5 V, (except I/O pins) 1, 2, 3 All -5.0 A
I
IL2 V
CC = 5.5 V, VIN = 5.5 V, (I/O pins only) 1, 2, 3 All -15.0 A
Short circuit output
current
IOS
1/
VCC = 4.5 V, VOUT = GND 1, 2, 3 All 60 mA
Quiescent power
supply current
(CMOS inputs)
ICCQ
VIN 0.2 V or VIN 5.3 V
VCC = 5.5 V, fi = fCP = 0 MHz
1, 2, 3 All 1.5 mA
Quiescent power
supply current
(TTL inputs)
ICC
2/
VCC = 5.5 V
VIN = 3.4 V
1, 2, 3 All 1.5 mA
Dynamic power
supply current
ICCD
3/
VCC = 5.5 V, VIN 5.3 V or VIN 0.2 V
Outputs open, One bit toggling, 50% duty cycle
CEAB
= OEAB
= GND, CEBA
= VCC
1, 2, 3 All 0.25 mA/
MHz
Total power
supply current
ICC
4/ 6/
VCC = 5.5 V,
fCP = LEAB
= 10 MHz
Outputs open, 50% duty cycle
One bit toggling at fi = 5 MHz
CEAB
= OEAB
= GND, CEBA
= VCC
VIN 5.3 V or
VIN 0.2 V
1, 2, 3 All 4.0 mA
VIN =3.4 V or
VIN = GND
1, 2, 3 All 6.0 mA
VCC = 5.5 V,
fCP = LEAB
= 10 MHz
Outputs open, 50% duty cycle
Eight bits toggling at fi = 5 MHz
CEAB
= OEAB
= GND, CEBA
= VCC
VIN 5.3 V or
VIN 0.2 V
1, 2, 3 All 12.8
7/
mA
VIN =3.4 V or
VIN = GND
1, 2, 3 All 21.8
7/
mA
see footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55C TC +125C
unless otherwise specified
1/
Group A
subgroups
Device
types
Limits
Unit
Min Max
Functional test See 4.3.1d 7, 8 All
Input capacitance CIN See 4.3.1c 4 All 10 pF
I/O capacitance CI/O See 4.3.1c 4 All 12 pF
Propagation delay
time, transparent
mode, An to Bn,
Bn to An
tPHL1,
tPLH1
5/
RL = 500
CL = 50 pF
See figure 4
9, 10, 11 01 2.5 10.0 ns
02 2.5 7.5
Propagation delay
time, LEBA
to An,
LEAB
to Bn
tPHL2,
tPLH2
RL = 500
CL = 50 pF
See figure 4
9, 10, 11 01 2.5 14.0 ns
02 2.5 9.0
Output enable time,
OEBA
or OEAB
to
An or Bn, CEBA
or
CEAB
to An or Bn
tPZH,
tPZL
RL = 500
CL = 50 pF
See figure 4
9, 10, 11 01 2.0 14.0 ns
02 2.0 10.0
Output disable time,
OEBA
or OEAB
to
An or Bn, CEBA
or
CEAB
to An or Bn
tPHZ,
tPLZ
RL = 500
CL = 50 pF
See figure 4
9, 10, 11 01 2.0 13.0 ns
02 2.0 8.5
Setup time, An to
LEBA
to LEAB
, Bn
to LEBA
to LEAB
ts
9, 10, 11 01 3.0 ns
02 2.0
Hold time, An to
LEBA
to LEAB
, Bn
to LEBA
to LEAB
th
9, 10, 11 01 2.0 ns
02 2.0
Pulse width
LEBA
to LEAB
tw
9, 10, 11 01 5.0 ns
02 5.0
1/ Not more than one output should be shorted at one time and the duration of the short circuit condition shall not exceed
1 second.
2/ TTL driven input, VIN = 3.4 V, all other inputs at VCC or GND.
3/ This parameter is not directly testable, but is derived for use in total power supply calculations.
4/ ICC = ICCQ + (ICC X DH x NT)+(ICCD x fi x Ni)
Where: DH = Duty cycle for TTL inputs high; NT = Number of TTL inputs at DH
f
i = Input frequency in MHz; Ni = Number of inputs at fi
5/ The minimum limits for the propagation delay times are guaranteed, if not tested, to the limits specified in table I.
6/ For total current supply (ICCT) test in an ATE environment, the effect of parasitic output capacitive loading from the test
environment must be taken into account, as its effect is not intended to be included in the test results. The impact must be
characterized and appropriate offset factors must be applied to the test result.
7/ These limits are guaranteed but not tested.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 7
DSCC FORM 2234
APR 97
Device type 01 and 02
Case outline K and L 3
Terminal number Terminal symbol Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
OEAB
LEAB
B7
B6
B5
B4
B3
B2
B1
B0
CEBA
VCC
- - -
- - -
- - -
- - -
NC
LEBA
OEBA
A0
A1
A2
A3
NC
A4
A5
A6
A7
CEAB
GND
NC
OEAB
LEAB
B7
B6
B5
B4
NC
B3
B2
B1
B0
CEBA
VCC
Terminal symbol Terminal description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0 - A7
B0 - B7
A-to-B output enable input (active low)
B-to-A output enable input (active low)
A-to-B enable input (active low)
B-to-A enable input (active low)
A-to-B latch enable input (active low)
B-to-A latch enable input (active low)
A-to-B data inputs to B-to-A three-state outputs
B-to-A data inputs to A-to-B three-state outputs
FIGURE 1. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 8
DSCC FORM 2234
APR 97
Inputs Latch status Output buffers
CEAB
LEAB
OEAB
A to B
B0 - B7
H X X Storing High Z
X H - Storing -
X - H - High Z
L L L Transparent Current A inputs
L H L Storing *Previous A inputs
H = High voltage level
L = Low voltage level
X = Irrelevant
* = Before LEAB low-to-high transition.
A-to-B data flow shown: B-to-A flow control is the same except using CEBA, LEBA, and OEBA.
FIGURE 2. Truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 9
DSCC FORM 2234
APR 97
FIGURE 3. Logic diagram.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 10
DSCC FORM 2234
APR 97
FIGURE 4. Test circuit and switching waveforms.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
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DSCC FORM 2234
APR 97
FIGURE 4. Test circuit and switching waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 12
DSCC FORM 2234
APR 97
Test Switch
tPLZ Closed
tPZL Closed
Open drain Closed
All other Open
1. CL includes probe and jig capacitance.
2. RT = termination resistance and should be equal to ZOUT of the pulse generator.
3. tr = tf = 2.5 ns (10% to 90%), unless otherwise specified.
FIGURE 4. Test circuit and switching waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 13
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
TABLE II. Electrical test requirements.
MIL-STD-883 test requirements Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004)
- - -
Final electrical test parameters
(method 5004)
1*, 2, 3, 7, 8, 9, 10, 11
Group A test requirements
(method 5005)
1, 2, 3, 7, 8, 9, 10, 11
Groups C and D end-point
electrical parameters
(method 5005)
1, 2, 3
* PDA applies to subgroup 1.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-
883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CIN and CI/O measurements) shall be measured only for the initial test and after process or design
changes which may affect input capacitance. Capacitance shall be measured between the designated terminal and
GND at a frequency of 1 MHz. Test all applicable pins on 5 devices with zero failures.
d. Subgroups 7 and 8 shall include verification of the truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89730
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
C
SHEET 14
DSCC FORM 2234
APR 97
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1005 of MIL-STD-883.
(2) TA = +125C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be
used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices
(FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in
MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and
accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-08-11
Approved sources of supply for SMD 5962-89730 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-89730013A 0C7V7 IDT54FCT543LB
5962-8973001KA 0C7V7 IDT54FCT543EB
5962-8973001LA 0C7V7 IDT54FCT543DB
5962-89730023A 0C7V7 IDT54FCT543ALB
5962-8973002KA 0C7V7 IDT54FCT543AEB
5962-8973002LA 0C7V7 IDT54FCT543ADB
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
