74HC193D,652 - NXP - Datasheet.Directory

1. General description

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate

up/down clocks, CPU and CPD respectively, simplify operation. The output s change state

synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is

pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while

CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at

any time to guarantee predict able behaviour . The device can be cleared at any time by the

asynchronous master reset input (MR); it may also be loaded in parallel by activating the

asynchronous parallel load input (PL). The terminal count up (TCU) and terminal coun t

down (TCD) outputs are normally HIGH. When the circuit has reached the maximum

count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.

TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,

the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.

The terminal count outputs can be used as the clock input signals to the next higher order

circuit in a multistage counter, since they duplicate the clock waveforms. Multistage

counters will not be fully synchronous, since there is a slight delay time difference added

for each stage that is added. The counter may be preset by the asynchronous parallel

load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is

loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the

conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on

the master reset (MR) input will disable the parallel load gates, override both clock inputs

and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a

reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted

as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the

use of current limit ing res ist ors to interface inputs to voltages in excess of VCC.

2. Features and benefits

Input levels:

For 74HC193: CMOS level

For 74HCT193: TTL level

Synchronous reversible 4-bit binary counting

Asynchronous parallel load

Asynchronous reset

Expandable without external logic

Complies with JEDEC standard no. 7A

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 20 0 V.

74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Rev. 4 — 24 June 2013 Product data sheet

Product data sheet Rev. 4 — 24 June 2013 2 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Multiple package options

Specified from 40 C to +85 C and 40 C to +125 C.

3. Ordering information

4. Functional diagram

Tabl e 1. Ordering information

Type number Package

Temperature

range Name Description Version

74HC193D 40 C to +125 C SO16 plastic small outline package; 16 leads;

body width 3.9 mm SOT109-1

74HC193DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm SOT338-1

74HC193N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HC193PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

74HCT193D 40 C to +125 C SO16 plastic small outline package; 16 leads;

body width 3.9 mm SOT109-1

74HCT193DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm SOT338-1

74HCT193N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HCT193PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

Fig 1. Functiona l dia g ram Fig 2. Logic symb ol

001aag405

FLIP-FLOPS

COUNTER

11 CPU

5TCD 13

TCU 12

3267

151109

Q1 Q2 Q3

D0 D1 D2 D3

CPD

001aag409

MR Q0 Q1 Q2 Q3

PL D0 D1 D2 D3

143267

11151109

4CPD TCD

TCU5

12CPU

Product data sheet Rev. 4 — 24 June 2013 3 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Fig 3. IEC logic symbol

CTR4

2CT = 0

1CT = 15

001aag410

4G1

11 C3

14 R

1−

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Product data sheet Rev. 4 — 24 June 2013 4 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Fig 4. Logic diagram

001aag412

D0 D1 D2 D3

Q0 Q1 Q2 Q3

TCD

CPU

CPD

FF1

RD Q

FF2

RD Q

FF3

RD Q

FF4

RD Q

TCU

Product data sheet Rev. 4 — 24 June 2013 5 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

5. Pinning information

5.1 Pinning

5.2 Pin description

[1] LOW-to-HIGH, edge triggered.

Fig 5. Pin configurati on SO16 Fig 6. Pin configurat i on TS SOP1 6

and SSOP16 Fig 7. Pin configuration DIP16

D1 V

Q1 D0

Q0 MR

CPD TCD

CPU TCU

Q2 PL

Q3 D2

GND D3

001aag406

74HC193

74HCT193

74HC193

74HCT193

D1 V

Q1 D0

Q0 MR

CPD TCD

CPU TCU

Q2 PL

Q3 D2

GND D3

001aag407

74HC193

74HCT193

D1 VCC

Q1 D0

Q0 MR

CPD TCD

CPU TCU

Q2 PL

Q3 D2

GND D3

001aaf408

Table 2. Pin description

Symbol Pin Description

D0 15 data input 0

D1 1 data input 1

D2 10 data input 2

D3 9 data input 3

Q0 3 flip-flop output 0

Q1 2 flip-flop output 1

Q2 6 flip-flop output 2

Q3 7 flip-flop output 3

CPD 4 count down clock input[1]

CPU 5 count up clock input[1]

GND 8 ground (0 V)

PL 11 asynchronous parallel load input (active LOW)

TCU 12 terminal count up (carry) output (active LOW )

TCD 13 terminal count down (borrow) output (active LOW)

MR 14 asynchronous master reset input (active HIGH)

VCC 16 supply voltage

Product data sheet Rev. 4 — 24 June 2013 6 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

6. Functional description

[1] H = HIGH voltage level

L = LOW voltage level

X = don’t care

 = LOW-to-HIGH clock transition.

[2] TCU = CPU at terminal count up (HHHH)

[3] TCD = CPD at terminal count down (LLLL).

Table 3. Function table[1]

Operating mode Inputs Outputs

MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD

Reset (clear) HXXLXXXXLLLLHL

HXXHXXXXLLLLHH

Parallel load LLXLLL LLLLLLHL

LLXHLLLLLLLLHH

LLLXHHHHHHHHLH

LLHXHHHHHHHHHH

Count up L H H X X X X count up H[2] H

Count down L H H X X X X count down H H[3]

Product data sheet Rev. 4 — 24 June 2013 7 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

(1) Clear overrides load, data and count inputs.

(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input

(CPU) must be HIGH.

Sequence

Clear (reset outputs to zero);

load (preset) to binary thirteen;

count up to fourteen, fifteen, terminal count up, zero, one and two;

count down to one, zero, terminal count down, fifteen, fourteen and thirteen.

Fig 8. Typical clear, load and count sequence

001aag411

COUNT UP COUNT DOWN

013

CLEAR PRESET

1 0 15 14 1314 15 0 1 2

MR(1)

CPU(2)

CPD(2)

TCU

TCD

Product data sheet Rev. 4 — 24 June 2013 8 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP16 packages: above 70 C the value of Ptot derates linearly at 12 mW/K.

For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.

For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.

8. Recommended operating conditions

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7.0 V

IIK input clamping current VI < 0.5 V or VI>V

CC + 0.5 V [1] -20 mA

IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] -20 mA

IOoutput curren t VO= 0.5 V to VCC + 0.5 V - 25 mA

ICC supply current - 50 mA

IGND ground current - 50 mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation DIP16 package [2] -750mW

SO16 package [2] -500mW

SSOP16 package [2] -500mW

TSSOP16 package [2] -500mW

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

74HC193

VCC supply voltage 2.0 5.0 6.0 V

VIinput voltage 0- V

CC V

VOoutput voltage 0 - VCC V

Tamb ambient temperature 40 +25 +125 C

t/V input transition rise and

fall rate VCC = 2.0 V - - 625 ns/V

VCC = 4.5 V - 1.67 139 ns/V

VCC = 6.0 V --83ns/V

74HCT193

VCC supply voltage 4.5 5.0 5.5 V

VIinput voltage 0- V

CC V

VOoutput voltage 0 - VCC V

Tamb ambient temperature 40 +25 +125 C

t/V input transition rise and

fall rate VCC = 4.5 V - 1.67 139 ns/V

Product data sheet Rev. 4 — 24 June 2013 9 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

9. Static characteristics

Table 6. Static characteristics type 74HC193

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb = 25 C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V

VCC = 4.5 V 3.15 2.4 - V

VCC = 6.0 V 4.2 3.2 - V

VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V

VCC = 4.5 V - 2.1 1.35 V

VCC = 6.0 V - 2.8 1.8 V

VOH HIGH-level output voltage VI = VIH or VIL ---

IO=20 A; VCC = 2.0 V 1.9 2.0 - V

IO=20 A; VCC = 4.5 V 4.4 4.5 - V

IO=20 A; VCC = 6.0 V 5.9 6.0 - V

IO = 4.0 mA; VCC = 4.5 V 3.984.32- V

IO = 5.2 mA; VCC = 6.0 V 5.485.81- V

VOL LOW-level output voltage VI = VIH or VIL

IO=20A; VCC = 2.0 V - 0 0.1 V

IO=20A; VCC = 4.5 V - 0 0.1 V

IO=20A; VCC = 6.0 V - 0 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0 .26 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V

IIinput leakage current VI=V

CC or GND; VCC =6.0V - - 0.1 A

ICC supply current VI = VCC or GND; IO = 0 A;

VCC =6.0V --8.0A

Ciinput capacitance - 3.5 - pF

Tamb = 40 C to +85 C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V

VCC = 4.5 V 3.15 - - V

VCC = 6.0 V 4.2 - - V

VIL LOW-level input voltage V CC = 2.0 V - - 0.5 V

VCC = 4.5 V - - 1.3 5 V

VCC = 6.0 V - - 1.8 V

VOH HIGH-level output voltage VI = VIH or VIL

IO=20 A; VCC = 2.0 V 1.9 - - V

IO=20 A; VCC = 4.5 V 4.4 - - V

IO=20 A; VCC = 6.0 V 5.9 - - V

IO = 4.0 mA; VCC = 4. 5 V 3.84 - - V

IO = 5.2 mA; VCC = 6. 0 V 5.34 - - V

Product data sheet Rev. 4 — 24 June 2013 10 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

VOL LOW-level output voltage VI = VIH or VIL

IO=20A; VCC = 2.0 V - - 0.1 V

IO=20A; VCC = 4.5 V - - 0.1 V

IO=20A; VCC = 6.0 V - - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - - 0.33 V

IO = 5.2 mA; VCC = 6.0 V - - 0.33 V

IIinput leakage current VI=V

CC or GND; VCC =6.0V - - 1.0 A

ICC supply current VI = VCC or GND; IO = 0 A;

VCC =6.0V --80A

Tamb = 40 C to +125 C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V

VCC = 4.5 V 3.15 - - V

VCC = 6.0 V 4.2 - - V

VIL LOW-level input voltage V CC = 2.0 V - - 0.5 V

VCC = 4.5 V - - 1.3 5 V

VCC = 6.0 V - - 1.8 V

VOH HIGH-level output voltage VI = VIH or VIL

IO=20 A; VCC = 2.0 V 1.9 - - V

IO=20 A; VCC = 4.5 V 4.4 - - V

IO=20 A; VCC = 6.0 V 5.9 - - V

IO = 4.0 mA; VCC = 4. 5 V 3.7 - - V

IO = 5.2 mA; VCC = 6. 0 V 5.2 - - V

VOL LOW-level output voltage VI = VIH or VIL

IO=20A; VCC = 2.0 V - - 0.1 V

IO=20A; VCC = 4.5 V - - 0.1 V

IO=20A; VCC = 6.0 V - - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - - 0.4 V

IIinput leakage current VI=V

CC or GND; VCC =6.0V - - 1.0 A

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC =6.0V - - 160 A

Table 6. Static characteristics type 74HC193 …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Table 7. Static characteristics type 74HCT193

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb = 25 C

VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V

VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V

VOH HIGH-level output voltage VI=V

IH or VIL; VCC =4.5V

IO=20 A4.44.5-V

IO=4.0mA 3.984.32- V

Product data sheet Rev. 4 — 24 June 2013 11 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

VOL LOW-level output voltage VI=V

IH or VIL; VCC =4.5V

IO=20A-00.1V

IO= 4.0 mA - 0.15 0.26 V

IIinput leakage current VI=V

CC or GND; VCC =5.5V - - 0.1 A

ICC supply current VI = VCC or GND; IO = 0 A;

VCC =5.5V --8.0A

ICC additional supply current per input pin; VI=V

CC  2.1 V and

other inputs at VCC or GND;

IO=0A; V

CC = 4.5 V to 5.5 V

pin Dn - 35 126 A

pins CPU, CPD - 140 504 A

pin PL - 65 234 A

pin MR - 105 378 A

Ciinput capacitance - 3.5 - pF

Tamb = 40 C to +85 C

VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V

VIL LOW-level input voltage V CC = 4.5 V to 5.5 V - - 0.8 V

VOH HIGH-level output voltage VI=V

IH or VIL; VCC =4.5V

IO=20 A4.4--V

IO=4.0 mA 3.84 - - V

VOL LOW-level output voltage VI=V

IH or VIL; VCC =4.5V

IO=20A--0.1V

IO= 4.0 mA - - 0.33 V

IIinput leakage current VI=V

CC or GND; VCC =5.5V - - 1.0 A

ICC supply current VI = VCC or GND; IO = 0 A;

VCC =5.5V --80A

ICC additional supply current per input pin; VI=V

CC  2.1 V and

other inputs at VCC or GND;

IO=0A; V

CC = 4.5 V to 5.5 V

pin Dn - - 157.5 A

pins CPU, CPD - - 630 A

pin PL - - 292.5 A

pin MR - - 472.5 A

Tamb = 40 C to +125 C

VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V

VIL LOW-level input voltage V CC = 4.5 V to 5.5 V - - 0.8 V

VOH HIGH-level output voltage VI=V

IH or VIL; VCC =4.5V

IO=20 A4.4--V

IO=4.0 mA 3.7 - - V

VOL LOW-level output voltage VI=V

IH or VIL; VCC =4.5V

IO=20A--0.1V

IO = 4.0 mA - - 0.4 V

Table 7. Static characteristics type 74HCT193 …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 24 June 2013 12 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

IIinput leakage current VI=V

CC or GND; VCC =5.5V - - 1.0 A

ICC supply current VI = VCC or GND; IO = 0 A;

VCC =5.5V - - 160 A

ICC additional supply current per input pin; VI=V

CC  2.1 V and

other inputs at VCC or GND;

IO=0A; V

CC = 4.5 V to 5.5 V

pin Dn - - 171.5 A

pins CPU, CPD - - 686 A

pin PL - - 318.5 A

pin MR - - 514.5 A

Table 7. Static characteristics type 74HCT193 …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 24 June 2013 13 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

10. Dynamic characteristics

Table 8. Dynamic characteristics type 74HC193

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

tpd propagation

delay CPU, CPD to Qn;

see Figure 9 [1] -

VCC = 2.0 V - 63 215 - 270 - 325 ns

VCC = 4.5 V - 23 43 - 54 - 65 ns

VCC = 6.0 V - 18 37 - 46 - 55 ns

CPU to TCU; see

Figure 10

VCC = 2.0 V - 39 125 - 155 - 190 ns

VCC = 4.5 V - 14 25 - 31 - 38 ns

VCC = 6.0 V - 11 21 - 26 - 32 ns

CPD to TCD; see

Figure 10

VCC = 2.0 V - 39 125 - 155 - 190 ns

VCC = 4.5 V - 14 25 - 31 - 38 ns

VCC = 6.0 V - 11 21 - 26 - 32 ns

PL to Qn; see

Figure 11

VCC = 2.0 V - 69 220 - 275 - 330 ns

VCC = 4.5 V - 25 44 - 55 - 66 ns

VCC = 6.0 V - 20 37 - 47 - 56 ns

MR to Qn; see

Figure 12

VCC = 2.0 V - 58 200 - 250 - 300 ns

VCC = 4.5 V - 21 40 - 50 - 60 ns

VCC = 6.0 V - 17 34 43 - 51 ns

Dn to Qn; see

Figure 11

VCC = 2.0 V - 69 210 - 265 - 315 ns

VCC = 4.5 V - 25 42 - 53 - 63 ns

VCC = 6.0 V - 20 36 - 45 - 54 ns

PL to TCU,PLto

TCD; see Figure 14

VCC = 2.0 V - 80 290 - 365 - 435 ns

VCC = 4.5 V - 29 58 - 73 - 87 ns

VCC = 6.0 V - 23 49 - 62 - 74 ns

MR to TCU,MRto

TCD; see Figure 14

VCC = 2.0 V - 74 285 - 355 - 430 ns

VCC = 4.5 V - 27 57 - 71 - 86 ns

VCC = 6.0 V - 22 48 - 60 - 73 ns

Product data sheet Rev. 4 — 24 June 2013 14 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

tpd propagation

delay Dn to TCU,Dnto

TCD; see Figure 14

VCC = 2.0 V - 80 290 - 365 - 435 ns

VCC = 4.5 V - 29 58 - 73 - 87 ns

VCC = 6.0 V - 23 49 - 62 - 74 ns

tTHL HIGH to LOW

output transition

time

see Figure 12

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC =4.5V - 7 15 - 19 - 22 ns

VCC =6.0V - 6 13 - 16 - 19 ns

tTLH LOW to HIGH

output transition

time

see Figure 12

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC =4.5V - 7 15 - 19 - 22 ns

VCC =6.0V - 6 13 - 16 - 19 ns

tWpulse width CPU, CPD (HIGH

or LOW); see

Figure 9

VCC = 2.0 V 100 22 - 125 - 150 - ns

VCC =4.5V 20 8 - 25 - 30 - ns

VCC =6.0V 17 6 - 21 - 26 - ns

MR (HIGH); see

Figure 12

VCC = 2.0 V 100 25 - 125 - 150 - ns

VCC =4.5V 20 9 - 25 - 30 - ns

VCC =6.0V 17 7 - 21 - 26 - ns

PL (LOW); see

Figure 11

VCC = 2.0 V 100 19 - 125 - 150 - ns

VCC =4.5V 20 7 - 25 - 30 - ns

VCC =6.0V 17 6 - 21 - 26 - ns

trec recovery time PL to CPU, CPD;

see Figure 11

VCC =2.0V 50 8 - 65 - 75 - ns

VCC =4.5V 10 3 - 13 - 15 - ns

VCC =6.0V 9 2 - 11 - 13 - ns

MR to CPU, CPD;

see Figure 12

VCC =2.0V 50 0 - 65 - 75 - ns

VCC =4.5V 10 0 - 13 - 15 - ns

VCC =6.0V 9 0 - 11 - 13 - ns

Table 8. Dynamic characteristics type 74HC193 …continued

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 4 — 24 June 2013 15 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

[1] tpd is the same as tPHL and tPLH.

[2] CPD is used to determine the dynamic power dissipation (PD in W):

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

tsu set-up time Dn to PL; see

Figure 13; note:

CPU = CPD =

HIGH

VCC = 2.0 V 80 22 - 100 - 120 - ns

VCC =4.5V 16 8 - 20 - 24 - ns

VCC =6.0V 14 6 - 17 - 20 - ns

thhold time Dn to PL; see

Figure 13

VCC =2.0V 0 14 - 0 - 0 - ns

VCC =4.5V 0 5- 0 - 0 -ns

VCC =6.0V 0 4- 0 0 -ns

CPU to CPD,

CPD to CPU; see

Figure 15

VCC = 2.0 V 80 22 - 100 - 120 - ns

VCC =4.5V 16 8 - 20 - 24 - ns

VCC =6.0V 8 6 - 17 - 20 - ns

fmax maximum

frequency CPU, CPD; see

Figure 9

VCC = 2.0 V 4.0 13.5 - 3.2 - 2.6 - MHz

VCC =4.5V 20 41 - 16 - 13 - MHz

VCC =6.0V 24 49 - 19 - 15 - MHz

CPD power

dissipation

capacitance

VI = GND to VCC;

VCC =5V;

fi=1MHz

[2] -24- - - - -pF

Table 8. Dynamic characteristics type 74HC193 …continued

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 4 — 24 June 2013 16 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Table 9. Dynamic characteristics type 74HCT193

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

tpd propagation

delay CPU, CPD to Qn;

see Figure 9 [1]

VCC = 4.5 V - 23 43 - 54 - 65 ns

CPU to TCU; see

Figure 10

VCC = 4.5 V - 15 27 - 34 - 41 ns

CPD to TCD; see

Figure 10

VCC = 4.5 V - 15 27 - 34 - 41 ns

PL to Qn; see

Figure 11

VCC = 4.5 V - 26 46 - 58 - 69 ns

MR to Qn; see

Figure 12

VCC = 4.5 V - 22 40 - 50 - 60 ns

Dn to Qn; see

Figure 11

VCC = 4.5 V - 27 46 - 58 - 69 ns

PL to TCU,PLto

TCD; see Figure 14

VCC = 4.5 V - 31 55 - 69 - 83 ns

MR to TCU,MRto

TCD; see Figure 14

VCC = 4.5 V - 29 55 - 69 - 83 ns

Dn to TCU,Dnto

TCD; see Figure 14

VCC = 4.5 V - 32 58 - 73 - 87 ns

tTHL HIGH to LOW

output transition

time

see Figure 12

VCC =4.5V - 7 15 - 19 - 22 ns

tTLH LOW to HIGH

output transition

time

see Figure 12

VCC =4.5V - 7 15 - 19 - 22 ns

tWpulse width CPU, CPD (HIGH

or LOW); see

Figure 9

VCC =4.5V 25 11 - 31 - 38 - ns

MR (HIGH); see

Figure 12

VCC =4.5V 20 7 - 25 - 30 - ns

PL (LOW); see

Figure 11

VCC =4.5V 20 8 - 25 - 30 - ns

Product data sheet Rev. 4 — 24 June 2013 17 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

[1] tpd is the same as tPHL and tPLH.

[2] CPD is used to determine the dynamic power dissipation (PD in W):

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

trec recovery time PL to CPU, CPD;

see Figure 11

VCC =4.5V 10 2 - 13 - 15 - ns

MR to CPU, CPD;

see Figure 12

VCC =4.5V 10 0 - 13 - 15 - ns

tsu set-up time Dn to PL; see

Figure 13; note:

CPU = CPD =

HIGH

VCC =4.5V 16 8 - 20 - 24 - ns

thhold time Dn to PL; see

Figure 13

VCC =4.5V 0 6- 0 - 0 -ns

CPU to CPD,

CPD to CPU; see

Figure 15

VCC =4.5V 16 7 - 20 - 24 - ns

fmax maximum

frequency CPU, CPD; see

Figure 9

VCC =4.5V 20 43 - 16 - 13 - MHz

CPD power

dissipation

capacitance

VI = GND to VCC 

1.5 V; VCC =5V;

fi=1MHz

[2] -26- - - - -pF

Table 9. Dynamic characteristics type 74HCT193 …continued

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 4 — 24 June 2013 18 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

11. Waveforms

Measurement points are given in Table 10.

tPLH and tPHL are the same as tpd.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the cl oc k puls e width, and the maximum cl oc k

pulse freque nc y

001aag413

CPU, CPD

input

GND

VOH

VOL

Qn output

tPHL tPLH

1/fmax

Measurement points are given in Table 10.

tPLH and tPHL are the same as tpd.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 10. The clock (CPU, CPD) to terminal count output (TCU,TCD) propagation delays

001aag414

CPU, CPD

input

TCU , TCD

output

tPHL

GND

VOH

VOL

tPLH

Product data sheet Rev. 4 — 24 June 2013 19 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Measurement points are given in Table 10.

tPLH and tPHL are the same as tpd.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 11. The pa rallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock

input (CPU, CPD)

001aag415

Dn input

GND

Qn output

CPU, CPD

input

PL input V

rec

PLH

PHL

Measurement points are given in Table 10.

tPLH and tPHL are the same as tpd.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 12. The master reset input (MR) pulse wid th, MR to Qn pr op agatio n delays, MR to CPU, CPD removal time and

output transition times

001aag416

MR input

Qn output

GND

CPU, CPD

input V

10 %

90 %

rec

PHL

THL

TLH

Product data sheet Rev. 4 — 24 June 2013 20 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 10.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 13. The data inp ut (Dn) to pa rallel load input (PL) set-up and hold times

001aag417

Dn input

Qn output

VOL

VOH

GND

PL input VM

tsu th

Measurement points are given in Table 10.

tPLH and tPHL are the same as tpd.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 14. The data in put (Dn), parallel load input (PL) and the master r eset input (MR) to the termi nal co unt out puts

(TCU,TCD) propagation delays

001aag418

PL, MR, Dn

input

TCU , TCD

output

tPLH tPHL

VOL

VOH

GND

Measurement points are given in Table 10.

Fig 15. The CPU to CPD or CPD to CPU hold times

001aag419

CPD or CPU

input

CPU or CPD

input

GND

Product data sheet Rev. 4 — 24 June 2013 21 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Table 10. Measurement points

Type Input Output

VMVIVM

74HC193 0.5 VCC GND to VCC 0.5 VCC

74HCT193 1.3 V GND to 3 V 1.3 V

Test data is given in Table 11.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator

CL = Load capacitance including jig and probe capacitance

RL = Load resistor

S1 = Test selection switch

Fig 16. Load circuitry for measuring switching time s

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

VIVO

RLS1

open

Table 11. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH

74HC193 VCC 6ns 15pF, 50 pF 1kopen

74HCT193 3 V 6 ns 15 pF, 50 pF 1 kopen

Product data sheet Rev. 4 — 24 June 2013 22 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

12. Application information

Fig 17. Application for cascaded up/down counter with parallel load

001aag420

data input

IC1 IC2

data output

up clock

down clock

carry

borrow

asynchronous

parallel load

reset

D0 D1 D2 D3

Q0 Q1 Q2 Q3

TCU

TCD

CPU

CPD

D0 D1 D2 D3

Q0 Q1 Q2 Q3

TCU

TCD

CPU

CPD

Product data sheet Rev. 4 — 24 June 2013 23 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

13. Package outline

Fig 18. Package outline SOT 109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 4 — 24 June 2013 24 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Fig 19. Package outline SOT 338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Product data sheet Rev. 4 — 24 June 2013 25 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Fig 20. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 4 — 24 June 2013 26 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Fig 21. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 4 — 24 June 2013 27 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

14. Abbreviations

15. Revision history

Table 12. Abbr eviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

LSTTL Low-power Schottky Transistor-Transistor Logic

MM Machine Model

TTL Tr ansistor-Transistor Logic

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT193 v.4 20130624 Product data sheet - 74HC_HCT193 v.3

Modifications: •General description updated.

74HC_HCT193 v.3 20070523 Product data sheet - 74HC_HCT193_CNV v.2

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Family specification included

74HC_HCT193_CNV v.2 19970828 Produ ct specification - -

Product data sheet Rev. 4 — 24 June 2013 28 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond tho se described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the prod uct specification.

Product data sheet Rev. 4 — 24 June 2013 29 of 30

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 June 2013

Document identifier: 74HC_HCT193

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 6

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Recommended operating conditions. . . . . . . . 8

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 13

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12 Application information. . . . . . . . . . . . . . . . . . 22

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

17 Contact information. . . . . . . . . . . . . . . . . . . . . 29

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30