Am9517A/8237A Multimode DMA Controller FINAL DISTINCTIVE CHARACTERISTICS @ Four independent DMA channels, each with separate registers for Mode Control, Current Address, Base Address, Current Word Count and Base Word Count Transfer modes: Block, Demand, Single Word, Cascade Independent Autoinitialization of all channels Memory-to-memory transfers Memory block initialization Address increment or decrement Master system disable Enable/disable control of individual DMA requests Directly expandable to any number of channels @ End of Process input for terminating transfers @ Software DMA requests @ Independent poiarity control for DREQ and DACK signals @ Compressed timing option speeds transfers up to 2.5M bytes/second @ +5 volt power supply @ N-channel silicon gate MOS technology @ 40-pin Hermetic DIP package, 44-pin PLCC package @ 9517A-5 5 MHz version for higher speed CPU compati- bility GENERAL DESCRIPTION The Am9517A/8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for micro- processor systems. It is designed to improve system performance by allowing external devices to directly trans- fer information to or from the system memory. Memory-to- memory transfer capability is also provided. The Am9517A/ 8237A offers a wide variety of programmable contro! features to enhance data throughput and system optimiza- tion and to allow dynamic reconfiguration under program control. The Am9517A/8237A is designed to be used in conjunc- tion with an external 8-bit address register such as the Am74LS373. It contains four independent channels and may be expanded to any number of channels by cascading additional controller chips. The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be individually programmed to Autoinitialize to its original condition following an End of Process (EOP). Each channel has a full 64K address and word count capability. An external EOP signal can terminate a DMA or memory-to-memory transfer. This is useful for block search orf compare operations using external comparators or for intelligent peripherals to abort erroneous services. BLOCK DIAGRAM DECREMENTOR INC/DECREMENTOR TEMP WORD COUNT REG (16) 0F ~-q TEMP ADDRESS REG (16) [oes K**> RESET eT 16 BIT BUS cs -q 16 BIT BUS READY +J CLOCK e TIMING READ BUFFER AND READ/WRITE BUFFER ovTPUT BUFFER AEN J BASE @ASE f WORD aponess | WENA d 6) I 16) CONTROL ADSTBS ~_} CURRENT CURRENT I WORD ADDRESS COUNT 16) COUNT ne MEMW cd Oh q Ow =d WRITE BUFFER COMMAND CONTROL AS-AIS READ BUFFER COMMAND (8: 4 OREQO.OREQ3 j4 | HACK o-f PRIORITY ENCODER ROTATING PRIORITY HREQ ~J INTERNAL OATA @US 080 087 VO BUFFER K MASK (4) 4 DACKO-DACKI => 44 LOGIC READ/WRITE MODE ax) STATUS (8 TEMPORARY (8) REQUEST (4) BD003250 *The 8237A is an AMD-invented device more commonly referred to as the Am9517A. - Publication # Rev. Amendment 03040 o 40 Issue Date: August 1989 Am9517A/8237A 1-227CONNECTION DIAGRAMS Top View DIPs PLCC TOR 1 @ YS 40 [}= a7 zc iow ~=(_]2 39 [7 }} as gEEBBoseezh MENA ~{_] 3 38 [T}> as gBR6bereee8 MEMW ~_{_] 4 37 [=}+> a4 * (NOTE 11) e#{_] 36 [T}e OR . Reavy #{_] 6 35 [7}= 43 (NOTE 11) HNC HACK ~e{_] 7 34 [Fj a2 READY L] A3 ADSTB 8 33 (ee at HACK D a2 aen ~1_] 9 32 [-}e= ao ADSTB T] At HREQ ~-{_] 10 31 [+ vec (+5) AEN 1] Ao cs 30 T}-= peo HREQ Voc ctk e{_] 12 29 }-= pei cs 1) DBO RESET {_]} 13 28 Lo }= pe2 CLK M081 pack2 ~1__] 14 27 *~ 3 RESET r oB2 pack3 -{_} 15 26 T}-~ ea DACK2 D pas prea --=L_] 16 25 [~>}} pacxo NC 9 084 prREQ2 ={_] 17 24 [}- ack 21 prea: =1_] 18 23 (}#> 2s DOWE Do bLlo oreo e{] 19 22 = 026 SESSssRRRS (GND) vss {_] 20 2 DB? SESA5 as cp00s072 cb009911 Note: Pin 1 is marked for orientation. *See Note 11 under DC Characteristics table. 1-228 Am9517A/8237AORDERING INFORMATION Am9517A AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Package Type d. Temperature Range e. Optional Processing AM9517A 4 D G Li . OPTIONAL PROCESSING Blank = Standard processing B = Burn-in a . TEMPERATURE RANGE* C= Commercial (0 to + 70C) t= Industrial (-40 to + 85C) c. PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) D = 40-Pin Ceramic DIP (CD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) Co . SPEED OPTION ~4=4 MHz ~5=5 MHz a. DEVICE NUMBER/DESCRIPTION Am9517A Multimode DMA Controller Valid Combinations ji Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD AM9517A-4 DC, DCB, DIB, PC sales office to confirm availability of specific valid AM9517A-5 DC, DCB, PC, JC combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade Products. Am9517A/8237A 1-229- jo ORDERING INFORMATION (continued) b. Package Type c. Device Number d. Speed Option e. Optional Processing 8237, =8 B | 8237A AMD commodity products are available in severai packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in 2 SPEED OPTION -4=4 MHz -5=5 MHz a . DEVICE NUMBER/DESCRIPTION 8237A Multimode OMA Controller b. PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) D = 40-Pin Ceramic DIP (CD 040) Valid Combinations 8237A-4 8237A-5 P, D 8237A-4B 8237A-5B D . TEMPERATURE RANGE Blank = Commercial (0 to + 70C) Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products. 1-230 Am9517A/8237AORDERING INFORMATION (continued) Standard Military Drawing (SMD)/DESC Products AMD standard products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Military Drawing (SMD)/DESC products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for SMD/DESC products is formed by a combination of: a. Mititary Drawing Part Number b. Device Type . c. Case Outline d. Lead Finish 5962-87575, OL x Lg LEAD FINISH X = Any Lead Finish Acceptable c. CASE OUTLINE Q= 40 pin Ceramic DIP (CD 040) b. MILITARY DEVICE TYPE 01 =3 MHz (9517A) 02 = 4 MHz (9517A-4) & a. MILITARY DRAWING NO./DESCRIPTION 5962-87575 Muitimode DMA Controller Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD ax sales office to confirm availability of specific valid combinations, to check on newly released combinations. 962-8757501 5962-875702 Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am9517A/8237A 1-231ORDERING INFORMATION (continued) APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Device Class d. Package Type e. Lead Finish AM9517A =4 AB Q A |, LEAD FINISH A= Hot Solder Dip d. PACKAGE TYPE Q = 40-Pin Ceramic DIP (CD 040) c. DEVICE CLASS /B = Class B b. SPEED OPTION Blank = 3 MHz -4=4 MHz a. DEVICE NUMBER/DESCRIPTION Am9517A Multimode DMA Controller Valid Combinations Vatid Combinations Valid Combinations list configurations planned to be "AM9517A supported in volume for this device. Consult the local AMD /BQA sales office to confirm availability of specific valid AM9517A-4 . . combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. 1-232 Am9517A/8237APIN DESCRIPTION Pin No.* VO Description 31 Vec Power: +5 volt supply. 20 Vss Ground. 12 CLK Clock Input: Clock Input controls the internal operations of the Am9517A/8237A and its rate of data transfers. The input may be driven at up to 3MHz for the standard Am9517A/8237A and up to 5 MHz for the Am95t7A-5/8237A-5. Chip Select: Chip Select is an active low input used to select the Am9517A/8237A as an |/O device during the idle cycle.This allows CPU communication on the data bus. RESET Reset: Reset is an active high input which clears the Command, Status, Request and Temporary registers. It also clears the First/Last Flip/Flop and sets the Mask register. Following a Reset the device is in the Idle cycle. READY Ready: Ready is an input used to extend the memory read and write pulses from the Am9517A/ 8237A to accommodate slow memories or I/O peripheral devices. Ready must not make transitions during its specified setup/hold time. HACK Hold Acknowledge: The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the system buses. 19-16 DREQ0-DREQ3 DMA Request: The DMA Request lines are individual asynchronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQO has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of DREQ signal. Polarity of DREQ is programmable. Reset initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. 30-26, 23-21 DB0-DB7 vo DATA Bus: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of an Address register, a Status register, the Temporary register or a Word Count register to the CPU. The outputs are disabled and the inputs are read during an i/O Write cycle when the CPU is programming the Am9517A/8237A contro! registers. During DMA cycles the most significant 8 bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory comes into the Am9517A/8237A on the data bus during the read-from-memory transfer. In the write-to-memory transfer, the data bus outputs place the data into the new memory location. VO 1/O Read: 1/0 Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the Am9517A/8237A to access data from a peripheral during a DMA Write transfer. vo VO Write: [/O Write is a bidirectional active low three-state line. In the Idte cycle, it is an input control signal used by the CPU to load information into the Am9517A/8237A. In the Active cycle, it is an output control signat used by the Am9517A/8237A to load data to the peripheral during a DMA Read transfer. 36 0 End of Process: End of Process is an active low bidirectional open-drain signal. Information concerning the completion of DMA service is available at the bidirectional EGP pin. The Am9517A/ 82374 atlows an external signal to terminate an active DMA service. This is accomplished by pulling the EOP input low with an external EOP signal. The Am9517A/8237A also generates a pulse when the terminal count (TC) for any channel is reached. This generates an EOP signal which is output through the EOP Line. The reception of EOP, either internal or external, will cause the Am9517A/ 82374 to terminate the service, reset the request, and, if Autoinitialize is enabled, to write the base registers to the current registers of that channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP unless the channel is programmed for Autoinitialize. tn that case, the mask bit remains unchanged. During memory-to-memory transfers, EOP will be output when the TC for channel 1 occurs. EOP shouid be tied high with a pull-up resistor if it is not used to prvent erroneous end of process inputs. 32-35 AQ-A3 VO Address: The four least significant address lines are bidirectional three-state signals. In the Idle cycle, they are inputs and are used by the CPU to address the registers to be load or read. In the Active cycle, they are outputs and provide the lower 4 bits of the output address. 37-40 A4-A7 Address: The four most significant address lines are three-state outputs and provide 4 bits of address. These lines are enabled only during DMA service. 10 HREQ Hold Request: This is the Hold Request to the CPU and is used to request control of the system bus. If the corresponding mask bit is clear, the presence of any valid DREQ causes the Am9517A/ 82374 to issue the HRQ. After HRQ goes active, at least one clock cycie (TCY) must occur before HLDA goes active. 25, 24 14, 16 DACKO-DACK3 DMA Acknowledge: DMA Acknowledge is used to notify the individual peripherals when one has been granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low. AEN Address Enable. Address Enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. AEN can also be used to disable in other system bus drivers during DMA transfers. AEN is active-high. Address Strobe. The active-hign Address Strobe is used to strobe the upper address byte into an external latch. Memory Read: The Memory Read signal is an active iow three-state output used to access data from the selected memory location during a DMA Read or a memory-to-memory transfer. Memory Write: The Memory Write signal is an active low three-state output used to write data to the selected memory location during a DMA Write or a a memory-to-memory transfer. *Applies to. DIPs only. Am9517A/8237A 1-233Name Size Number Base Address Registers 16 bits 4 Base Word Count Registers 16 bits 4 Current Address Registers 16 bits 4 Current Word Count Registers 16 bits 4 Temporary Address Register 16 bits 1 Temporary Word Count Register 16 bits 1 Status Register 8 bits 1 Command Register 8 bits 1 Temporary Register 8 bits 1 Mode Registers 6 bits 4 Mask Register 4 bits 1 Request Register 4 bits 1 Am9517/8237A Internal Registers. DETAILED DESCRIPTION The Am9517A/8237A block diagram includes the major fogic blocks and ali of the internai registers. The data interconnec- tion paths are also shown. Not shown are the various control signals between the blocks. The Am9517A/8237A contains 344 bits of internal memory in the form of registers. The table shown above lists these registers by name and shows the size of each. A detailed description of the registers and their functions can be found under Register Description. The Am9517A/8237A contains three basic blocks of control logic. The Timing Control block generates internal timing and external control signals for the Am9517A/8237A. The Pro- gram Command Control block decodes the various commands given to the Am9517A/8237A by the microprocessor prior to servicing a DMA Request. it also decodes each channel's Mode Control word. The Priority Encoder block resolves priority contention among DMA channels requesting service simultaneously. The Timing Control block derives internal timing from the clock input. In Am9080A systems this input will usually be the 2 TTL clock from an Am8224. However, any appropriate system clock will suffice. DMA Operation The Am9517A/8237A is designed to operate in two major cycles. These are called Idle and Active cycles. Each device cycle is made up of a number of states. The Am9517A/8237A can assume seven separate states, each composed of one full clock period. State | (Si) is the inactive state. It is entered when the Am9517A/8237A has no valid DMA requests pending. While in SI, the DMA controller is inactive but may be in the Program Condition, being programmed by the proces- sor. State 0 (SO) is the first state of a DMA service. The Am9517A/8237A has requested a hold but the processor has not yet returned an acknowledge. An acknowledge from the CPU will signal that transfers may begin. $1, $2, $3, and $4 are the working states of the DMA service. If more time is needed to complete a transfer than is available with normal timing, wait states (SW) can be inserted before S4 by the use of the Ready fine on the Am9517A/8237A. Memory-to-memory transfers require a read-from and a write- to-memory to compiete each transfer. The states, which resemble the normal working states, use two digit numbers for identification. Eight states are required for each complete transfer. The first four states (S11, S12, S13, S14) are used for the read-from-memory half and the last four states (S21, $22, $23 and S24) for the write-to-memory half of the transfer. The Temporary Data register is used for intermediate storage of the memory byte. Idle Cycle When no channel is requesting service, the Am9517A/8237A will enter the Idle cycle and perform ''SI'' states. In this cycle the Am9517A/8237A will sample the DREQ lines every clock cycle to determine if any channel is requesting a DMA service. The device will aiso sample CS, looking for an attempt by the microprocessor to write or read the internal registers of the Am9517A/8237A. When CS is LOW and HACK is LOW, the Am9517A/8237A enters the Program Condition. The CPU can now establish, change or inspect the internal definition of the part by reading from or writing to the internal registers. Address fines AO-A3 are inputs to the device and select which registers will be read or written. The IOR and IOW lines are used to select and time reads or writes. Due to the number and size of the internal registers, an internal flip/flop is used to generate an additional bit of address. This bit is used to determine the upper or lower byte of the 16-bit Address and Word Count registers. The flip/flop is reset by Master Clear or Reset. A separate software command can also reset this flip/ flop. Special software commands can be executed by the Am9517A/8237A in the Program Condition. These commands are decoded as sets of addresses when both CS and IOW are active and do not make use of the data bus. Functions include Clear First/Last Flip/Flop and Master Clear. Active Cycle When the Am9517A/8237A is in the idle cycle and a channet requests a DMA service, the device will output a HREQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA service will take place in one of four modes: Single Transfer Mode: In Single Transfer mode, the Am9517A/8237A will make a one-byte transfer during each HREQ/HACK handshake. When DREQ goes active, HREQ will go active. After the CPU responds by driving HACK active, a one-byte transfer witl take place. Following the transfer, HREQ will go inactive, the word count will be decremented and the address will be either incremented or decremented. When the word count goes to zero, a Terminal Count (TC) will cause an Autoinitialize if the channel has been programmed to do so. To perform a single transfer, DREQ must be held active only until the corresponding DACK goes active. If DREQ is held continuously active, HREQ will go inactive following each transfer and then will go active again and a new one-byte transfer will be made following each rising edge of HACK. In 8080A/Am9080A systems, this will ensure one full machine cycle of execution between DMA transfers. Details of timing between the Am9517A/8237A and other bus control proto- cols will depend upon the characteristics of the microproces- sor involved. Block Transfer Mode: In Block Transfer mode, the Am9517A/8237A will continue making transfers until a TC (caused by the word count going to zero) or an external End of Process (EOP) is encountered. DREQ need be held active only until DACK becomes active. An Autoinitialize will occur at the end of the service if the channel has been programmed for it. Demand Transfer Mode: In Demand Transfer mode the device will continue making transfers until a TC or external EOP is encountered or until DREQ goes inactive. Thus, the device requesting service may discontinue transfers by bring- ing DREQ inactive. Service may be resumed by asserting an active DREQ once again. During the time between services when the microprocessor is allowed to operate, the intermedi- ate values of address and word count may be read from the Am9517A/8237A Current Address and Current Word Count 1-234 Am9517A/8237Aregisters. Autoinitialization will only occur following a TC or EOP at the end of service. Following Autoinitialization, an active-going DREQ edge is required to initiate a new DMA service. Cascade Mode: This mode is used to cascade more than one Am9517A/8237A together for simple system expansion. The HREQ and HACK signals from the additional Am9517A/ 8237A are connected to the DREQ and DACK signals of a channel of the initia! Am9517A/8237A. This allows the DMA requests of the additional device to propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device must wait for its turn to acknowledge requests. Since the cascade channel in the initial device is used only for prioritizing the additional device, it does not output any address or control signals of its own. These would conflict with the outputs of the active channel in the added device. The Am9517A/8237A will respond to DREQ with DACK but all other outputs except HREQ will be disabled. Figure 1 shows two additional devices cascaded into an initial device using two of the previous channels. This forms a two level DMA system. More Am9517A/8237As could be added at the second level by using the remaining channels of the first level. Additional devices can also be added by cascading into the channels of the second level devices forming a third level. 2ND LEVEL 1ST LEVEL, AmO517A/B2I7A, BOLOREO | treo OREG MREQ HOLD ACK HACK DACK HACK AmO517A/82370 oREG MREQ pack Hack INITIAL DEVICE Am@SI7A/B297A ADOITIONAL DEVICES AFO002171 Figure 1. Cascaded Am9517A/8237As Transfer Types Each of the three active transfer modes can perform three different types of transfers. These are Read, Write and Verify. Write transfers move data from an !/O device to the memory by activating IOR and MEMW. Read transfers move data from memory to an I/O device by activating MEMR and IOW. Verify transfers are pseudo transfers; the Am9517A/8237A operates as in Read or Write transfers generating addresses, respond- ing to EOP, etc. However, the memory and |/O control lines remain inactive. Memory-to-Memory: The Am9517A/8237A includes a block move capability that allows blocks of data to be moved from one memory address space to another. When Bit CO in the Command register is set to a logical 1, channels 0 and 1 will operate as memory-to-memory transfer channels. Channel 0 forms the source address and channel 1 forms the destination address. The channe! 1 word count is used. A memory-to- memory transfer is initiated by setting a software DMA request for channel 0. Block Transfer Mode should be used for memory-to-memory. When channel 0 is programmed for a fixed source address, a single source word may be written into a block of memory. When setting up the Am9517A/8237A for memory-to-memory operation, it is suggested that both channels 0 and 1 be masked out. Further, the channel 0 word count should be initialized to the same value used in channel 1. No DACK outputs will be active during memory-to-memory transfers. The Am9517A/8237A will respond to external EOP signals during memory-to-memory transfers. Data comparators in block search schemes may use this input to terminate the service when a match is found. The timing of memory-to- memory transfers may be found in Timing Diagram 2. Autoinitialize: By programming a bit in the Mode register, a channel may be set up for an Autoinitialize operation. During Autoinitialization, the original values of the Current Address and Current Word Count registers are automatically restored from the Base Address and Base Word Count registers of that channel following EOP. The base registers are loaded simulta- neously with the current registers by the microprocessor and remain unchanged throughout the DMA service. The mask bit is not set by EOP when the channel is in Autoinitialize. Following Autoinitialize the channel is ready to repeat its service without CPU intervention. Priority: The Am9517A/8237A has two types of priority encoding available as software selectable options. The first is Fixed Priority which fixes the channels in priority order based upon the descending value of their number. The channel with the lowest priority is 3 followed by 2, 1 and the highest priority channel, 0. The second scheme is Rotating Priority. The last channel to get service becomes the lowest priority channel with the others rotating accordingly. With Rotating Priority in a single chip DMA system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have occurred. This prevents any one channel from monopolizing the system. Ist Service 2nd Service 3rd Service highest Q 2 ~e service 3 ~ service 1 = service 3 ~ request oO 2 ~ 0 1 lowest 3 1 2 TBOOCCOs The priority encoder selects the highest priority channel requesting service on each active-going HACK edge. Once a channel is started, its operation will not be suspended if a request is received by a higher priority channel. The high priority channet will only gain control after the lower priority channel releases HREQ. When control is passed from one channel to another, the CPU will always gain bus control. This ensures generation of rising HACK edge to be used to initiate selection of the new highest-priority requesting channel. Compressed Timing: To achieve even greater throughput where system characteristics permit, the Am9517A/8237A can compress the transfer time to two clock cycles. From Timing Diagram 3 it can be seen that state S3 is used to extend the access time of the read pulse. By removing state S3 the read pulse width is made equal to the write pulse width, and a transfer consists only of state S2 to change the address and state S4 to perform the read/write. S1 states will still occur when A8-A15 need updating (see Address Genera- tion). Timing for compressed transfers is found in Timing Diagram 4. Extended Write: For Flyby Transactions late write is normally used, as this allows sufficient time for the TOR signal to get data from the peripheral onto the bus before MEMW is activated. In some systems, performance can be improved by starting the write cycle earlier. This is especially true for memory-to-memory transactions. Am9517A/8237A 1-235Address Generation: To reduce pin count, the Am9517A/ 8237A multiplexes the eight higher order address bits on the data lines. State S1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. The falling edge of Address Strobe (ADSTB) is used to joad these bits from the data fines to the latch. Address Enable (AEN) is used to enable the bits onto the address bus through a three-state enable. The lower order address bits are output by the Am9517A/8237A directly. Lines AO-A7 should be connected to the address bus. Timing Diagram 1 shows the time relationships between CLK, AEN, ADSTB, DBO -0DB7 and AO -A7. During Block and Demand Transfer mode services which include muitiple transfers, the addresses generated will be sequential. For many transfers the data held in the external address latch will remain the same. This data need only change when a carry or borrow from A7 to A8 takes place in the normal sequence of addresses. To save time and speed transfers, the Am9517A/8237A executes St states only when updating of A8 - A15 in the latch is necessary. This means for long services that S1 states may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers. Register Description Current Address Register: Each channel has a 16-bit Current Address register. This register holds the value of the address used during DMA transfers. The address is automati- cally incremented or decremented after each transfer and the intermediate values of the address are stored in the Current Address register during the transfer. This register is written or read by the microprocessor in successive 8-bit bytes. it may also be reinitialized by an Autoinitialize back to its original value. Autoinitialization takes place only after an EOP. Current Word Count Register: Each channel has a 16-bit Current Word Count register. This register should be pro- grammed with, and will return on a CPU read, a value one less than the number of words to be transferred. The word count is decremented after each transfer. The intermediate value of the word count is stored in the register during the transfer. When the value in the register goes to zero, a TC will be generated. This register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. Follow- ing the end of a DMA service, it may also be reinitialized by an Autoinitialize back to its original value. Autoinitialize can occur only when an EOP occurs. Note that the contents of the Word Count register will be FFFF (hex) following on internally generated EOP. Base Address and Base Word Count Registers: Each channel has a pair of Base Address and Base Word Count registers. These 16-bit registers store the original values of their associated current registers. During Autoinitialize these values are used to restore the current registers to their original values. The base registers are written simultaneously with their corresponding current register in 8-bit bytes during DMA, programming by the microprocessor. Accordingly, writing to these registers when intermediate values are in the Current registers will overwrite the intermediate values. The Base registers cannot be read by the microprocessor. Command Register: This 8-bit register controls the operation of the Am9517A/8237A. It is programmed by the microproces- sor in the Program Condition and is cleared by Reset. The following table lists the function of the command bits. See Figure 2 for address coding. 0 ~* Bit Number 0 Memory-to-memary disable 1 Memory-to-memory enable o Channel 0 address hoid disable Channel 0 address hold enable {f bit O=0 x o Controller enable Controller disable Q Norma! timing Compressed timing if bit O= 1 x Fixed Priority Rotating Priority O Late write selection 1 Extended write selection X Ifbit3=1 O DREQ sense active high 1 DREQ sense active tow 0 DACK sense active tow 1 DACK sense active high DF000970 | re Mode Register: Each channel has a 6-bit Mode register associated with it. When the register is being written to by the microprocessor in the Program Condition, bits 0 and 1 determine which channel Mode register is to be written to. 7 6 6 4 3 2 #1 0 -Bit Number ~ Channel 0 select 01 Channel 1 select Channel 2 select 11 Channel 3 select f \ i 00 Verify transfer 01 Write transfer 10 Read transfer 11 Wtegal XX If bits 6 and 7 = 11 Autoinitiatize disable Autoinitialize enable QO Address increment select 1 Address decrement select 00 Demand mode select 01 Single mode select 10 Block mode select 11 Cascade mode select DFoo0980 Request Register: The Am9517A/8237A can respond to requests for DMA service which are initiated by software as weil as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are nonmaskable and subject to prioritization by the Priority Encoder network. fir 1-236 Am9517A/8237AEach register bit is set or reset separately under software contro! or is cleared upon generation of a TC or external EOP. The entire register is cleared by a Reset. To set or reset a bit, the software loads the proper form of the data word. See Figure 2 for address coding. 7 6 4 3 2 1 =O - Bit Number LITT Tt Dont Care 00 Select channel 0 04 Select channel 1 10 Select channel 2 11 Select channel 3 O Reset request bit 1 Set request bit DFOO093s0 Software requests will be serviced only if the channel is in Block mode. When initiating a memory-to-memory transfer, the software request for channel 0 should be set. Mask Register: Each channel has associated with it a mask bit which can be set to disable the incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed for Autoinitialize. Each bit of the 4-bit Mask register may aiso be set or cleared separately under software control. The entire register is also set by a Reset. This disables all DMA requests until a clear Mask register instruction allows them to occur. The instruction to separately set or clear the mask bits is similar in form to that used with the Request register. See Figure 2 for instruction addressing. 7 6 5 4 3 2 = 1 =O Bit Number [LT TEtT TT) 00 ; Select channel 0 mask bit Don't Care Ot Select channel 1 mask bit 10 Select channel 2 mask bit 11. Select channel 3 mask bit 0 Ctear mask bit 4 Set mask bit All four bits of the Mask Register may also be written with a single command. DF001000 OQ ~* Bit Number OQ Clear Channel 0 mask bit 1 Don't Care Set Channel 0 mask bit O Clear Channel 1 mask bit 1 Set Channel t mask bit O Clear Channel 2 mask bit 1 Set Channel 2 mask bit 0 Clear Channel 3 mask bit 1 Set Channel 3 mask bit OF001010 Status Register: The Status registers may be read out of the Am9517A/8237A by the microprocessor. It indicates which channeis have reached a terminal count and which channels have pending DMA requests. Bits 0 - 3 are set each time a TC is reached by that channel, including after each Autoinitializa- tion. These bits are cleared by Reset and each Status Read. Bits 4-7 are set whenever their corresponding channei is requesting service. 7 6 5 4 3 2 #1 O ~Bit Number 1. Channel 0 has reached TC 1. Channel 1 has reached TC 1 Channel 2 has reached TC 1 Channel 3 has reached TC Channel 0 request Channel 2 request Channel 3 request 1 1 Channel 1 request 1 1 DF001020 Temporary Register: The Temporary register is used to hold data during memory-to-memory transfers. Following the com- pletion of the transfers, the last word moved can be read by the microprocessor in the Program Condition. The Temporary register always contains the last byte transferred in the previous memory-to-memory operation, unless cleared by a Reset. Software Commands: There are three special software commands which can be executed in the Program Condition. They do not depend on any specific bit pattern on the data bus. The three software commands are: Clear First/Last Flip/Flop: This command may be issued prior to writing or reading Am9517A/8237A address or word count information. This initializes the Flip/Flop to a known state so that subsequent accesses to register contents by the microprocessor will address lower and upper bytes in the correct sequence. When the Flip/Flop is cleared it addresses the lower byte and when set it addresses the upper byte. Master Clear: This software instruction has the same effect as the hardware Reset. The Command, Status, Request, Temporary and Internal First/Last Flip/Flop registers are cleared and the Mask register is set. The Am9517A/8237A will enter the idle cycle. Clear Mask Register: This command clears the mask bits of all four channels, enabling them to accept DMA requests. Am9517A/8237A 1-237Interface Signals A3 A2 Al AO OR lOW | Operation 1 0 0 0 0 1 Read Status Register 1 0 0 0 1 0 Write Command Register 1 oO 0 1 0 1 iltegal 1 0 0 1 1 0 Write Request Register 1 0 1 0 0 1 INegal 1 0 1 0 1 0 Write Single Mask Register Bit 1 Q 1 1 0 1 {Negal 1 0 1 1 1 0 Write Mode Register 1 1 0 9 0 1 \iegal 1 1 0 0 1 0 Clear Byte Pointer Flip/Flop 1 1 o 1 0 1 Read Temporary Register 1 1 0 1 1 0 Master Clear 1 1 1 0 0 1 lllegat 1 1 1 9 1 0 Clear Mask Register 1 1 1 1 0 1 Itlegat 1 1 1 1 1 0 Write All Mask Register Bits Figure 2. Register and Function Addressing . Signals Internal Data Bus Channel Register Operation _ Flip/Fl DBO - DB7 cs OR iOW a3 A2 Al AO Ip/TIop 0 Base & Current Write 0 1 0 0 0 0 0 0 AQ-A7 Address Q t 0 9 0 0 0 1 AB-A15 Current Read 0 0 1 Qo 0 oO Q 0 AQ-A7 Address QO 0 1 Oo Q oO 0 1 A8-A15 Base & Current Write 0 1 0 0 0 0 1 0 WO -W7 Word Count 0 1 0 0 0 0 1 1 W8-W15 Current Read 0 0 1 0 0 Q 1 0 WO -W7 Word Count 0 0 1 0 0 O 1 1 W8-W15 1 Base & Current Write 0 1 0 oO 0 1 0 0 AQ- A? Address 0 1 0 Qo 0 1 0 1 AB- A15 Current Read 6 0 1 0 0 | 0 0 AQ-A7 Address 0 0 1 0 0 1 0 1 A8- A15 Base & Current Write 0 1 0 0 0 1 1 0 WO -W7 Word Count 0 1 0 Qo Qo 1 1 1 W8-W15 Current Read 0 0 1 0 0 1 1 0 WO - W7 Word Count 0 0 1 0 0 1 1 1 Ws - W15 Base & Current : 0 1 0 0 1 0 0 0 AQ -A?7 2 Address Write 0 1 0 0 1 0 0 1 AB - A15 Current Read 0 0 1 0 1 0 0 0 AOQ-A7 Address 0 0 1 0 1 0 9 1 AB~A15 Base & Current Write 0 1 0 0 1 0 1 0 WO - W7 Word Count 0 1 0 0 4 oO 1 1 ws -W15 Current Read 0 0 1 0 1 0 1 9 WO -W7 Word Count 0 Q 1 0 1 0 1 1 W8-W15 Base & Current : 0 1 0 0 1 1 0 0 AO - A7 3 Address Write 0 1 0 0 1 1 0 1 AB - A15 Current 0 oO 1 0 1 1 QO 0 AQ-A7 Address Read 0 0 1 0 1 1 0 1 AB A15 Base & Current Write 0 1 0 0 1 1 1 0 WoO - W7 Word Count 0 1 0 0 1 1 1 1 W8 -W15 Current Read 0 0 1 0 1 1 1 0 WO - W7 Word Count 0 0 1 0 1 1 1 1 W8 - W15 Figure 3. Word Count and Address Register Command Codes 1-238 Am9517A/8237AAPPLICATIONS INFORMATION Figure 4 shows a convenient method for configuring a DMA system with the Am9517A/8237A Controller and a micropro- cessor system. The Multimode DMA Controller issues a Hoid Request to the processor whenever there is at least one valid DMA Request from a peripheral device. When the processor replies with a Hold Acknowledge signal, the Am9517A/8237A takes control of the Address Bus, the Data Bus and the Control Bus. The address for the first transfer operation comes out in two bytes the feast significant eight bits on the eight Address outputs and the most significant eight bits on the Data Bus. The contents of the Data Bus are then latched into the Am74LS373 register to complete the full 16 bits of the Address Bus. The Am74LS373 is a high-speed, low power, 8- bit, three-state register in a 20-pin package. After the initial transfer takes place, the register is updated only after a carry or borrow is generated in the teast significant address byte. Four DMA channels are provided when one Am9517A/8237A is used. ADDRESS BUS AOA1S K AB-AIS fo Of OE Am74LS373 cep 8-BIT LATCH 2 A0-A15 J4LS74 AEN AO-A3 0 A4~A7 cS = ADSTB Zs HLDA db oa HACK Am9517A/8237A 7 9 dB0- 4 cP - 3 087 bie 8 & ~ @ JE 2 oe w 9 HLDRO nrea g # |e i [6 8 a 8 cpu | 65 ? CLOCK 4 4 RESET MEM fO MEMW (O- CONTROL TOR fo- BUS TOW jo DB0-DB7 [ SYSTEM DATA BUS > AF002182 Figure 4. Basic OMA Configuration Am9517A/8237A 1-239ABSOLUTE MAXIMUM RATINGS Storage temperature .....................cee -65 to +150C Voc with Respect to Vgg ......... ee -0.5 to +7.0 V All Signal Voltages with Respect tO VSG oeecccecececeeceeeeeeeeeettttteeeeetees -0.5 V to +7.0 V Power Dissipation (Package Limitation) .................. 1.5 W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device OPERATING RANGES Commercial (C) Devices Temperature (Ta) Supply Voltage (Vcc) Industrial (I) Devices Temperature (Ta) Supply Voltage (Vcc) Operating ranges define those limits between which the functionality of the device is guaranteed. reliability. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified. (Note 1) Parameters Description Test Conditions Min Typ Max Units IOH = -200 pA 2.4 VOH Output HIGH Voltage Volts IOH =-100 vA, (HREQ Only) 3.3 VOL Output LOW Voltage OL =3.2 mA 0.40 V Volts VIH Input HIGH Voltage 2.0 VCC + 0.5 Volts VIL Input LOW Voltage -0.5 0.8 Volts 1X Input Load Current VSS <VI< VCC -10 +10 uA 1OZ Output Leakage Current VCC < VO <VSS + 0.40 -10 +10 HA Ta = + 25C 65 130 Icc VCC Supply Current Ta =0C 75 150 mA co Output Capacitance (Note 14} 4 8 pF Cl Input Capacitance fe = 1.0 MHz, inputs = 0 V 8 15 pF clo 1/O Capacitance 10 18 pF COHREQ Output Capicitance (HREQ) fe = 1.0 MHz, Inputs =0 V 18 20 pF Notes: 1. Typical values are for Ta = 25C, nominal supply voltage and nominal processing parameters. Input timing parameters assume transition times of 20 ns or less. Waveform measurement points for both input and output signals are 2.0 2. V for HIGH and 0.8 V for LOW, unless otherwise noted. 3. Output loading is 1 Standard TTL gate plus 50 pF capacitance unless noted otherwise. 4. The new IOW or MEMW pulse width for normal write will be TCY-100 ns and for extended write will be 2TCY-100 ns. The net IOR or MEMR pulse width for normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns. 5. TDOQ is specified for two different output HIGH levels. TDQ1 is measured at 2.0 V. TOQ2 is measured at 3.3 V. The value for TDQ2 assumes an external 3.3 kQ pull-up resistor connected from HREQ to VCC. 6. DREQ should be held active until DACK is returned. 7. DREQ and DACK signals may be active high or active low. Timing diagrams assume the active high mode. 8. Output loading on the data bus is 1 Standard TTL gate plus 15 pF for the minimum value and 1 Standard TTL gate plus 100 pF for the maximum value. 9. Successive read and/or write operations by the external processor to program or examine the controller must be timed to allow at least 450 ns for the Am9517A-4/8237A-4, and 400 ns for the Am9517A-5/8237A-5 as recovery time between active read or write pulses. 10. Parameters are listed in alphabetical order. 11. Pin 5 is an input that should always be at a logic high level. An internal pull-up resistor will establish a logic high when the pin is left floating. Alternatively, pin 5 may be tied to VCC. 12. Signals READ and WRITE refer to JOR and MEMW respectively for peripheral-to-memory DMA operations and to MEMR and TOW respectively for memory-to-peripheral DMA operations. 13. |f N wait states are added during the write-to-memory half of a memory-to-memory transfer, this parameter will increase by N (TCY). 14, All output pins except HREQ. 15. Because EOP high from clock high is load dependent, users wishing to test these parameters should use a 2k pull-up resistor and a tester with 50 pF or less load capacitance. Time constant RC = 120 ns is added to the specified number in the data sheet for testing. SWITCHING TEST INPUT WAVEFORM 24 2.0 2.0 TEST POINTS o8 08 0.45 WF003310 1-240 Am9517A/8237AABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage temperature .-65 to +150C Military (M) Devices Voc with Respect to Vss see. 705 to +7.0 V Temperature (Tc) .-55 to + 125C All Signal Voltages with Respect to Vss ..-0.5 to +7.0 V Supply Voltage (Vcc) 5 V 10% Power Dissipation (Package Limitation) .................. 15 W Operating ranges define those limits between which the Stresses above those listed under ABSOLUTE MAXIMUM functionality of the device is guaranteed. RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over MILITARY operating range (for SMD/DESC and APL Products, Group A, Subgroups 1, 2, 3 are tested uniess otherwise noted) Parameter Parameter Symbol Description Test Conditions Min. Max. Unit Vou Output HIGH Voltage lon = -200 HA, Veo = 45 V 24 v joH =-100 WA, (HREQ Only) 3.3 VoL Output LOW Voltage lot = 3.2 mA, Voc = 5.5 V 0.45 V v Vin Input HIGH Voltage Voc = 4.5 V, 5.5 V 22 Voc + 0.5" Vv VIHCLK Input HIGH Voltage Voc = 4.5 V, 5.5 V (CLK Only) 2.35 Voc + 0.5" Vv Vit Input LOW Voltage Voc = 45 V, 5.5 V -0.5* 0.7 v Nx Input Load Current Vss <V) Voc. Voc = .5 V -10 +10 BA loz Output Leakage Current wes S9 , Vgg + 0.40, -10 +10 BA loc Voc Supply Current (Note 1) 150 mA Co t Output Capacitance (Note 12) 8* pF Gt Input Capacitance fe = 1.0 MHz, Inputs = 0 V 15 pF Cio VO Capacitance 18 pF * Guaranteed by design. + Not included in Group A tests. Notes: 1. loc is measured in a dynamic condition with outputs in a worst-case state having no loads applied. 2. Input timing parameters assume transition times of 20 ns or tess. Waveform measurement points for both input and output signals are 2.0 V for HIGH and 0.8 V for LOW, unless otherwise noted. 3. The new [OW or MEMW pulse width for normal write will be TCY-100 ns and for extended write will be 2TCY-100 ns. The net IOR or MEMR pulse width for normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns. 4. TDQ is specified for two different output HIGH levels. TOQ1 is measured at 2.0 V. TOQ2 is measured at 3.3 V. The value for TDQ2 assumes an external 3.3 k92 pull-up resistor connected from HREQ to Vcc. DREQ should be held active until DACK is returned. DREQ and DACK signals may be active HIGH or active LOW. Timing diagrams assume the active-HIGH mode. Successive read and/or write operations by the external processor to program or examine the controller must be timed to allow at least 600 ns for the Am9517A, at least 450 ns for the Am9517A-4 as recovery time between active read or write pulses. Parameters are listed in alphabetical order. Pin 5 is an input that should always be at a logic-HIGH level. An internal pull-up resistor will establish a logic HIGH when the pin is left floating. Alternatively, pin 5 may be tied to Vcc. 10. Signals READ and WAITE refer to TOR and MEMW respectively for peripheral-to-memory DMA operations and to MEMR and Tow respectively for memory-to-peripheral DMA operations. 11. If N wait states are added during the write-to-memory half of a memory-to-memory transfer, this parameter will increase by N (TCY). 12. Atl output pins except HREQ. 13. Because EOP HIGH from clock HIGH is toad-dependent, users wishing to test these parameters should use a 2k pull-up resistor and a tester with 50 pF or less load capacitance. Time constant Rc = 120 ns is added to the specified number in the data sheet for testing. NO @2@ Am9517A/8237A 1-241SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified ACTIVE CYCLE (Notes 2, 3, 10, 11, and 12) Am9517A-4/8237A-4 Am9517A-5/8237A-5 Parameters Description Min Max Min Max Units TAEL AEN HIGH from CLK LOW (S1) Delay Time 225 200 ns TAET AEN LOW from CLK HIGH (St) Delay Time 150 130 ns TAFAB ADR Active to Float Delay from CLK HIGH 4120 90 ns TAFC READ or WRITE Float from CLK HIGH 120 120 ns TAFDB OB Active to Float Delay from CLK HIGH 190 170 ns TAHR ADR from READ HIGH Hold Time TCY-100 TCY-100 ns TAHS DB from ADSTB LOW Hold Time 30 30 ns TAHW ADA from WRITE HIGH Hold Time TCY-50 TCY-50 ns DACK Valid from CLK LOW Delay Time 220 170 ns TAK . EOP HIGH from CLK HIGH Delay Time 190 170 ns EOP LOW to CLK HIGH Delay Time 190 170 ns TASM ADR Stable from CLK HIGH 190 170 ns TASS OB to ADSTB LOW Set-up Time 100 100 ns TCH Clock High Time (Transitions < 10ns)} 100 80 ns TCL Clock Low Time (Transitions < 10ns) 110 68 ns TcY CLK Cycle Time 250 200 ns TOCL CLK HIGH to READ or WRITE LOW Delay (Note 4) 200 190 ns TDCTR Read HIGH from CLK HIGH ($4) Delay Time (Note 4) 210 190 ns TOCTW WRITE HIGH from CLK HIGH (S4) Delay Time (Note 4) 450 130 ns Toa 420 120 ns Tpa2 HREQ Valid from CLK HIGH Delay Time (Note 5) 190 720 ne TEPS EOP LOW from CLK LOW Set-up Time 45 40 ns TEPW EOP Pulse Width 225 220 ns TFAAB ADR Float to Active Delay from CLK HIGH 190 170 ns TFAC READ or WRITE Active from CLK HIGH 150 150 ns TFADB DB Float to Active Delay from CLK HIGH 225 200 ns THS HACK Valid to CLK HIGH Set-up Time 75 75 ns TIDH Input Data from MEMR HIGH Hold Time 0 0 ns TIDS Input Data to MEMR HIGH Set-up Time 190 170 ns TODH Output Data from MEMW HIGH Hold Time 20 10 ns TODV Output Data Valid to MEMW HIGH (Note 13) 125 125 ns Tas DREQ to CLK LOW (S1, S4) Set-up Time 0 0 ns TRH CLK to READY LOW Hold Time 20 20 ns TRS READY to CLK LOW Set-up Time 60 60 ns TSTL AOSTB HIGH from CLK HIGH Delay Time 150 130 ng TSTT ADSTB LOW from CLK HIGH Delay Time 110 90 ns TQH DREQ from DACK Valid Hold Time 0 0 ns TROQHA HREQ to HACK Delay Time 1 1 c/k PROGRAM CONDITION (idie Cycle) (Notes 2, 3, 10, and 11) TAR ADR Valid or TS LOW to READ Low 50 50 ns TAW ADR Valid to WRITE HIGH Set-up Time 150 130 ns TCW CS LOW to WRITE HIGH Set-up Time 150 130 ns TOW Data Valid to WRITE HIGH Set-up Time 150 130 ns TRA ADR or CS Hold from READ HIGH 0 0 ns TRDE Data Access from READ LOW (Note 8) 200 140 ns TROF DB Fioat Delay from READ HIGH 20 100 0 70 ns TRSTD Power Supply HIGH to RESET LOW Set-up Time 500 500 us TRSTS RESET to First IOWR 2TCY 2TCY ns TRSTW RESET Pulse Width 300 300 ns TRW READ Width 250 200 ns TWA ADR from WRITE HIGH Hold Time 20 20 ns Two CS HIGH from WRITE HIGH Hold Time 20 20 ns TWD Data from WRITE HIGH Hold Time 30 30 ns Twws Write Width 200 160 ns Notes: See notes under OC Characteristics tabie. 1-242 Am9517A/8237ASWITCHING CHARACTERISTICS over MILITARY operating range (for SMD/DESC and APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) ACTIVE CYCLE (Notes 2, 8, 9, and 10) Am9517A Am9517A-4 Parameters Description Min. Max. Min. Max. Unit TAEL AEN HIGH from CLK LOW (S1)} Delay Time 300 225 ns TAET AEN LOW from CLK HIGH (S1) Delay Time 200 150 ns TAFAB ADR Active to Float Delay from CLK HIGH 150 120 ns TAFC READ or WRITE Float from CLK HIGH 150 120 ns TAFDB DB Active to Float Delay from CLK HIGH 250 190 ns TAHR ADR from READ HIGH Hold Time TCY-100 TCY-100 ns TAHS DB from ADSTB LOW Hold Time 30 30 ns TAHW ADR from WRITE HIGH Hold Time TCY-50 TCY-50 ns DACK Valid from CLK LOW Delay Time 280 220 ns TAK EOP HIGH from CLK HIGH Delay Time 250 190 ns EOP LOW to CLK HIGH Delay Time 250 190 ns TASM ADR Stable from CLK HIGH 250 190 ns TASS DB to ADSTB LOW Setup Time 100 100 ns TCH Clock High Time (Transitions < 10ns) 120 100 ns TCL Clock Low Time (Transitions < 10ns) 150 110 ns TCY CLK Cycle Time 320 250 ns TOCL CLK HIGH to READ or WRITE LOW Delay (Note 3) 270 200 ns TOCTR Read HIGH from CLK HIGH (S4) Delay Time (Note 3) 270 210 ns TDOCTW WRITE HIGH from CLK HIGH ($4) Delay Time (Note 3) 200 150 ns TDA! 160 120 ns Toae2 HREQ Valid from CLK HIGH Delay Time (Note 4) 2TCY + 250 2TCY + 190 ns TEPS EOP LOW from CLK LOW Setup Time 60 45 ns TEPW EOP Pulse Width 300 225 ns TFAAB ADR Float to Active Delay from CLK HIGH 250 190 ns TFAC READ or WRITE Active from CLK HIGH 200 150 ns TFAOB DB Float to Active Delay from CLK HIGH 300 225 ns THS HACK Valid to CLK HIGH Setup Time 100 75 ns TIDH input Data from MEMR HIGH Hold Time 0 0 ns TIDS Input Data to MEMR HIGH Setup Time 250 190 ns TODH Output Data from MEMW HIGH Hold Time 20 20 ns TODV Output Data Valid to MEMW HIGH (Note 11) 200 125 ns TAS DREQ to CLK LOW (S1, S4) Setup Time 0 0 ns TRH CLK to READY LOW Hold Time 20 20 ns TRS READY to CLK LOW Setup Time 100 60 ns TSTt ADSTB HIGH from CLK HIGH Delay Time 200 150 ns TSTT ADSTB LOW from CLK HIGH Delay Time 140 110 ns TQH DREQ from DACK Valid Hold Time 0 0 ns TRQHA HREQ to HACK Delay Time 1 1 elk AG Device Test Conditions: Vcc = 4.5 V, 5.5 V Vir = 0.45 V, Vin = 2.4 V Vo. = 0.8 V, Von = 2.0 V lol = 3.2 MA, [oH = 200 pA CL = 100 pF +20 pF Notes: See notes following DC Characteristics. Am9517A/8237A 1-243SWITCHING CHARACTERISTICS over MILITARY operating range (continued) PROGRAM CONDITION (idle Cycle) (Notes 2, 3, 10, and 11) Am9517A Am9517A-4 Parameters Description Min. Max. Min. Max. Unit TAR ADR Valid or TS LOW to READ LOW 50 50 ns TAW AOR Valid to WRITE HIGH Setup Time 200 150 ns TCW CS LOW to WRITE HIGH Setup Time 200 150 ns TOW Data Valid to WRITE HIGH Setup Time 200 150 ns TRA ADA or CS Hold from READ HIGH 0 0 ns TRDE Data Access from READ LOW (Note 8) 300 200 ns TRDF DB Float Delay from READ HIGH 20 150 20 100 ns TRSTD Power Supply HIGH to RESET LOW Setup Time 500 500 us TRSTS RESET to First IOWR 2TCY 2TCY ns TRSTW RESET Pulse Width 300 300 ns TRW READ Width 300 250 ns TWA ADR from WRITE HIGH Hold Time 20 20 ns TWG CS HIGH from WRITE HIGH Hold Time 20 20 ns TwD Data from WRITE HIGH Hold Time 30 30 ns TWWs Write Width 200 200 ns TAD Data, Access from ADR Valid TS LOW 300 300 ns Notes: See notes following DC Characteristics. 1-244 Am9517A/8237ASWITCHING WAVEFORMS Timing Diagram 1. Active Cycle Timing Diagram ht TFAAB ADDRESS VALID al As {FOR EXTENDED WRITE) Note: EOP must precede AEN in single transfer mode. WF003300 Am9517A/8237A 1-245SWITCHING WAVEFORMS (continued) Timing Diagram 2. Memory-to-Memory ADSTB ath fo-Tans ry jatans [rara| f AO-AT ___{ ADDRESS VALID x ADORESS VALID > TAFOB | aS TEADB | | pe0-DA7? ue AB- AIS In ouT TocT! | \ TRAOG | TRAC tao TOCL { TOOV TODH seme [T Tare EMR TIDS: |rocrw | \- TOCL i aeERW f NN iFoR exrenten WRITE) [op rax int E08 TEPW TEPS ~ WF003320 Timing Diagram 3. Ready Timing Timing Diagram 4. Compressed Timing 82 ey $2 s cuK i vase il aoa? I 4 | vao | VAUD ro. em oe TOCTR | | ws + |" | | ms WRITE TRH =] TRH TRS r 1RS ne WF003330 wenn (XX A XK) WF003340 Timing Diagram 5. Reset Timing TRSTW RESET L-_ T = A WF003350 TOR on 1OW 1-246 Am9517A/8237ASWITCHING WAVEFORMS (continued) Timing Diagram 6. Program Condition Write Timing -____ tw Bt pe | TWA TAW INPUT VALID ADA TOW 060-087 INPUT VALID WF003360 Timing Diagram 7. Program Condition Read Cycle aN a roar | bo TRA | TOR TRDE TADF _~ 80-087 DATA OUT VALID } WF003370 Am9517A/8237A 1-247