3D3428-0.5 - Data Delay Devices, Inc.

3D3428

MONOLITHIC 8-BIT

PROGRAMMABLE DELAY LINE

(SERIES 3D3428 – LOW NOISE)

FEATURES PACKAGES

• All-silicon, low-power CMOS technology

• 3.3V CMOS compatible inputs and outputs

• Vapor phase, IR and wave solderable

• Auto-insertable (DIP pkg.)

• Leading- and trailing-edge accuracy

• Programmable via serial or parallel interface

• Increment range: 0.25 through 15.0ns

• Delay tolerance: 0.5% (See Table 1)

• Supply current: 2mA typical

• Temperature stability: ±1.5% max (-40C to 85C)

• Vdd stability: ±1.0% max (3.0V to 3.6V)

FUNCTIONAL DESCRIPTION

The 3D3428 device is a versatile 8-bit programmable monolithic delay

line. The input (IN) is reproduced at the output (OUT) without inversion,

shifted in time as per the user selection. Delay values, programmed

either via the serial or parallel interface, can be varied over 255 equal

steps according to the formula:

Ti,nom = Tinh + i * Tinc

where i is the programmed address, Tinc is the delay increment (equal

to the device dash number), and Tinh is the inherent (address zero)

delay. The device features both rising- and falling-edge accuracy.

The all-CMOS 3D3428 integrated circuit has been designed as a reliable, economic alternative to hybrid

TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount

16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.

TABLE 1: PART NUMBER SPECIFICATIONS

delay

devices, inc.



PIN DESCRIPTIONS

IN Signal Input

OUT Signal Output

MD Mode Select

AE Address Enable

P0-P7 Parallel Data Input

SC Serial Clock

SI Serial Data Input

SO Serial Data Output

VDD +3.3 Volts

GND Ground

GND

VDD

OUT

3D3428Z-xx SOIC

SO/P0 MD

GND

VDD

OUT

3D3428-xx DIP

SO/P0

GND

VDD

OUT

3D3428S-xx SOL

For mechanical dimensions, click here.

For package marking details, click here.

PART DELAYS AND TOLERANCES INPUT RESTRICTIONS

NUMBER Inherent

Delay (ns)

Delay

Range (ns)

Delay

Step (ns)

Rec’d Max

Frequency

Absolute Max

Frequency

Rec’d Min

Pulse Width

Absolute Min

Pulse Width

3D3428-0.25 11.5 ± 2.0 63.75 ± 0.4 0.25 ± 0.15 6.25 MHz 77 MHz 80.0 ns 6.5 ns

3D3428-0.5 11.5 ± 2.0 127.5 ± 0.8 0.50 ± 0.25 3.12 MHz 45 MHz 160.0 ns 11.0 ns

3D3428-1 11.5 ± 2.0 255.0 ± 1.5 1.00 ± 0.50 1.56 MHz 22 MHz 320.0 ns 22.0 ns

3D3428-1.5 11.5 ± 2.0 382.5 ± 2.3 1.50 ± 0.75 1.04 MHz 15 MHz 480.0 ns 33.0 ns

3D3428-2 11.5 ± 2.0 510.0 ± 2.0 2.00 ± 1.00 781 KHz 11 MHz 640.0 ns 44.0 ns

3D3428-2.5 13.0 ± 2.5 637.5 ± 2.5 2.50 ± 1.25 625 KHz 9.0 MHz 800.0 ns 55.0 ns

3D3428-4 15.5 ± 4.0 1020 ± 4.0 4.00 ± 2.00 390 KHz 5.6 MHz 1280.0 ns 88.0 ns

3D3428-5 18.0 ± 5.0 1275 ± 4.0 5.00 ± 2.50 312 KHz 4.5 MHz 1600.0 ns 110.0 ns

3D3428-7.5 23.0 ± 7.5 1912.5 ± 6.0 7.50 ± 3.75 208 KHz 3.0 MHz 2400.0 ns 165.0 ns

3D3428-10 27.5 ± 10 2550 ± 8.0 10.0 ± 5.00 156 KHz 2.2 MHz 3200.0 ns 220.0 ns

3D3428-15 38.0 ± 15 3825 ± 12 15.0 ± 7.50 104 KHz 1.5 MHz 4800.0 ns 330.0 ns

NOTES: Any delay increment between 0.25 and 15 ns not shown is also available as standard.

See application notes section for more details 2004 Data Delay Devices

Doc #04004 DATA DELAY DEVICES, INC. 1

5/8/2006 3 Mt. Prospect Ave. Clifton, NJ 07013

3D3428

APPLICATION NOTES

The inherent delay error is the deviation of the

inherent delay from its nominal value. It is limited

to 1.0 LSB or 2.0 ns, whichever is greater.

GENERAL INFORMATION

The 8-bit programmable 3D3428 delay line

architecture is comprised of a number of delay

cells connected in series with their respective

outputs multiplexed onto the Delay Out pin (OUT)

by the user-selected programming data (the

address). Each delay cell produces at its output a

replica of the signal present at its input, shifted in

time. The change in delay from one address

setting to the next is called the increment, or

LSB. It is nominally equal to the device dash

number. The minimum delay, achieved by setting

the address to zero, is called the inherent delay.

DELAY STABILITY

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The 3D3428 utilizes novel compensation circuitry

to minimize the delay variations induced by

fluctuations in power supply and/or temperature.

With regard to stability, the delay of the 3D3428

at a given address, i, can be split into two

components: the inherent delay (T0) and the

relative delay (Ti – T0). These components exhibit

very different stability coefficients, both of which

must be considered in very critical applications.

For best performance, it is essential that the

power supply pin be adequately bypassed and

filtered. In addition, the power bus should be of

as low an impedance construction as possible.

Power planes are preferred. Also, signal traces

should be kept as short as possible.

The thermal coefficient of the relative delay is

limited to ±250 PPM/C (except for the dash 0.25),

which is equivalent to a variation, over the -40C

to 85C operating range, of ±1.5% (±9% for the

dash 0.25) from the room-temperature delay

settings. The thermal coefficient of the inherent

delay is nominally +20ps/C for dash numbers 5

or less, and +30ps/C for all other dash numbers.

DELAY ACCURACY

There are a number of ways of characterizing the

delay accuracy of a programmable line. The first

is the differential nonlinearity (DNL), also referred

to as the increment error. It is defined as the

deviation of the increment at a given address

from its nominal value. For most dash numbers,

the DNL is within 0.5 LSB at every address (see

Table 1: Delay Step).

The power supply sensitivity of the relative delay

is ±1.0% (±3.0% for the dash 0.25) over the 3.0V

to 3.6V operating range, with respect to the delay

settings at the nominal 3.3V power supply. This

holds for all dash numbers. The sensitivity of the

inherent delay is nominally –5ps/mV for all dash

numbers.

The integrated nonlinearity (INL) is determined

by first constructing the least-squares best fit

straight line through the delay-versus-address

data. The INL is then the deviation of a given

delay from this line. For all dash numbers, the

INL is within 1.0 LSB at every address.

INPUT SIGNAL CHARACTERISTICS

The frequency and/or pulse width (high or low) of

operation may adversely impact the specified

delay and increment accuracy of the particular

device. The reasons for the dependency of the

output delay accuracy on the input signal

characteristics are varied and complex.

Therefore a recommended maximum and an

absolute maximum operating input frequency and

a recommended minimum and an absolute

minimum operating pulse width have been

specified.

The relative error is defined as follows:

erel = (Ti – T0) – i * Tinc

where i is the address, Ti is the measured delay

at the i’th address, T0 is the measured inherent

delay, and Tinc is the nominal increment. It is very

similar to the INL, but simpler to calculate. For

most dash numbers, the relative error is less than

1.0 LSB at every address (see Table 1: Delay

Range).

OPERATING FREQUENCY

The absolute error is defined as follows:

The absolute maximum operating frequency

specification, tabulated in Table 1, determines

the highest frequency of the delay line input

signal that can be reproduced, shifted in time at

the device output, with acceptable duty cycle

eabs = Ti – (Tinh + i * Tinc)

where Tinh is the nominal inherent delay. The

absolute error is limited to 1.5 LSB or 3.0 ns,

whichever is greater, at every address.

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3D3428

APPLICATION NOTES (CONT’D)

distortion. Exceeding this limit will generally result

in no signal output.

The recommended maximum operating

frequency specification determines the highest

frequency of the delay line input signal for which

the output delay accuracy is guaranteed.

Exceeding this limit (while remaining within the

absolute limit) may cause some delays to shift

with respect to their values at low frequency. The

amount of delay shift will depend on the degree

to which the limit is exceeded.

To guarantee (if possible) the Table 1 delay

accuracy for input frequencies higher than the

recommended maximum frequency, the 3D3428

must be tested at the user operating frequency.

In this case, to facilitate production and device

identification, the part number will include a

custom reference designator identifying the

intended frequency of operation. The

programmed delay accuracy of the device is

guaranteed, therefore, only at the user specified

input frequency. Small input frequency variation

about the selected frequency will only marginally

impact the programmed delay accuracy, if at all.

Contact the factory for details.

OPERATING PULSE WIDTH

The absolute minimum operating pulse width

(high or low) specification, tabulated in Table 1,

determines the smallest pulse width of the delay

line input signal that can be reproduced, shifted

in time at the device output, with acceptable

pulse width distortion. Exceeding this limit will

generally result in no signal output.

The recommended minimum operating pulse

width (high or low) specification determines the

smallest pulse width of the delay line input signal

for which the output delay accuracy tabulated in

Table 1 is guaranteed. Exceeding this limit (while

remaining within the absolute limit) may cause

some delays to shift with respect to their values

at long pulse width. The amount of delay shift will

depend on the degree to which the limit is

exceeded.

To guarantee the Table 1 delay accuracy for

input pulse width smaller than the recommended

minimum operating pulse width, the 3D3428

must be tested at the user operating pulse width.

In this case, to facilitate production and device

identification, the part number will include a

custom reference designator identifying the

intended frequency and duty cycle of operation.

The programmed delay accuracy of the device is

guaranteed, therefore, only for the user specified

input characteristics. Small input pulse width

variation about the selected pulse width will only

marginally impact the programmed delay

accuracy, if at all.

PROGRAMMED DELAY UPDATE

A delay line is a memory device. It stores

information present at the input for a time equal

to the delay setting before presenting it at the

output with minimal distortion. The 3D3428 8-bit

programmable delay line can be represented by

256 serially connected delay elements

(individually addressed by the programming

data), each capable of storing data for a time

equal to the device increment (step time). The

delay line memory property, in conjunction with

the operational requirement of “instantaneously”

connecting the delay element addressed by the

programming data to the output, may inject

spurious information onto the output data stream.

In order to ensure that spurious outputs do not

occur, it is essential that the input signal be idle

(held high or low) for a short duration prior to

updating the programmed delay. This duration is

given by the maximum programmable delay.

Satisfying this requirement allows the delay line

to “clear” itself of spurious edges. When the new

address is loaded, the input signal can begin to

switch (and the new delay will be valid) after a

time given by tPDV or tEDV (see section below).

PROGRAMMING INTERFACE

Figure 1 illustrates the main functional blocks of

the 3D3428 delay program interface. Since the

3D3428 is a CMOS design, all unused input pins

must be returned to well defined logic levels,

VDD or Ground.

TRANSPARENT PARALLEL MODE (MD = 1,

AE = 1)

The eight program pins P0 - P7 directly control

the output delay. A change on one or more of

the program pins will be reflected on the output

delay after a time tPDV, as shown in Figure 2. A

bused.

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3D3428

APPLICATION NOTES (CONT’D)

LATCHED PARALLEL MODE

(MD = 1, AE PULSED)

The eight program pins P0 - P7 are loaded by the

falling edge of the Enable pulse, as shown in

Figure 3. After each change in delay value, a

settling time tEDV is required before the input is

accurately delayed.

SERIAL MODE (MD = 0)

While observing data setup (tDSC) and data hold

(tDHC) requirements, timing data is loaded in

MSB-to-LSB order by the rising edge of the clock

(SC) while the enable (AE) is high, as shown in

Figure 4. The falling edge of the enable (AE)

activates the new delay value which is reflected

at the output after a settling time tEDV. As data is

shifted into the serial data input (SI), the previous

contents of the 8-bit input register are shifted out

of the serial output port pin (SO) in MSB-to-LSB

order, thus allowing cascading of multiple

devices by connecting the serial output pin (SO)

of the preceding device to the serial data input

pin (SI) of the succeeding device, as illustrated in

Figure 5. The total number of serial data bits in a

cascade configuration must be eight times the

number of units, and each group of eight bits

must be transmitted in MSB-to-LSB order.

To initiate a serial read, enable (AE) is driven

high. After a time tEQV , bit 7 (MSB) is valid at the

serial output port pin (SO). On the first rising

edge of the serial clock (SC), bit 7 is loaded with

the value present at the serial data input pin (SI),

while bit 6 is presented at the serial output pin

(SO). To retrieve the remaining bits seven more

rising edges must be generated on the serial

clock line. The read operation is destructive.

Therefore, if it is desired that the original delay

setting remain unchanged, the read data must be

written back to the device(s) before the enable

(AE) pin is brought low.

The SO pin, if unused, must be allowed to float if

the device is configured in the serial

programming mode.

The serial mode is the only mode available on

the 8-pin version of the 3D3428.

PROGRAMMABLE

DELAY LINE

LATCH

8-BIT INPUT

OUT

P0 P1 P2 P3 P4 P5 P6 P7

MODE SELECT

SHIFT CLOCK

SERIAL INPUT

DDRESS ENABLE

SIGNAL IN SIGNAL OUT

SERIAL OUTPUT

PARALLEL INPUTS

Figure1: Functional block diagram

NEW VALUE

tPDX tPDV

PARALLEL

INPUTS

P0-P7

DELAY

TIME

Figure 2: Non-latched parallel mode (MD=1, AE=1)

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3D3428

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APPLICATION NOTES (CONT’D)

NEW VALUE

tEDX tEDV

PARALLEL

INPUTS

P0-P7

DELAY

TIME

tDSE tDHE

tEW

ENABLE

(AE)

Figure 3: Latched parallel mode (MD=1)

NEW

VALUE

NEW

BIT 7

NEW

BIT 0

NEW

BIT 6

OLD

BIT 7

OLD

BIT 6

OLD

BIT 0

ENABLE

(AE)

CLOCK

(SC)

SERIAL

INPUT

(

)

SERIAL

OUTPUT

(

)

DELAY

TIME

tEW

tES tCW tCW tEH

tDSC tDHC

tEGV tCQV tCQX tEQZ

tEDV

tEDX

PREVIOUS VALUE

Figure 4: Serial mode (MD=0)

FROM

WRITING

DEVICE

SI SO

3D3428 3D3428 3D3428

Figure 5: Cascading Multiple Devices

SI SO

TABLE 2: DELAY VS. PROGRAMMED ADDRESS

PROGRAMMED ADDRESS

PARALLEL P7 P6 P5 P4 P3 P2 P1 P0

NOMINAL DELAY (NS)

PER 3D3428 DASH NUMBER

SERIAL Msb

Lsb -0.25 -0.5 -1 -2 -5 -10 -15

STEP 0 0 0 0 0 0 0 0 0 11.50 11.5 11.5 11.5 18 27.5 38

STEP 1 0 0 0 0 0 0 0 1 11.75 12.0 12.5 13.5 23 37.5 53

STEP 2 0 0 0 0 0 0 1 0 12.00 12.5 13.5 15.5 28 47.5 68

STEP 3 0 0 0 0 0 0 1 1 12.25 13.0 14.5 17.5 33 57.5 83

STEP 4 0 0 0 0 0 1 0 0 12.50 13.5 15.5 19.5 38 67.5 98

STEP 5 0 0 0 0 0 1 0 1 12.75 14.0 16.5 21.5 43 77.5 113

STEP 253 1 1 1 1 1 1 0 1 74.75 138.0 264.5 517.5 1283 2557.5 3833

STEP 254 1 1 1 1 1 1 1 0 75.00 138.5 265.5 519.5 1288 2567.5 3848

STEP 255 1 1 1 1 1 1 1 1 75.25 139.0 266.5 521.5 1293 2577.5 3863

CHANGE 63.75 127.5 255.0 510.0 1275 2550.0 3825

3D3428

DEVICE SPECIFICATIONS

TABLE 3: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage VDD -0.3 7.0 V

Input Pin Voltage VIN -0.3 VDD+0.3 V

Input Pin Current IIN -10 10 mA 25C

Storage Temperature TSTRG -55 150 C

Lead Temperature TLEAD 300 C 10 sec

TABLE 4: DC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 3.0V to 3.6V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Static Supply Current* IDD 2.0 4.0 mA

High Level Input Voltage VIH 2.0 V

Low Level Input Voltage VIL 0.8 V

High Level Input Current IIH 1.0

µA VIH = VDD

Low Level Input Current IIL 1.0

µA VIL = 0V

High Level Output

Current

IOH -35.0 -4.0 mA VDD = 3.0V

VOH = 2.4V

Low Level Output Current IOL 4.0 15.0 mA VDD = 3.0V

VOL = 0.4V

Output Rise & Fall Time TR & TF 2.0 2.5 ns CLD = 5 pf

*IDD(Dynamic) = CLD * VDD * F Input Capacitance = 10 pf typical

where: CLD = Average capacitance load/line (pf) Output Load Capacitance (CLD) = 25 pf max

F = Input frequency (GHz)

TABLE 5: AC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 3.0V to 3.6V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Clock Frequency fC 80 MHz

Enable Width tEW 10 ns

Clock Width tCW 10 ns

Data Setup to Clock tDSC 10 ns

Data Hold from Clock tDHC 3 ns

Data Setup to Enable tDSE 10 ns

Data Hold from Enable tDHE 3 ns

Enable to Serial Output Valid tEQV 20 ns

Enable to Serial Output High-Z tEQZ 20 ns

Clock to Serial Output Valid tCQV 20 ns

Clock to Serial Output Invalid tCQX 10 ns

Enable Setup to Clock tES 10 ns

Enable Hold from Clock tEH 10 ns

Parallel Input Valid to Delay Valid tPDV 20 40 ns 1

Parallel Input Change to Delay Invalid tPDX 0 ns 1

Enable to Delay Valid tEDV 35 45 ns 1

Enable to Delay Invalid tEDX 0 ns 1

Input Pulse Width tWI 8 % of Total Delay See Table 1

Input Period Period 20 % of Total Delay See Table 1

Input to Output Delay tPLH, tPHL ns See Table 2

NOTES: 1 - Refer to PROGRAMMED DELAY UPDATE section

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3D3428

SILICON DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT: OUTPUT:

Ambient Temperature: 25oC ± 3oC Rload: 10KΩ ± 10%

Supply Voltage (Vcc): 3.3V ± 0.1V Cload: 5pf ± 10%

Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.

10KΩ

470Ω5pf

Device

Under

Test

Digital

Scope

Rise/Fall Time: 3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width: PWIN = 1.25 x Total Delay

Period: PERIN = 2.5 x Total Delay

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

OUT

TRIG

REF

TRIG

Figure 6: Test Setup

DEVICE UNDER

TEST (DUT)

DIGITAL SCOPE/

TIME INTERVAL COUNTER

PULSE

GENERATOR

OUTIN

COMPUTER

SYSTEM

PRINTER

Figure 7: Timing Diagram

tPLH tPHL

PERIN

PWIN

tRISE tFALL

0.60.6 1.51.5

2.4 2.4

1.51.5

VIH

VIL

VOH

VOL

INPUT

SIGNAL

OUTPUT

SIGNAL

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