N-Channel JFET Monolithic Dual $S7404 /SST405 /SST406 FEATURES Very LowNolse ........ Low Input Blas ......... e High Breakdown Voltage APPLICATIONS * Precision Instrumentation Input Amplifiers e Impedance Converters @n < 10 nV/VHz @ 10Hz Io < 2pA By > 50V CORPORATION a DESCRIPTION The SST404 Series is a very Low Noise Monolithic N-Channel JFET Pair in a surface mount SO-8 plastic package. Designed utilizing Calogics proprietary JFET processing techniques these devices are ideal for front end amplification of low level signals. The low noise, low leakage and good frequency response are excellent features for sensitive medical, instrumentation and infrared designs. ORDERING INFORMATION Part Package Temperature Range SST404-6 Plastic SO-8 -55C 10 +125C NOTE: For Sorted Chips in Carriers, See U401 Series PIN CONFIGURATIONS CJ2 TOP VIEW (1) si [] YL] we (3) (2) 01 (| TT) a2 (7) 3) a1 LL) 02 (6) (4) we LT 1] s2 (5) PRODUCT MARKING SST404 R04 SST405 RO5 SST406 ROG 8-56CORPORATION 4 14 14 calogic SST404 /SST405 /SST406 ABSOLUTE MAXIMUM RATINGS (Ta = 25C unless otherwise noted) Parameter/Test Condition Symbol Limit Unit Gate-Drain Voltage Veo -50 Vv Gate-Source Voltage Vas -50 Vv Forward Gate Current le 10 mA Power Dissipation (per side) Pp 300 mw (total) 500 mW Power Derating (per side) 2.4 mW/ C (total) 4 mW/ C Operating Junction Temperature Ty -55 to 150 C Storage Temperature Tetg -55 to 200 C Lead Temperature (1/16 from case for 10 seconds) TL 300 ae) ELECTRICAL CHARACTERISTICS (Ta = 25C unless otherwise noted) ,| SST404 | SST405 | SST406 SYMBOL CHARACTERISTCS TYP UNIT TEST CONDITIONS MIN [MAX] MIN [MAX| MIN (MAX STATIC ViBR)GSs Gate-Source Breakdown Voltage -58 | -50 -50 -50 Iq =-1pA, Vos = OV ViarjGi - G2 Gate-Gate Breakdown Voltage -8 | +50 +50 +50 Vv Iq =+1pA, Vos = OV, Vas = OV Vas(orF) Gate-Source Cut off Voltage -1.5 |-0.5 | -2.5] -0.5 | -2.5]-0.5 | -2.5 Vos = 15V, Ip = 1nA loss Saturation Drain Current # 3.5 |05]10]05]10]05] 10] mA _ |Vos=15V, Vas = 0V lass Gate Reverse Current 2 25 28 25 pA | Vas = -30V, Vos = OV 1 nA |Ta=126 | Iq Gate Operating Current 2 18 6 18] PA [Noa = 15V, Ip = 200nA -0.8 10 -10 -10[ nA |[Ta=125C | DS(ON) Drain-Source On-Resistance 250 Q [Ves =O0V, lp =0.1mA Ves Gate-Source Voltage 4 -2.3 -2.3 -2.3 y Voe = 15V, Ip = 20014 Vasir) Gate-Source Forward Voltage 0.7 IG = ImA, Vps = OV DYNAMIC ts Common-Source Forward Transconductance | 1.5] 1] 2] 1 | 2] 1 | 2 mS_| VOG = 15V, Ip = 200A gos Common-Source Output Conductance 1.3 2 2 2 us [f= 1kHz Gis Common-Source Forward Transconductance | 1.5] 2] 7] 2 | 7 |] 2] 7 VDS = 10V, Veg = OV Gos Common-Source Output Conductance 10 20 20 20 f= 1kHz Ciss Common-Source Input Capacitance 8 8 8 g |Voa= 15V, Ip = 200uA Ciss Common-Source Reverse Transfer Capacitance | 1.5 3 3 3 P f= 1MHz en Equivalent Input Noise Voltage 10 20 20 20 [nw Hz oor 5V, Ib = 200HA MATCHING | Vasi - Vase | | Differential Gate-Source Voltage 15 20 40 | mV_ | Vpe = 10V, Ip = 200,A A] Vas1 - Vase || Gate-Source Voltage Differential Change with 25 40 80 on | TA= 785 to 25C I yng = 10V, AT Temperature 25 40 eo | Ta = 25 to 126C | |0 = 200uA CMRR Common Mode Rejection Ratio 102 | 95 90 dB | Vpa = 10 to 20V, Ip = 200A NOTES: 1. For design aid only, not subject to production testing. 2. Pulse test; PW = 300us, duty cycle < 3%. 8-57