v2.3 TM Axcelerator Family FPGAs u e Leading-Edge Performance * * * * - 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications * * * * * Up to 2 Million Equivalent System Gates Up to 684 I/Os Up to 10,752 Dedicated Flip-Flops Up to 295 kbits Embedded SRAM/FIFO Manufactured on Advanced 0.15 m CMOS Antifuse Process Technology, 7 Layers of Metal Features * * * * * Single-Chip, Nonvolatile Solution Up to 100% Resource Utilization with 100% Pin Locking 1.5V Core Voltage for Low Power Footprint Compatible Packaging Flexible, Multi-Standard I/Os: - 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation - Bank-Selectable I/Os - 8 Banks per Chip - Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3V PCI-X - Differential I/O Standards: LVPECL and LVDS Table 1 * Axcelerator Family Product Profile Device Capacity (in Equivalent System Gates) Typical Gates Modules Register (R-cells) Combinatorial (C-cells) Maximum Flip-Flops Embedded RAM/FIFO Number of Core RAM Blocks Total Bits of Core RAM Clocks (Segmentable) Hardwired Routed PLLs I/Os I/O Banks Maximum User I/Os Maximum LVDS Channels Total I/O Registers Package CSP PQFP BGA FBGA CQFP CCGA October 2004 (c) 2004 Actel Corporation * * * * * * * Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 - Registered I/Os - Hot-Swap Compliant I/Os (except PCI) - Programmable Slew Rate and Drive Strength on Outputs - Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory: - Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18, x36 Organizations Available) - Independent, Width-Configurable Read and Write Ports - Programmable Embedded FIFO Control Logic Segmentable Clock Resources Embedded Phase-Locked Loop: - 14-200 MHz Input Range - Frequency Synthesis Capabilities up to 1 GHz Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Actel Silicon Explorer II Boundary-Scan Testing Compliant with IEEE Standard 1149.1 (JTAG) FuseLock TM Secure Programming Technology Prevents Reverse Engineering and Design Theft AX125 125,000 82,000 AX250 250,000 154,000 AX500 500,000 286,000 AX1000 1,000,000 612,000 AX2000 2,000,000 1,060,000 672 1,344 1,344 1,408 2,816 2,816 2,688 5,376 5,376 6,048 12,096 12,096 10,752 21,504 21,504 4 18,432 12 55,296 16 73,728 36 165,888 64 294,912 4 4 8 4 4 8 4 4 8 4 4 8 4 4 8 8 168 84 504 8 248 124 744 8 336 168 1,008 8 516 258 1,548 8 684 342 2,052 208 208 256, 484 208, 352 484, 676 208, 352 729 484, 676, 896 352 624 896, 1152 352 624 180 256, 324 i *See Actel's website for the latest version of the datasheet. Axcelerator Family FPGAs Ordering Information AX1000 _ 1 FG 896 I Application Blank = Commercial (0 to +70 C) PP = Pre-Production I = Industrial (-40 to +85 C) M = Military (-55 to +125 C) B = MIL-STD-883 Class B Package Lead Count Package Type BG = Ball Grid Array (1.27mm pitch) FG = Fine Ball Grid Array (1.0mm pitch) CS = Chip Scale Package (0.8mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) CQ = Ceramic Quad Flat Pack (0.5mm pitch) CG = Ceramic Column Grid Array Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard 3 = Approximately 35% Faster than Standard Part Number AX125 = 125,000 Equivalent System Gates AX250 = 250,000 Equivalent System Gates AX500 = 500,000 Equivalent System Gates AX1000 = 1,000,000 Equivalent System Gates AX2000 = 2,000,000 Equivalent System Gates Device Resources User I/Os (Including Clock Buffers) Package AX125 AX250 AX500 AX1000 AX2000 CS180 98 - - - - PQ208 - 115 115 - - CQ208 - 115 115 - - FG256 138 138 - - - FG324 168 - - - - CQ352 - 198 198 198 198 FG484 - 248 317 317 - CG624 - - - 418 418 FG676 - - 336 418 - BG729 - - - 516 - FG896 - - - 516 586 FG1152 - - - - 684 Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint compatible with one another. ii v2.3 Axcelerator Family FPGAs Temperature Grade Offerings Package AX125 AX250 AX500 AX1000 AX2000 CS180 C, I - - - - PQ208 - C, I, M C, I, M - - CQ208 - M, B M, B - - FG256 C, I C, I, M - - - FG324 C, I - - - - CQ352 - M, B M, B M, B M, B FG484 - C, I, M C, I, M C, I, M - CG624 - - - M, B M, B FG676 - - C, I, M C, I, M - BG729 - - - C, I, M - FG896 - - - C, I, M C, I, M FG1152 - - - - C, I, M Note: C = Commercial I = Industrial M = Military B = MIL-STD-883 Class B Speed Grade and Temperature Grade Matrix Std -1 -2 -3 C I M - - B - - Packaging Data Refer to the following documents located on the Actel website for additional packaging information. Package Mechanical Drawings Package Thermal Characteristics and Weights Hermatic Package Mechanical Information Contact your local Actel representative for device availability. v2.3 iii Axcelerator Family FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Low Power (LP) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Detailed Specifications Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Voltage-Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 Axcelerator Clock Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92 Package Pin Assignments 180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 729-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 324-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 iv v2.3 Axcelerator Family FPGAs Table of Contents 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88 624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 v2.3 v Axcelerator Family FPGAs General Description Axcelerator offers high performance at densities of up to two million equivalent system gates. Based upon the Actel AX architecture, Axcelerator has several systemlevel features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, lowimpedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the Axcelerator family abundant routing resources. Device Architecture Actel's AX architecture, derived from the highlysuccessful SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike in traditional FPGAs, the entire floor of the Axcelerator device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. The very nature of Actel's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (FuseLock technology). Cloning is impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "Security" on page 2-91). Programmable Interconnect Element The Axcelerator family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on Routing Switch Matrix Logic Block Sea-of-Modules Architecture Traditional FPGA Architecture Logic Modules Figure 1-1 * Sea-of-Modules Comparison v2.3 1-1 Axcelerator Family FPGAs Figure 1-2 * Axcelerator Family Interconnect Elements Logic Modules Actel's Axcelerator family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The can implement more than 4,000 combinatorial functions of up to five inputs (Figure 1-3 on page 1-3). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (Figure 1-3 on page 1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. Two C-cells, a single R-cell, and two Transmit (TX) and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (Figure 1-4 on page 1-3). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-route tool, minimizing system delays while improving logic utilization. 1 -2 v2.3 The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by-side, giving a C-C-R - C-C-R pattern to the SuperCluster. This C-C-R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5 on page 1-3). The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the AX1000 is composed of a 3x3 array of nine core tiles. Surrounding the array of core tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1 on page 1-3). Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the AX250). The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6 on page 1-4). Axcelerator Family FPGAs FCI A[1:0] B[1:0] C-cell D[3:0] DB D E CLK Y PSET Q CLR CFN (Positive Edge Triggered) FCO C-Cell R-Cell Figure 1-3 * AX C-Cell and R-Cell C C R TX TX RX RX B TX TX RX RX C C R Figure 1-4 * AX SuperCluster FCI DCOUT C-Cell C-Cell Y Y Carry Logic FCO Figure 1-5 * AX 2-bit Carry Logic Table 1-1 * Number of Core Tiles per Device Device Number of Core Tiles AX125 1 regular tile AX250 4 smaller tiles AX500 4 regular tiles AX1000 9 regular tiles AX2000 16 regular tiles v2.3 1-3 Axcelerator Family FPGAs SuperCluster C 4k RAM/ FIFO 4k RAM/ FIFO Chip Layout 4k RAM/ FIFO 4k RAM/ FIFO C R TX TX RX RX RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC HD HD HD HD HD HD HD HD HD HD HD HD HD RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC SC SCTile SC Core B TX TX RX RX C C R SC I/O Structure See Figure 7 Figure 1-6 * AX Device Architecture (AX1000 shown) Embedded Memory As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspectratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well 1 -4 v2.3 as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. I/O Logic The Axcelerator family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all, Axcelerator FPGAs support at least 14 different I/O standards (single-ended, differential, voltage-referenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see "User I/Os" on page 2-10 for more information). All I/O standards are available in each bank. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7 on page 1-5). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module. Axcelerator Family FPGAs I/O Module InReg OutReg EnReg I O B A N K 4k RAM/ FIFO I/O Module RX TX TX RX RX B RX I/O Module I/O Cluster 4k RAM/ FIFO 4k RAM/ FIFO CoreTile 4k RAM/ FIFO Figure 1-7 * I/O Cluster Arrangement Routing The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. The AX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. Global Resources FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-3). CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the FCO output of one two-bit, C-cell carry logic to the FCI input of the twobit, C-cell carry logic of the SuperCluster below it. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. Each HCLK and CLK has an associated analog PLL (a total of eight per chip). Each embedded PLL can be used for clock delay minimization, clock delay adjustment, or clock frequency synthesis. The PLL is capable of v2.3 1-5 Axcelerator Family FPGAs Figure 1-8 * AX Routing Structures operating with input frequencies ranging from 14 MHz to 200 MHz and can generate output frequencies between 20 MHz and 1 GHz. The clock can be either divided or multiplied by factors ranging from 1 to 64. Additionally, multiply and divide settings can be used in any combination as long as the resulting clock frequency is between 20 MHz and 1 GHz. Adjacent PLLs can be cascaded to create complex frequency combinations. The PLL can be used to introduce either a positive or a negative clock delay of up to 3.75 ns in 250 ps increments. The reference clock required to drive the PLL can be derived from three sources: external input pad (either single-ended or differential), internal logic, or the output of an adjacent PLL. Low Power (LP) Mode The AX architecture was created for high-performance designs but also includes a low power mode (activated via the LP pin). When the low power mode is activated, I/O banks can be disabled (inputs disabled, outputs tristated), and PLLs can be placed in a power-down mode. All internal register states are maintained in this mode. Furthermore, individual I/O banks can be configured to opt out of the LP mode, thereby giving the designer access to critical signals while the rest of the chip is in low power mode. The power can be further reduced by providing an external voltage source (VPUMP) to the device to bypass the internal charge pump (See "Low Power Mode" on page 2-90 for more information). 1 -6 v2.3 Design Environment The Axcelerator family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on Actel's website). Libero IDE includes Synplify(R) Actel Edition (AE) from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), and Designer software from Actel. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: * * * * * * Timer - a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route NetlistViewer - a design netlist schematic viewer ChipPlanner - a graphical floorplanner viewer and editor SmartPower - allows the designer to quickly estimate the power consumption of a design PinEditor - a graphical application for editing pin assignments and I/O attributes I/O Attribute Editor - displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format Axcelerator Family FPGAs In-System Diagnostic and Debug Capabilities With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel's back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. The Axcelerator family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation. Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II (Figure 1-9), Actel's integrated verification and logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG port (See "Silicon Explorer II Probe Interface" on page 2-92). Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Summary Programming Actel's Axcelerator family of FPGAs extends the successful SX-A architecture, adding embedded RAM/ FIFOs, PLLs, and high-speed I/Os. With the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an Axcelerator design yet still achieve high performance and efficient device utilization. Programming support is provided through Actel's Silicon Sculptor II, a single-site programmer driven via a PCbased GUI. In addition, BP Microsystems offers multi-site programmers that provide qualified support for Actel devices. Factory programming is available for highvolume production needs. Axcelerator FPGAs 16 Pin Connection TDI TCK Serial Connection TMS Silicon Explorer II TDO PRA PRB 22 Pin Connection CH3/PRC CH4/PRD Additional 14 Channels (Logic Analyzer) Figure 1-9 * Probe Setup v2.3 1-7 Axcelerator Family FPGAs Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.actel.com/documents/SSO.pdf Axcelerator Family PLL and Clock Management http://www.actel.com/documents/AX_PLL_AN.pdf Implementing DDR Transmit in Axcelerator http://www.actel.com/documents/AX_DDR_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/AntifuseSecurityAN.pdf User's Guides and Manuals Antifuse Macro Library Guide http://www.actel.com/documents/libguide.pdf ACTgen Macros User's Guide http://www.actel.com/documents/genguide.pdf Silicon Sculptor II User's Guide http://www.actel.com/techdocs/manuals/default.asp White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity.pdf Understanding Actel Antifuse Device Security http://www.actel.com/documents/ AntifuseSecurityWP.pdf Miscellaneous Libero IDE flow diagram http://www.actel.com/products/tools/libero/flow.html 1 -8 v2.3 Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommendations in Table 2-2. Table 2-1 * Absolute Maximum Ratings Symbol Parameter Limits Units VCCA DC Core Supply Voltage -0.3 to 1.6 V VCCI DC I/O Supply Voltage -0.3 to 3.75 V VREF DC I/O Reference Voltage -0.3 to 3.75 V VI Input Voltage -0.5 to 3.75 V VO Output Voltage -0.5 to 3.75 V TSTG Storage Temperature -60 to +150 C VCCDA* Supply Voltage for Differential I/Os -0.3 to 3.75 V Note: * Should be the maximum of all VCCI. Table 2-2 * Recommended Operating Conditions Parameter Range Commercial Industrial Military Units 0 to +70 -40 to +85 -55 to +125 C 1.5V Core Supply Voltage 1.425 to 1.575 1.425 to 1.575 1.425 to 1.575 V 1.5V I/O Supply Voltage 1.425 to 1.575 1.425 to 1.575 1.425 to 1.575 V 1.8V I/O Supply Voltage 1.71 to 1.89 1.71 to 1.89 1.71 to 1.89 V 2.5V I/O Supply Voltage 2.375 to 2.625 2.375 to 2.625 2.375 to 2.625 V 3.3V I/O Supply Voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V VCCDA Supply Voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V VPUMP Supply Voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V Ambient Temperature (TA)* Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. Power-Up/Down Sequence All Axcelerator I/Os are tristated during power-up until normal device operating conditions are reached, when I/Os enter user mode. VCCDA should be powered up before (or coincidentally with) VCCA and VCCI to ensure the behavior of user I/Os at system start-up. Conversely, VCCDA should be powered down after (or coincidentally with) VCCA and VCCI. Note that VCCI and VCCA can be powered up in any sequence with respect to each other, provided the requirement with respect to VCCDA is satisfied. v2.3 2-1 Axcelerator Family FPGAs Calculating Power Dissipation Table 2-3 * Standby Current ICCA ICCDA ICCBANK ICCPLL Standby Current per Standby I/O Bank Standby Current, Current Differential (Core) I/O 2.5V VCCI 3.3V VCCI ICCCP Standby Current, Charge Pump Standby Current per PLL Active Bypassed mode Units Device Temperature AX125 Typical at 25C 1.5 1.5 0.2 0.3 0.2 0.3 0.01 70C 10 6 0.5 0.75 1 0.4 0.01 mA 85C 15 6 0.6 0.8 1 0.4 0.2 mA 125C 40 8 1 1.5 2 0.4 0.5 mA Typical at 25C 1.5 1.4 0.25 0.4 0.2 0.3 0.01 mA 70C 15 7 0.8 0.9 1 0.4 0.01 mA 85C 25 7 0.8 1 1 0.4 0.2 mA mA AX250 AX500 AX1000 AX2000 mA 125C 55 9 1.3 1.8 2 0.4 0.5 Typical at 25C 5 1.4 0.4 0.75 0.2 0.3 0.01 mA 70C 20 7 1 1.5 1 0.4 0.01 mA 85C 40 7 1 1.9 1 0.4 0.2 mA 125C 75 9 1.75 2.5 1.5 0.4 0.5 mA Typical at 25C 7.5 1.5 0.5 1.25 0.2 0.3 0.01 mA 70C 40 8 1.5 3 1 0.4 0.01 mA 85C 85 8 1.5 3.4 1 0.4 0.2 mA 125C 150 10 3 4 1.5 0.4 0.5 mA Typical at 25C 20 1.6 0.7 1.5 0.2 0.3 0.01 mA 70C 80 10 2 7 1 0.4 0.01 mA 85C 150 10 3 8 1 0.4 0.2 mA 125C 300 15 4 10 1.5 0.4 0.5 mA Note: ICCCP Active is the ICCDA or the Internal Charge Pump current. ICCCP Bypassed mode is the External Charge Pump current IIH (VPUMP pin). Table 2-4 * Default CLOAD/VCCI CLOAD (pF) VCCI (V) PLOAD (mw/MHz) P10 (mw/MHz) PI/O (mW/MHZ)* LVTTL 24mA High Slew 35 3.3 381.2 262.6 643.7 LVTTL 16mA High Slew 35 3.3 381.2 220.1 601.3 LVTTL 12mA High Slew 35 3.3 381.2 160.9 542.1 LVTTL 8mA High Slew 35 3.3 381.2 125.4 506.5 LVTTL 24mA Low Slew 35 3.3 381.2 164.2 545.4 LVTTL 16mA Low Slew 35 3.3 381.2 145.9 527.0 LVTTL 12mA Low Slew 35 3.3 381.2 133.6 514.8 LVTTL 8mA Low Slew 35 3.3 381.2 113.8 494.9 LVCMOS - 25 35 2.5 218.8 143.2 361.9 35 1.8 113.4 68.7 182.1 Single-Ended without VREF LVCMOS - 18 Note: *PI/O = P10 + 2 -2 CLOAD *VCCI2 v2.3 Axcelerator Family FPGAs Table 2-4 * Default CLOAD/VCCI (Continued) CLOAD (pF) VCCI (V) PLOAD (mw/MHz) P10 (mw/MHz) PI/O (mW/MHZ)* LVCMOS - 15 (JESD8-11) 35 1.5 78.8 44.9 123.6 PCI 10 3.3 108.9 213.5 322.4 PCI-X 10 3.3 108.9 158.0 266.9 HSTL-I 20 1.5 - 36.8 36.8 SSTL2-I 30 2.5 - 166.9 166.9 SSTL2-II 30 2.5 - 143.5 143.5 SSTL3-I 30 3.3 - 322.8 322.8 SSTL3-II 30 3.3 - 284.0 284.0 GTLP - 25 10 2.5 - TBD TBD GTLP - 33 10 3.3 - TBD TBD N/A 3.3 - 255.1 255.1 N/A 2.5 - 140.4 140.4 Single-Ended with VREF Differential LVPECL - 33 LVDS - 25 Note: *PI/O = P10 + Table 2-5 * CLOAD *VCCI2 Different Components Contributing to the Total Power Consumption in Axcelerator Devices Device Specific Value (in W/MHz) Component Definition AX125 AX250 AX500 AX1000 AX2000 P1 Core tile HCLK power component 33 49 71 130 216 P2 R-cell power component 0.2 0.2 0.2 0.2 0.2 P3 HCLK signal power dissipation 4.5 4.5 9 13.5 18 P4 Core tile RCLK power component 33 49 71 130 216 P5 R-cell power component 0.3 0.3 0.3 0.3 0.3 P6 RCLK signal power dissipation 6.5 6.5 13 19.5 26 P7 Power dissipation due to the switching activity on the R-cell 1.6 1.6 1.6 1.6 1.6 P8 Power dissipation due to the switching activity on the C-cell 1.4 1.4 1.4 1.4 1.4 P9 Power component associated with the input voltage 10 10 10 10 10 P10 Power component associated with the output voltage P11 Power component associated with the read operation in the RAM block 25 25 25 25 25 P12 Power component associated with the write operation in the RAM block 30 30 30 30 30 P13 Core PLL power component 1.5 1.5 1.5 1.5 1.5 See table Per pin contribution Ptotal = Pdc + Pac Pdc = ICCA * VCCA Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL v2.3 2-3 Axcelerator Family FPGAs PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs s = the number of R-cells clocked by this clock Fs = the clock frequency PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs s = the number of R-cells clocked by this clock Fs = the clock frequency PR-cells = P7 * ms * Fs ms = the number of R-cells switching at each Fs cycle Fs = the clock frequency PC-cells = P8 * mc * Fs mc = the number of C-cells switching at each Fs cycle Fs = the clock frequency Pinputs = P9 * pi * Fpi pi = the number of inputs Fpi = the average input frequency Poutputs = PI/O * po * Fpo Cload VCCI po Fpo = = = = the output load (technology dependent) the output voltage (technology dependent) the number of outputs the average output frequency Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK Nblock = the number of RAM/FIFO blocks (1 block = 4k) FRCLK = the read-clock frequency of the memory FWCLK = the write-clock frequency of the memory PPLL = P13 * FCLK FRefCLK = the clock frequency of the clock input of the PLL FCLK = the clock frequency of the first clock output of the PLL 2 -4 v2.3 Axcelerator Family FPGAs Power Estimation Example This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input, and one LVTTL 12mA Output, with High Slew. This design uses one HCLK at 100 MHz. ms = 1,080 (in a shift register - 100% of R-cells are toggling at each clock cycle) Fs s = 100 MHz = 1080 => PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 79 mW and Fs = 100 MHz => PR-cells = P7 * ms * Fs = 173 mW mc = 1 (1 C-cell in this shift-register) and Fs = 100 MHz => PC-cells = P8 * mc * Fs = 0.14 mW Fpi ~ 0 MHz and pi= 1 (1 reset input => this is why Fpi=0) => Pinputs = P9 * pi * Fpi = 0 mW Fpo = 50 MHz and po = 1 => Poutputs = PI/O * po * Fpo= 27.10 mW No RAM/FIFO in this shift-register => Pmemory = 0 mW No PLL in this shift-register => PPLL = 0 mW Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL = 276 mW Pdc = 7.5mA * 1.5V = 11.25 mW Ptotal = Pdc + Pac = 11.25 mW + 276mW = 290.30 mW v2.3 2-5 Axcelerator Family FPGAs Thermal Characteristics Introduction The temperature variable in Actel's Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ can be used to calculate junction temperature. T = ja * P TJ = Junction Temperature = T + Ta EQ 2-1 Where: Ta EQ 2-2 Where: = Ambient Temperature T = Temperature gradient (silicon) and ambient P between = Power ja = Junction to ambient of package. ja numbers are located under Table 2-6 on page 2-7. junction Package Thermal Characteristics The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. jc values are provided for reference. The absolute maximum junction temperature is 150C. The maximum power dissipation allowed for commercial- and industrial-grade devices is a function of ja. A sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and still air is as follows: 150C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 5.88W 13.6C/W ja (C/W) The maximum power dissipation allowed for Military temperature and Mil-Std 883B devices is specified as a function of jc. The calculation of the absolute maximum power dissipation allowed for a Military temperature or Mil-Std 883B application is illustrated in the following example for a 484-pin FBGA package: Max. junction temp. (C) - Max. case temp. (C) 150C - 125C Maximum Power Allowed = ----------------------------------------------------------------------------------------------------------------------------- = ---------------------------------------- = 7.815 W jc (C/W) 3.2C/W 2 -6 v2.3 Axcelerator Family FPGAs Table 2-6 * Package Thermal Characteristics Pin Count jc ja Still Air ja 1.0m/s ja 2.5m/s Units Chip Scale Package (CSP) 180 N/A 57.8 51.0 50 C/W Plastic Quad Flat Pack (PQFP) 208 8.0 26 23.5 20.9 C/W Plastic Ball Grid Array (PBGA) 729 2.2 13.7 10.6 9.6 C/W Fine Pitch Ball Grid Array (FBGA) 256 3.0 26.6 22.8 21.5 C/W Fine Pitch Ball Grid Array (FBGA) 324 3.0 25.8 22.1 20.9 C/W Fine Pitch Ball Grid Array (FBGA) 484 3.2 20.5 17.0 15.9 C/W Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 13.0 12.0 C/W Fine Pitch Ball Grid Array (FBGA) Hardwired 896 2.4 13.6 10.4 9.4 C/W Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12.0 8.9 7.9 C/W Ceramic Quad Flat Pack (CQFP)1 208 2.0 22 19.8 18.0 C/W 352 2.0 17.9 16.1 14.7 C/W 624 6.5 8.9 8.5 8 C/W Package Type Ceramic Quad Flat Pack (CQFP)1 2 Ceramic Column Grid Array (CCGA) Notes: 1. jc for the 208-pin and 352-pin CQFP refers to the thermal resistance between the junction and the bottom of the package. 2. jc for the 624-pin CCGA refers to the thermal resistance between the junction and the top surface of the package. Thermal resistance from junction to board (jb) for CCGA 624 package is 3.4 C/W. Timing Characteristics Axcelerator devices are manufactured in a CMOS process, therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-7 should be applied to all timing data contained within this datasheet. Table 2-7 * Temperature and Voltage Timing Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 1.425V) Junction Temperature VCCA -55C -40C 0C 25C 70C 85C 125C 1.4V 0.83 0.86 0.91 0.96 1.02 1.05 1.15 1.425V 0.82 0.84 0.90 0.94 1.00 1.04 1.13 1.5V 0.78 0.80 0.85 0.89 0.95 0.98 1.07 1.575V 0.74 0.76 0.81 0.85 0.90 0.94 1.02 1.6V 0.73 0.75 0.80 0.84 0.89 0.92 1.01 Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of -55C to 175C. 2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V. All timing numbers listed in this datasheet represent sample timing characteristics of Axcelerator devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel's Designer software after placeand-route. v2.3 2-7 Axcelerator Family FPGAs Timing Model I/O Module (Nonregistered) Carry Chain Combinatorial Cell tPY = 1.98 ns Combinatorial Cell I/O LVPECL FCO tPDC = 0.49 ns I/O tCCY = 0.53 ns I/O Module (Registered) + LVPECL tDP = 1.47 ns tRD2 = 0.46 ns Buffer Module Combinatorial Cell Buffer Module tPY = 2.63 ns Y tBFPD = 0.10 ns tPD = 0.64 ns tIOCKLQ = 0.59 ns tSUD = 0.20 ns tHCKH = 2.64 ns FMAX (external) = 350 MHz FMAX (internal) = 1 GHz D Q Combinatorial I/O Module Register Cell Cell t tRCO = 0.59 ns IOCLKY = 0.59 ns Buffer tRD1 = 0.39 ns tSUD = 0.20 ns tSUD = 0.20 ns Module D Q D Q Y tBPFD = 0.10 ns tPD = 0.64 ns tRCO = 0.59 ns tSUD = 0.20 ns tPY = 0.88 ns GTL + 3.3V tRCKL = 2.67 ns FMAX (external) = 350 MHz FMAX (internal) = 1 GHz Routed Clock tDP = 1.60 ns Hardwired or Routed Clock LVTTL Output Drive Strength = 4 (24mA) High Slew Rate Register Cell I/O Module (Non- registered) + tBFPD = 0.10 ns tRD1 = 0.39 ns tRD2 = 0.46 ns tRD3 = 0.48 ns Hardwired Clock LVDS I/O Module (Nonregistered) tHCKL = 2.98 ns tRCKL = 2.86 ns Note: Worst case timing data for the AX1000, -3 speed grade Figure 2-1 * Worst Case Timing Data Hardwired Clock - Using LVTTL 24mA High Slew Clock I/O Routed Clock - Using LVTTL 24mA High Slew Clock I/O External Setup External Setup = (tDP + tRD2 + tSUD) - tHCKL = (tDP + tRD2 + tSUD) - tRCKH = (1.50 + 0.46 + 0.20) - 2.64 = -0.48 ns = (1.50 + 0.46 + 0.20) - 2.72 = -0.56 ns Clock-to-Out (Pad-to-Pad) 2 -8 Clock-to-Out (Pad-to-Pad) = tHCKL + tRCO + tRD1 + tPYs = tRCKH + tRCO + tRD1 + tPY = 2.63 + 0.59 + 0.39 + 2.63 = 6.24 ns = 2.72 + 0.59 + 0.39 + 2.63 = 6.33 ns v2.3 Axcelerator Family FPGAs I/O Specifications Pin Descriptions Axcelerator Chip Supply Pins GND 250 1.5V Supply Ground Low supply voltage. VCCA VCCPLX 10f 0.1f Supply Voltage VCOMPLX Supply voltage for array (1.5V). See "Operating Conditions" on page 2-1 for more information. VCCIBx Supply Voltage Figure 2-2 * VCCPLX and VCOMPLX Power Supply Connect Supply voltage for I/Os. Bx is the I/O Bank ID - 0 to 7. See "Operating Conditions" on page 2-1 for more information. VCCDA User-Defined Supply Pins VREF Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF pins are not in fixed locations. There can be one or more VREF pins in an I/O bank. Supply Voltage Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. See "Operating Conditions" on page 2-1 for more information. VCCDA should be tied to 3.3V. Global Pins VCCPLA/B/C/D/E/F/G/H Supply Voltage HCLKA/B/C/D PLL analog power supply (1.5V) for internal PLL. There are eight in each device. VCCPLA supports the PLL associated with global resource HCLKA, VCCPLB supports the PLL associated with global resource HCLKB, etc. The PLL analog power supply pins should be connected to 1.5V whether PLL is used or not. Dedicated (Hardwired) Clocks A, B, C and D These pins are the clock input for sequential modules or north PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. VCOMPLA/B/C/D/E/F/G/HSupply Voltage Compensation reference signals for internal PLL. There are eight in each device. VCOMPLA supports the PLL associated with global resource HCLKA, VCOMPLE supports the PLL associated with global resource CLKE, etc. (see Figure 2-2 on page 2-9 for correct external connection to the supply). The VCOMPLX pins should be left floating if PLL is not used. VPUMP Supply Voltage CLKE/F/G/H Routed Clocks E, F, G, and H These pins are clock inputs for clock distribution networks or south PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. The clock input is buffered prior to clocking the R-cells. Supply Voltage (External Pump) In the low power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches VIH1. In normal device operation, when using the internal charge pump, VPUMP should be tied to GND. JTAG/Probe Pins PRA/B/C/D Probe A/B/C/D The Probe pins are used to output data from any userdefined design node within the device (controlled with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. The pins' probe capabilities can be permanently disabled to protect 1. When VPUMP = VIH, it shuts off the internal charge pump. See "Low Power Mode" on page 2-90. v2.3 2-9 Axcelerator Family FPGAs programmed design confidentiality. The probe pins are of LVTTL output levels. TCK Test Clock Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II). TDI Test Data Input Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal 10 k pull-up resistor. TDO Test Data Output Serial output for JTAG boundary-scan testing. TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is equipped with an internal 10 k pull-up resistor. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with a 10 k pull-up resistor. Special Functions LP Low Power Pin The LP pin controls the low power mode of Axcelerator devices. The device is placed in the low power mode by connecting the LP pin to logic high. To exit the low power mode, the LP pin must be set Low. Additionally, the LP pin must be set Low during chip powering-up or chip powering-down operations. See "Low Power Mode" on page 2-90 for more details. NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. User I/Os2 Introduction The Axcelerator family features a flexible I/O structure, supporting a range of mixed voltages (1.5V, 1.8V, 2.5V, and 3.3V) with its bank-selectable I/Os. Table 2-8 on page 2-11 contains the I/O standards supported by the Axcelerator family, and Table 2-10 on page 2-11 compares the features of the different I/O standards. Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. I/O standards, except 3.3V PCI and 3.3V PCI-X, are capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V tolerant with the aid of an external resistor. The input buffer has an optional user-configurable delay element. The element can reduce or eliminate the hold time requirement for input signals registered within the I/O cell. The value for the delay is set on a bank-wide basis. Note that the delay WILL be a function of process variations as well as temperature and voltage changes. Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg). I/Os are organized into banks, and there are eight banks per device -- two per side (Figure 2-6 on page 2-15). Each I/O bank has a common VCCI, the supply voltage for its I/Os. For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any user I/O in the bank can be selected to be a VREF. The location of the VREF pin should be selected according to the following rules: * Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each direction (16 total maximum) within the same I/O bank. * I/O pad locations listed as no connects are counted as part of the 16 maximum. In many cases, this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF pin. * Dedicated I/O pins (GND, VCCI...) are counted as part of the 16. * The two user I/O pads immediately adjacent on each side of the VREF pin (four in total) may only be used as an input. The exception is when there is a VCCI/ GND pair separating the VREF pin and the user I/O pad location. The differential amplifier supply voltage VCCDA should be connected to 3.3V. A user can gain access to the various I/O standards in three ways: * Instantiate specific library macros that represent the desired specific standard * Use generic I/O macros and then use Actel Designer's PinEditor to specify the desired I/O standards (please note that this is not applicable to differential standards) * A combination of the first two methods. Please refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library Guide for more details. 2. Do not use an external resister to pull the I/O above VCCI for a higher logic "1" voltage level. The desired higher logic "1" voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI. 2 -1 0 v2.3 Axcelerator Family FPGAs Table 2-8 * I/O Standards Supported by the Axcelerator Family Input/Output Supply Voltage (VCCI) Input Reference Voltage (VREF) Board Termination Voltage (VTT) LVTTL 3.3 N/A N/A LVCMOS 2.5V 2.5 N/A N/A LVCMOS 1.8V 1.8 N/A N/A LVCMOS 1.5V (JDEC8-11) 1.5 N/A N/A 3.3V PCI/PCI-X 3.3 N/A N/A GTL+ 3.3V 3.3 1.0 1.2 I/O Standard GTL+ 2.5V* 2.5 1.0 1.2 HSTL Class 1 1.5 0.75 0.75 SSTL3 Class 1 and II 3.3 1.5 1.5 SSTL2 Class1 and II 2.5 1.25 1.25 LVDS 2.5 N/A N/A LVPECL 3.3 N/A N/A Note: *2.5V GTL+ is not supported across the full military temperature range. Table 2-9 * Supply Voltages VCCA VCCI Input Tolerance Output Drive Level 1.5V 1.5V 3.3V 1.5V 1.5V 1.8V 3.3V 1.8V 1.5V 2.5V 3.3V 2.5V 1.5V 3.3V 3.3V 3.3V Table 2-10 * I/O Features Comparison I/O Assignment LVTTL Clamp Diode No Hot Insertion Yes 5V Tolerance Input Buffer Output Buffer 1 Enabled/Disabled 1, 2 Enabled/Disabled Yes 3.3V PCI, 3.3V PCI-X Yes No Yes LVCMOS2.5V No Yes No Enabled/Disabled LVCMOS1.8V No Yes No Enabled/Disabled LVCMOS1.5V (JESD8-11) No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Enabled/Disabled Differential, LVDS/LVPECL, Input No Yes No Enabled Disabled3 Differential, LVDS/LVPECL, Output No Yes No Disabled Enabled4 Notes: 1. 2. 3. 4. Can be implemented with an IDT bus switch. Can be implemented with an external resistor. The OE input of the output buffer must be deasserted permanently (handled by software). The OE input of the output buffer must be asserted permanently (handled by software). v2.3 2-11 Axcelerator Family FPGAs 5V Tolerance There are two schemes to achieve 5V tolerance: 1. 3.3V PCI and 3.3V PCI-X are the only I/O standards that directly allow 5V tolerance. To implement this, an internal clamp diode between the input pad and the VCCI pad is enabled so that the voltage at the input pin is clamped as shown in EQ 2-3: Vinput = VCCI + Vdiode = 3.3V + 0.8V = 4.1V EQ 2-3 An external series resister (~100) is required between the input pin and the 5V signal source to limit the current (Figure 2-3). Non-Actel Part 3.3V Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more information. I/O Banks and Compatibility Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output supply voltage (VCCI), only I/Os with compatible standards can be assigned to the same bank. Table 2-11 shows the compatible I/O standards for a common VREF (for voltage-referenced standards). Similarly, Table 2-12 shows compatible standards for a common VCCI. Actel FPGA 5V recommends that users not exceed eight simultaneous switching outputs (SSO) per each VCCI/GND pair. To ease this potential burden on designers, Actel has designed all of the Axcelerator BGAs3 to not exceed this limit with the exception of the CS180, which has an I/O to VCCI/GND pair ratio of nine to one. 3.3V PCI clamp diode Table 2-11 * Compatible I/O Standards for Different VREF Values Rext VREF Figure 2-3 * Use of an External Resistor for 5V Tolerance 2. 5V tolerance can also be achieved with 3.3V I/O standards (3.3V PCI, 3.3V PCI-X, and LVTTL) using a bus-switch product (e.g. IDTQS32X2384). This will convert the 5V signal to a 3.3V signal with minimum delay (Figure 2-4). Compatible Standards 1.5V SSTL 3 (Class I and II) 1.25V SSTL 2 (Class I and II) 1.0V GTL+ (2.5V and 3.3V Outputs) 0.75V HSTL (Class I) Table 2-12 * Compatible I/O Standards for Different VCCI Values VCCI1 Compatible Standards VREF 3.3V LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3V 1.0 3.3V 20X 3.3V SSTL 3 (Class I and II), LVTTL, PCI, LVPECL 1.5 2.5V LVCMOS 2.5V, GTL+ 2.5V, LVDS 1.0 3.3V 2.5V LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS2 1.25 1.8V LVCMOS 1.8V N/A Figure 2-4 * Bus Switch IDTQS32X2384 1.5V LVCMOS 1.5V, HSTL Class I 0.75 Simultaneous Switching Outputs (SSO) Notes: 5V 5V When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or more commonly, ground bounce. SSN becomes more of an issue in high pin count packages and when using high performance devices such as the Axcelerator family. Based upon testing, Actel 2 1. VCCI is used for both inputs and outputs 2. VCCI tolerance is 5% Table 2-13 on page 2-13 summarizes the different combinations of voltages and I/O standards that can be used together in the same I/O bank. Note that two I/O standards are compatible if: * Their VCCI values are identical. * Their VREF standards are identical (if applicable). 3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio. 2 -1 2 v2.3 Axcelerator Family FPGAs For example, if LVTTL 3.3V (VREF= 1.0V) is used, then the other available (i.e. compatible) I/O standards in the same bank are LVTTL 3.3V PCI/PCI-X, GTL+, and LVPECL. Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all I/O standards used in the bank. I/O Standard LVTTL 3.3V LVCMOS 2.5V LVCMOS1.8V LVCMOS1.5V (JESD8-11) 3.3V PCI/PCI-X GTL + (3.3V) GTL + (2.5V) HSTL Class I (1.5V) SSTL2 Class I & II (2.5V) SSTL3 Class I & II (3.3V) LVDS (2.5V) LVPECL (3.3V) Table 2-13 * Legal I/O Usage Matrix LVTTL 3.3V (VREF=1.0V) - - - - - - - - LVTTL 3.3V(VREF=1.5V) - - - - - - - - LVCMOS 2.5V (VREF=1.0V) - - - - - - - - - LVCMOS 2.5V (VREF=1.25V) - - - - - - - - - LVCMOS1.8V - - - - - - - - - - - LVCMOS1.5V (VREF=1.75V) (JESD8-11) - - - - - - - - - - 3.3V PCI/PCI-X (VREF=1.0V) - - - - - - - - 3.3V PCI/PCI-X (VREF=1.5V) - - - - - - - - GTL + (3.3V) - - - - - - - - GTL + (2.5V) - - - - - - - - - - HSTL Class I - - - - - - - - - - SSTL2 Class I & II - - - - - - - - - SSTL3 Class I & II - - - - - - - - LVDS (VREF=1.0V) - - - - - - - - - LVDS (VREF=1.25V) - - - - - - - - - LVPECL (VREF=1.0V) - - - - - - - - LVPECL (VREF=1.5V) - - - - - - - - Notes: 1. Note that GTL+ 2.5V is not supported across the full military temperature range. 2. A "" indicates whether standards can be used within a bank at the same time. Examples: a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when VREF = 1.0V (GTL+ requirement). b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when VREF = 1.5V (SSTL3 requirement). v2.3 2-13 Axcelerator Family FPGAs I/O CLUSTER routed input track OEP routed input track OutREg DIN YOUT routed input track UOP output track Y InReg DCIN BSR P PAD routed input track EnReg DIN YOUT UIP output track I/O slew rate drive strength programmable delay FPGA LOGIC CORE VREF N PAD EnReg DIN YOUT routed input track routed input track OutREg DIN YOUT routed input track output track Y InReg DCIN OEN UON output track UIN BSR routed input track I/O slew rate drive strength programmable delay VREF Figure 2-5 * I/O Cluster Interface I/O Clusters Each I/O cluster incorporates two I/O modules, four RX modules and two TX modules, and a buffer module. In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one Enable Register (EnReg) (Figure 2-5). Using an I/O Register To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os. Usage of each I/O register (register combining) is individually controlled and can be selected/deselected using the PinEditor tool in Actel's Designer software. I/O register combining can also be controlled at the device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any given design.4 In addition, Designer software provides a global option to enable/disable the usage of registers in the I/Os. This option is design-specific. The setting for each individual I/O overrides this global option. Furthermore, the global set fuse option in the Designer software, when checked, causes all I/O registers to output logic High at device power-up. Using the Weak Pull-Up and Pull-Down Circuits Each Axcelerator I/O comes with a weak pull-up/down circuit (on the order of 10 k). I/O macros are provided for combinations of pull up/down for LVTTL, LVCMOS (2.5V, 1.8V, and 1.5V) standards. These macros can be instantiated if a keeper circuit for any input buffer is required. Customizing the I/O * A five-bit programmable input delay element is associated with each I/O. The value of this delay is set on a bank-wide basis (Table 2-14 on page 2-15). It is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the I/O). When the input buffer drives a register within the I/O, the delay element is 4. Please note that register combining for multi fanout nets is not supported. 2 -1 4 v2.3 Axcelerator Family FPGAs Using the Voltage-Referenced I/O Standards activated by default to ensure a zero hold-time. The default setting for this property can be set in Designer. When the input buffer does not drive a register, the delay element is deactivated to provide higher performance. Again, this can be overridden by changing the default setting for this property in Designer. * The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast. * The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values - 8mA, 12mA, 16mA, or 24mA - that can be specified in Designer.5 Using these I/O standards is similar to that of singleended I/O standards. Their settings can be changed in Designer. Using DDR (Double Data Rate) In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very highspeed systems. To implement a DDR, users need to: 1. Instantiate an input buffer (with the required I/O standard) 2. Instantiate the DDR_REG macro (Figure 2-6) Table 2-14 * Bank-Wide Delay Values Bits Setting Delay (ns) Bits Setting 3. Connect the output from the Input buffer to the input of the DDR macro Delay (ns) 0 0.54 16 2.01 1 0.65 17 2.13 2 0.71 18 2.19 D PSET QR 3 0.83 19 2.3 4 0.9 20 2.38 D 5 1.01 21 2.49 6 1.08 22 2.55 CLK CLR 7 1.19 23 2.67 8 1.27 24 2.75 Figure 2-6 * DDR Register 9 1.39 25 2.87 Macros for Specific I/O Standards 10 1.45 26 2.93 11 1.56 27 3.04 12 1.64 28 3.12 13 1.75 29 3.23 There are different macro types for any I/O standard or feature that determine the required VCCI and VREF voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and 24mA-drive strength. LVTTL can support high slew rate but this should only be used for critical signals. 14 1.81 30 3.29 15 1.93 31 3.41 QF Most of the macro symbols represent variations of the six generic symbol types: Note: Delay values are approximate and will vary with process, temperature, and voltage. Using the Differential I/O Standards Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot be changed inside Designer. Please note that there are no tristated or bidirectional I/O buffers for differential standards. * CLKBUF: Clock Buffer * HCLKBUF: Hardwired Clock Buffer * INBUF: Input Buffer * OUTBUF: Output Buffer * TRIBUF: Tristate Buffer * BIBUF: Bidirectional Buffer Other macros include the following: * Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential 5. These values are minimum drive strengths. v2.3 2-15 Axcelerator Family FPGAs inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL). * Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUF macros. These are available only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. Whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. This allows users to leave inputs unconnected without having the negative effect on simulation of propagating unknowns. * DDR_REG macro. It can be connected to any I/O standard input buffers (i.e. INBUF) to implement a double data rate register. Designer software will map it to the I/O module in the same way it maps the other registers to the I/O module. Table 2-15, Table 2-16 on page 2-17, and Table 2-17 on page 2-17 list all the available macro names differentiated by I/O standard, type, slew rate, and drive strength. Table 2-15 * Macros for Single-Ended I/O Standards Standard VCCI LVTTL 3.3V CLKBUF, HCLKBUF INBUF, OUTBUF, OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24, OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24, TRIBUF, TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24, TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24, BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24, BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24, 3.3V PCI 3.3V CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI, TRIBUF_PCI, BIBUF_PCI 3.3V PCI-X 3.3V CLKBUF_PCI-X, HCLKBUF_PCI-X, INBUF_PCI-X, OUTBUF_PCI-X, TRIBUF_PCI-X, BIBUF_PCI-X LVCMOS25 2.5V CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25, OUTBUF_LVCMOS25, TRIBUF_LVCMOS25, BIBUF_LVCMOS25 LVCMOS18 1.8V CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18, OUTBUF_LVCMOS18, TRIBUF_LVCMOS18, BIBUF_LVCMOS18 LVCMOS15 (JESD8-11) 1.5V CLKBUF_LVCMOS15, HCLKBUF_LVCMOS15, INBUF_LVCMOS15, OUTBUF_LVCMOS15, TRIBUF_LVCMOS15, BIBUF_LVCMOS15 2 -1 6 Macro Names v2.3 Axcelerator Family FPGAs Table 2-16 * I/O Macros for Differential I/O Standards Standard VCCI LVPECL 3.3V CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL, LVDS 2.5V CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS, Macro Names Table 2-17 * I/O Macros for Voltage-Referenced I/O Standards Standard VCCI VREF Macro Names GTL+ 3.3V 1.0V CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUF_GTP33, BIBUF_GTP33 GTL+ 2.5V 1.0V CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUF_GTP25, BIBUF_GTP25 SSTL2 Class I 2.5V 1.25V CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, TRIBUF_SSTL2_I, BIBUF_SSTL2_I INBUF_SSTL2_I, OUTBUF_SSTL2_I, SSTL2 Class II 2.5V 1.25V CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, TRIBUF_SSTL2_II, BIBUF_SSTL2_II INBUF_SSTL2_II, OUTBUF_SSTL2_II, SSTL3 Class I 3.3V 1.5V CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, TRIBUF_SSTL3_I, BIBUF_SSTL3_I INBUF_SSTL3_I, OUTBUF_SSTL3_I, SSTL3 Class II 3.3V 1.5V CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, TRIBUF_SSTL3_II, BIBUF_SSTL3_II INBUF_SSTL3_II, OUTBUF_SSTL3_II, HSTL Class I 1.5V 0.75V CLKBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I, TRIBUF_HSTL_I, BIBUF_HSTL_I v2.3 2-17 Axcelerator Family FPGAs User I/O Naming Conventions Due to the complex and flexible nature of the Axcelerator family's user I/Os, a naming scheme is used to show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for differential I/Os (Figure 2-7). GND V CCDA V PUMP V CCI 1 Corner2 I/O BANK 2 I/O BANK 1 AX125 VCCDA GND I/O BANK 3 Corner4 I/O BANK 5 GND VCCDA VCCI 2 GND VCCA GND GND VCCDA I/O BANK 6 GND V CCDA GND I/O BANK 0 GND VCCI 6 GND VCCA GND VCCA GND V COMPLD V CCPLD V COMPLC V CCPLC VCCDA GND V COMPLB V CCPLB V COMPLA V CCPLA PRB PRA V CCI 0 GND VCCA Corner1 I/O BANK 7 VCCI 7 GND VCCA GND TDO TDI TCK TMS TRST LP GND VCCDA I/O BANK 4 Corner3 VCCI 3 GND VCCA GND GND VCCDA GND V CCDA V CCI 4 GND V CCA GND V COMPLE V CCPLE V COMPLF V CCPLF PRC PRD V COMPLG V CCPLG V COMPLH V CCPLH GND V CCDA V CCI 5 GND V CCA GND VCCDA GND Figure 2-7 * I/O Bank and Dedicated Pin Layout IOxxXBxFx Pair number in the bank, starting at 00, clockwise from IOB NW P - Positive Pin/ N- Negative Pin Bank I/D 0 through 7, clockwise from IOB NW Fx refers to an unimplemented feature and can be ignored. Examples: IO12PB1F1 is the positive pin of the thirteenth pair of the first I/O bank (IOB NE). IO12PB1 combined with IO12NB1 form a differential pair. For those I/Os that can be employed either as a user I/O or as a special function, the following nomenclature is used: IOxxXBxFx/special_function_name IOxxPB1Fx/xCLKx this pin can be configured as a clock input or as a user I/O. Figure 2-8 * General Naming Schemes 2 -1 8 v2.3 Axcelerator Family FPGAs I/O Standard Electrical Specifications Table 2-18 * Input Capacitance Symbol Parameter Conditions Min. Max. Units CIN Input Capacitance VIN=0, f=1.0 MHz 10 pF CINCLK Input Capacitance on Clock Pin VIN=0, f=1.0 MHz 10 pF IN PAD Y INBUF Input High Vtrip Vtrip ln 0V VCCA 50% 50% Y GND t DP t DP (Rising) (Falling) Figure 2-9 * Input Buffer Delays OUT Pad TRIBUF ln To AC test loads (shown below) En VCCA 50% VCCA 50% 50% ln GND En Vtrip Out VOH Out VOL VCCA 50% 50% VCCI/VTT Vtrip GND VTT Vtrip VOH 10% tPY tPY (tDLH) (tDHL) VOL tENLZ 50% En GND tENLZ Out GND/VTT tENHZ Vtrip 90% tENHZ VTT Figure 2-10 * Output Buffer Delays v2.3 2-19 Axcelerator Family FPGAs I/O Module Timing Characteristics Out Q D OutReg OE D Q IN EnReg D D Q Q InReg CLK CLK (Routed or Hardwired) Figure 2-11 * Timing Model D tSUD tHD CLK tCPWHL tICLKQ tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tHASYN tPRESET tWASYN PRESET tSUE tHE E Figure 2-12 * Input Register Timing Characteristics 2 -2 0 v2.3 tREASYN Axcelerator Family FPGAs D tSUD tHD CLK tCPWHL tOCLKQ tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tPRESET tHASYN tREASYN tHASYN tREASYN tWASYN PRESET tSUE tHE E Figure 2-13 * Output Register Timing Characteristics D tSUD tHD CLK tCPWHL tOCLKQ tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tPRESET tWASYN PRESET tSUE tHE E Figure 2-14 * Output Enable Register Timing Characteristics v2.3 2-21 Axcelerator Family FPGAs 3.3V LVTTL Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-19 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 0.8 2.0 3.6 0.4 2.4 24 -24 AC Loadings R=1k Test Point for tpd Test Point for tristate 35 pF R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-15 * AC Test Loads Table 2-20 * AC Waveforms, Measuring Points, and Capacitive Load Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 3.0 1.40 N/A 35 * Measuring Point = Vtrip Timing Characteristics Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units LVTTL Output Drive Strength = 1 (8mA) / Low Slew Rate tDP Input Buffer 1.50 1.72 1.96 2.31 ns tPY Output Buffer 12.45 14.32 16.31 19.19 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -2 2 v2.3 Axcelerator Family FPGAs Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units LVTTL Output Drive Strength = 2 (12mA) / Low Slew Rate tDP Input Buffer 1.50 1.72 1.96 2.31 ns tPY Output Buffer 10.59 12.18 13.87 16.31 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 1.50 1.72 1.96 2.31 ns LVTTL Output Drive Strength =3 (16mA) / Low Slew Rate tDP Input Buffer tPY Output Buffer 9.62 11.07 12.61 14.83 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 2-23 Axcelerator Family FPGAs Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units LVTTL Output Drive Strength = 4 (24mA) / Low Slew Rate tDP Input Buffer 1.50 1.72 1.96 2.31 ns tPY Output Buffer 9.12 10.49 11.95 14.05 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 1.50 1.72 1.96 2.31 ns LVTTL Output Drive Strength = 1 (8mA) / High Slew Rate tDP Input Buffer tPY Output Buffer 3.71 4.26 4.86 5.72 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -2 4 v2.3 Axcelerator Family FPGAs Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units LVTTL Output Drive Strength = 2 (12mA) / High Slew Rate tDP Input Buffer 1.50 1.72 1.96 2.31 ns tPY Output Buffer 2.90 3.34 3.80 4.47 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 1.50 1.72 1.96 2.31 ns LVTTL Output Drive Strength =3 (16mA) / High Slew Rate tDP Input Buffer tPY Output Buffer 2.75 3.16 3.60 4.24 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 2-25 Axcelerator Family FPGAs Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units LVTTL Output Drive Strength = 4 (24mA) / High Slew Rate tDP Input Buffer 1.50 1.72 1.96 2.31 ns tPY Output Buffer 2.63 3.03 3.45 4.06 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -2 6 v2.3 Axcelerator Family FPGAs 2.5V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer. Table 2-22 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 0.7 1.7 3.6 0.4 2.0 12 -12 AC Loadings R=1k Test Point for tpd Test Point for tristate 35 pF R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-16 * AC Test Loads Table 2-23 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 2.5 1.25 N/A 35 * Measuring Point = Vtrip Timing Characteristics Table 2-24 * 2.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units 2.26 2.66 ns LVCMOS25 I/O Module Timing tDP Input Buffer 1.73 1.99 tPY Output Buffer 2.82 3.24 3.69 4.34 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time tHASYN tCLR tPRESET 0.10 0.10 0.10 0.10 ns Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 2-27 Axcelerator Family FPGAs 1.8V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer. Table 2-25 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 0.2VCCI 0.7VCCI 3.6 0.2 VCCI-0.2 8mA -8mA AC Loadings R to VCCI for tplz/tpzl R to GND for tphz/tpzh R=1k Test Point for tpd Test Point for tristate 35 pF 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-17 * AC Test Loads Table 2-26 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 1.8 0.5VCCI N/A 35 * Measuring Point = Vtrip Timing Characteristics Table 2-27 * 1.8V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.7V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units LVCMOS18 Output Module Timing tDP Input Buffer 2.87 3.30 3.76 4.42 ns tPY Output Buffer 3.94 4.54 5.17 6.08 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -2 8 v2.3 0.43 0.48 0.57 ns Axcelerator Family FPGAs 1.5V LVCMOS (JESD8-11) Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer. Table 2-28 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.5 0.35VCCI 0.65VCCI 3.6 0.4 VCCI-0.4 8mA -8mA AC Loadings R=1k Test Point for tpd Test Point for tristate 35 pF R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Table 2-29 * AC Test Loads Table 2-30 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 1.5 0.5VCCI N/A 35 * Measuring Point = Vtrip Timing Characteristics Table 2-31 * 1.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.4V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed Min. Max. Min. Max. Min. Max. 'Std' Speed Min. Max. Units LVCMOS15 (JESD8-11) I/O Module Timing tDP Input Buffer 3.16 3.63 4.14 4.87 ns tPY Output Buffer 5.23 6.02 6.86 8.07 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/ O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 2-29 Axcelerator Family FPGAs 3.3V PCI, 3.3V PCI-X Peripheral Component Interface for 3.3V standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5V tolerant with the aid of external components. Axcelerator 3.3V PCI and 3.3V PCI-X buffers are compliant with the PCI Local Bus Specification Rev. 2.1. The PCI Compliance Specification requires the clamp diodes to be able to withstand for 11 ns, -3.5V in undershoot, and 7.1V in overshoot. Table 2-32 * DC Input and Output Levels VIH VIL VOL VOH IOL IOH Max,V Min,V mA mA Min,V Max,V Min,V Max,V PCI -0.5 0.3VCCI 0.5VCCI VCCI+0.5 (per PCI specification) PCI-X -0.5 0.35VCCI 0.5VCCI VCCI+0.5 (per PCI specification) AC Loadings R=1k Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh R to V CCI for tpl R to GND for tph R=25 Test point for data 10pF 35 pF for tpzl/tpzh 5 pF for tphz/tplz GND Figure 2-18 * AC Test Loads Table 2-33 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) (Per PCI Spec and PCI-X Spec) * Measuring Point = Vtrip 2 -3 0 v2.3 VREF (typ) (V) Cload (pF) N/A 10 Axcelerator Family FPGAs Timing Characteristics Table 2-34 * 3.3V PCI I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units 3.3V PCI Output Module Timing tDP Input Buffer 1.40 1.61 1.83 2.16 ns tPY Output Buffer 1.70 1.95 2.22 2.62 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 2.87 tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.90 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.31 ns tHD Data Input Hold 0.00 0.00 0.00 0.35 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.00 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 tHASYN Asynchronous Removal Time 0.00 0.00 0.00 tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 '-1' Speed 'Std' Speed 0.57 ns 0.00 ns ns Table 2-35 * 3.3V PCI-X I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description '-2' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units 3.3V PCI-X Output Module Timing tDP Input Buffer 1.40 1.61 1.83 2.16 ns tPY Output Buffer 1.86 2.14 2.44 2.87 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 v2.3 0.43 0.48 0.57 ns ns 2-31 Axcelerator Family FPGAs Voltage-Referenced I/O Standards GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer and an Open Drain output buffer. The VCCI pin should be connected to 2.5V or 3.3V. Note that 2.5V GTL+ is not supported across the full military temperature range. Table 2-36 * DC Input and Output Levels VIH VIL VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA N/A VREF-0.1 VREF+0.1 N/A 0.6 NA NA NA AC Loadings VTT 25 Test Point 10 pF Figure 2-19 * AC Test Loads Table 2-37 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.2 * Measuring Point = Vtrip VREF+0.2 VREF 1.0 10 Timing Characteristics Table 2-38 * 2.5V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units 2.5V GTL+ I/O Module Timing tDP Input Buffer tPY tICLKQ 1.52 1.75 1.99 2.35 ns Output Buffer 0.88 1.01 1.15 1.36 ns Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -3 2 v2.3 Axcelerator Family FPGAs Table 2-39 * 3.3V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units 3.3V GTL+I/O Module Timing tDP Input Buffer 1.52 1.75 1.99 2.35 ns tPY Output Buffer 0.88 1.01 1.15 1.36 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 2-33 Axcelerator Family FPGAs HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5V bus standard (EIA/JESD8-6). The Axcelerator devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer. Table 2-40 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 VREF-0.1 VREF+0.1 3.6 0.4 VCC-0.4 8 -8 AC Loadings VTT 50 Test Point 20 pF Figure 2-20 * AC Test Loads Table 2-41 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.5 VREF+0.5 VREF 0.75 20 * Measuring Point = Vtrip Timing Characteristics Table 2-42 * 1.5V HSTL Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.425V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units 1.5V HSTL Class I I/O Module Timing tDP Input Buffer tPY Output Buffer 4.29 4.93 5.62 6.61 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -3 4 1.60 1.84 0.00 v2.3 2.10 0.00 0.43 2.47 0.00 0.48 0.00 0.57 ns ns ns Axcelerator Family FPGAs SSTL2 Stub Series Terminated Logic for 2.5V is a general-purpose 2.5V memory bus standard (JESD8-9). The Axcelerator devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-43 * DC Input and Output Levels VOL VOH IOL IOH Min,V Max,V Min,V VIH Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.57 VREF+0.57 7.6 -7.6 VIL AC Loadings VTT 50 Test Point 25 30 pF Figure 2-21 * AC Test Loads Table 2-44 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.75 * Measuring Point = Vtrip VREF+0.75 VREF 1.25 30 Timing Characteristics Table 2-45 * 2.5V SSTL2 Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units 2.5V SSTL2 Class I I/O Module Timing tDP Input Buffer 1.62 1.86 2.12 2.50 ns tPY Output Buffer 2.11 2.43 2.76 3.25 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 ns 2-35 Axcelerator Family FPGAs Class II Table 2-46 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.8 VREF+0.8 15.2 -15.2 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-22 * AC Test Loads Table 2-47 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.75 VREF+0.75 VREF 1.25 30 * Measuring Point = Vtrip Timing Characteristics Table 2-48 * 2.5V SSTL2 Class II I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units 2.5V SSTL2 Class II I/O Module Timing tDP Input Buffer 1.68 1.93 2.20 2.59 ns tPY Output Buffer 2.11 2.43 2.76 3.25 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -3 6 0.37 v2.3 0.43 0.48 0.57 ns Axcelerator Family FPGAs SSTL3 Stub Series Terminated Logic for 3.3V is a general-purpose 3.3V memory bus standard (JESD8-8). The Axcelerator devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-49 * DC Input and Output Levels VOL VOH IOL IOH Min,V Max,V Min,V VIH Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.6 VREF+0.6 8 -8 VIL AC Loadings VTT 50 Test Point 25 30 pF Figure 2-23 * AC Test Loads Table 2-50 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-1.0 *Measuring Point = Vtrip VREF+1.0 VREF 1.50 30 Timing Characteristics Table 2-51 * 3.3V SSTL3 Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units 3.3V SSTL3 Class I I/O Module Timing tDP Input Buffer 1.58 1.82 2.07 2.44 ns tPY Output Buffer 1.92 2.21 2.52 2.96 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 tREASYN Asynchronous Recovery Time tHASYN tCLR tPRESET 0.00 0.00 0.43 0.00 0.48 0.57 ns 0.10 0.10 0.10 0.10 ns Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns v2.3 2-37 Axcelerator Family FPGAs Class II Table 2-52 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.8 VREF+0.8 16 -16 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-24 * AC Test Loads Table 2-53 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-1.0 VREF+1.0 VREF 1.50 30 * Measuring Point = Vtrip Timing Characteristics Table 2-54 * 3.3V SSTL3 Class II I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units 3.3V SSTL3 Class II I/O Module Timing tDP Input Buffer 1.64 1.88 2.14 2.53 ns tPY Output Buffer 1.92 2.21 2.52 2.96 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 tCPWLH Clock Pulse Width Low to High 0.39 tWASYN Asynchronous Pulse Width 0.37 tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -3 8 0.00 v2.3 0.00 0.43 0.00 0.48 0.57 ns 0.45 0.51 0.60 ns 0.43 0.48 0.57 ns Axcelerator Family FPGAs Differential Standards Physical Implementation (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards. Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting in a single internal signal. To facilitate construction of the differential pair, a single I/O Cluster contains the resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Actel's Designer software when the user instantiates a differential I/O macro in the design. LVDS Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register OUTBUF_LVDS FPGA P 165 ZO=50 165 ZO=50 FPGA + - 100 140 N P INBUF_LVDS N Figure 2-25 * LVDS Board-Level Implementation The LVDS circuit consists of a differential driver connected to a terminated receiver through a constantimpedance transmission line. The receiver is a widecommon-mode-range differential amplifier. The common-mode range is from 0.2V to 2.2V for a differential input with 400 mV swing. current of 3.5 mA. When this current flows through a 100 termination resistor on the receiver side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is controlled by the data fed to the driver. An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV. Therefore, four external resistors are required, three for the driver and one for the receiver. To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the differential signals (note that the driver is not a currentmode driver). This driver provides a nominal constant Table 2-55 * DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units VCCI1 Supply Voltage 2.375 2.5 2.625 V VOH Output High Voltage 1.25 1.425 1.6 V VOL Output Low Voltage 0.9 1.075 1.25 V VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM2 Input Common Mode Voltage 0.2 1.25 2.2 V 1. +/- 5% 2. Differential input voltage =+/-350mV. v2.3 2-39 Axcelerator Family FPGAs Table 2-56 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.2-0.125 1.2+0.125 1.2 * Measuring Point = Vtrip Timing Characteristics Table 2-57 * LVDS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units LVDS Output Module Timing tDP Input Buffer 1.60 1.84 2.10 2.47 ns tPY Output Buffer 2.05 2.36 2.69 3.16 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/ O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -4 0 v2.3 Axcelerator Family FPGAs LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The voltage swing between these two signal lines is approximately 850 mV. FPGA P OUTBUF_LVPECL 100 FPGA P ZO=50 + INBUF_LVPECL 100 187 - ZO=50 100 N N Figure 2-26 * LVPECL Board-Level Implementation The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are different. Please note that the VOH levels are 200 mV below the standard LVPECL levels. Table 2-58 * DC Input and Output Levels Min. DC Parameter Min. VCCI Typ. Max. Min. 3 Max. Max. Min. 3.3 Max. Units 3.6 V VOH 1.8 2.11 1.92 2.28 2.13 2.41 V VOL 0.96 1.27 1.06 1.43 1.3 1.57 V VIH 1.49 2.72 1.49 2.72 1.49 2.72 V VIL 0.86 2.125 0.86 2.125 0.86 2.125 V Differential Input Voltage 0.3 0.3 0.3 V Table 2-59 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.6-0.3 1.6+0.3 1.6 * Measuring Point = Vtrip v2.3 2-41 Axcelerator Family FPGAs Timing Characteristics Table 2-60 * LVPECL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units LVPECL Output Module Timing tDP Input Buffer 1.47 1.70 1.93 2.28 ns tPY Output Buffer 1.98 2.28 2.60 3.06 ns tICLKQ Clock-to-Q for the I/O input register 0.59 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.59 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.37 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.39 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.37 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns 2 -4 2 v2.3 Axcelerator Family FPGAs Module Specifications C-Cell Introduction The C-cell is one of the two logic module types in the AX architecture. It is the combinatorial logic resource in the Axcelerator device. The AX architecture implements a new combinatorial cell that is an extension of the C-cell implemented in the SX-A family. The main enhancement of the new C-cell is the addition of carry-chain logic. The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not required, it can be disabled. * A carry input and a carry output. The carry input signal of the C-cell is the carry output from the Ccell directly to the north. * Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns. * A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the east side of a SuperCluster with a signal propagation time of less than 0.1 ns. This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a single cell delay. The C-cell features the following (Figure 2-27): * * Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed clocks (CLKE/F/G/H). The carry-chain configuration is handled automatically for the user with Actel's extensive macro library (please see Actel's Antifuse Macro Library Guide for a complete listing of available Axcelerator macros) Inverter (DB input) can be used to drive a complement signal of any of the inputs to the Ccell. . CFN FCI D1 D3 B0 B1 0 1 0 1 0 1 0 1 0 1 D0 D2 DB A0 A1 FCO Y Figure 2-27 * C-Cell v2.3 2-43 Axcelerator Family FPGAs Timing Model and Waveforms VCCA 50% 50% A, B, D, FCI GND VCCA 50% Y, FCO GND 50% tPD, tPDC tPD, tPDC VCCA Y, FCO 50% GND tPD, tPDC 50% tPD, tPDC Figure 2-28 * C-Cell Timing Model and Waveforms Timing Characteristics Table 2-61 * C-Cell Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units C-Cell Propagation Delays tPD Any input to output Y 0.64 0.74 0.84 0.99 ns tPDC Any input to carry chain output (FCO) 0.49 0.57 0.64 0.76 ns tPDB Any input through DB when one input is used 0.83 0.95 1.09 1.28 ns tCCY Input to carry chain (FCI) to Y 0.53 0.61 0.69 0.82 ns tCC Input to carry chain (FCI) to carry chain output (FCO) 0.07 0.08 0.09 0.11 ns 2 -4 4 v2.3 Axcelerator Family FPGAs Carry-Chain Logic The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-4 on page 1-3 and Figure 2-30 on page 2-46). To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e. carry out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay from the FCI (i.e. carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-29. The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is deasserted to save power. Again, this configuration is handled automatically for the user through Actel's macro library. The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns. CFN D1 D3 B0 B1 FCI D1 D3 B0 B1 CFN The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO of one 0 1 0 1 DCOUT 0 1 0 1 0 1 0 1 0 1 0 1 A1 A0 DB D0 D2 Y 0 1 FCO Y 0 1 A1 A0 DB D0 D2 0 1 Figure 2-29 * Axcelerator's Two-Bit Carry Logic v2.3 2-45 Axcelerator Family FPGAs FCI1 C-cell1 FCI3 C-cell2 DCOUT R-cell1 DCIN FCO2 DCOUT DCIN FCO4 FCI5 n-2 Clusters FCI(2n-1) C-cell (2n-1) C-cell2n DCOUT R-celln CDIN FCO2n Note: The carry-chain sequence can end on either C-cell. Figure 2-30 * Carry-Chain Sequencing of C-cells Timing Characteristics Refer to the Table 2-61 on page 2-44 for more information on carry-chain timing. 2 -4 6 v2.3 Axcelerator Family FPGAs R-Cell Introduction * The R-cell, the sequential logic resource of the Axcelerator devices, is the second logic module type in the AX family architecture. It includes clock inputs for all eight global resources of the Axcelerator architecture as well as global presets and clears (Figure 2-31). The main features of the R-cell include the following: * * * * Direct connection to the adjacent logic module through the hardwired connection DCIN. DCIN is driven by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a connection with less than 0.1 ns of routing delay. Provision of data enable-input (S0). Independent active-low asynchronous preset (PSET). If both CLR and PSET are low, CLR has higher priority. One of the four high performance hardwired fast clocks (HCLKs) - One of the four routed clocks (CLKs) - User signals Global power-on clear (GCLR) and preset (GPSET), which drive each flip-flop on a chip-wide basis. When the Global Set Fuse option in the Designer software is unchecked (by default), GCLR = 0 and GPSET =1 at device power-up. When the option is checked, GCLR = 1 and GPSET= 0. Both pins are pulled High when the device is in user mode. * S0, S1, PSET, and CLR can be driven by routed clocks CLKE/F/G/H or user signals. * DIN and S1 can be driven by user signals. As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for the user through Actel's extensive macro library (please see Actel's Macro Library Guide for a complete listing of available AX macros). CKP Independent active-low asynchronous clear (CLR). * - - The R-cell can be used as a standalone flip-flop. It can be driven by any C-cell or I/O modules through the regular routing structure (using DIN as a routable data input). This gives the option of using the R-Cell as a 2:1 MUXed flip-flop as well. * Clock can be driven by any of the following (CKP selects clock polarity): DIN(user signals) DCIN HCLKA/B/C/D CLKE/F/G/H Y PSET GPSET S0 S1 CKS CLR GCLR Internal Logic Figure 2-31 * R-Cell v2.3 2-47 Axcelerator Family FPGAs Timing Models and Waveforms D tSUD tHD CLK tCPWHL tRCO tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tHASYN tPRESET tREASYN tWASYN PRESET tSUE tHE E Figure 2-32 * R-Cell Delays Timing Characteristics Table 2-62 * R-Cell Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units R-Cell Propagation Delays tRCO Sequential Clock-to-Q 0.59 0.67 0.77 0.90 ns tCLR Asynchronous Clear-to-Q 0.20 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.20 0.23 0.27 0.31 ns tSUD Flip-Flop Data Input Set-Up 0.20 0.23 0.27 0.31 ns tSUE Flip-Flop Enable Input Set-Up 0.23 0.26 0.30 0.35 ns tHD Flip-Flop Data Input Hold 0.00 0.00 0.00 0.00 ns tHE Flip-Flop Enable Input Hold 0.00 0.00 0.00 0.00 ns tWASYN Asynchronous Pulse Width tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.36 0.42 0.47 0.55 ns tCPWLH Clock Pulse Width Low to High 0.35 0.40 0.46 0.54 ns 2 -4 8 0.37 0.43 v2.3 0.48 0.57 ns Axcelerator Family FPGAs Buffer Module Introduction An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to the AX architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets. Timing Models and Waveforms IN OUT Figure 2-33 * Buffer Module Timing Model VCCA 50% 50% GND IN VCCA OUT GND 50% 50% tBFPD tBFPD Figure 2-34 * Buffer Module Waveform Timing Characteristics Table 2-63 * Buffer Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units 0.16 ns Buffer Module Propagation Delays tBFPD Any input to output Y 0.10 v2.3 0.12 0.14 2-49 Axcelerator Family FPGAs Routing Specifications Routing Resources The routing structure found in Axcelerator devices enables any logic module to be connected to any other logic module while retaining high performance. There are multiple paths and routing resources that can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip. There are four primary types of routing within the AX architecture: DirectConnect, CarryConnect, FastConnect, and Vertical and Horizontal Routing. DirectConnect DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-35). This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1 line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less than 0.1 ns. Figure 2-35 * DirectConnect and CarryConnect CarryConnect CarryConnects are used to build carry chains for arithmetic functions (Figure 2-35). The FCO output of the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster immediately below it. This pattern continues down both sides of each SuperCluster column. Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This connection has a delay of less than 0.1 ns from the FCO of one two-C-cell cluster to the FCI of the two-C-cell cluster immediately below it (see the "Carry-Chain Logic" on page 2-45 for more information). FastConnect For high-speed routing of logic signals, FastConnects can be used to build a short distance connection using a single antifuse (Figure 2-36 on page 2-51). FastConnects provide a maximum delay of 0.3 ns. The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on the Output Tracks can 2 -5 0 v2.3 then be routed through a single antifuse connection to drive the inputs of logic modules either within one SuperCluster or in the SuperCluster immediately below it. Vertical and Horizontal Routing Vertical and Horizontal Tracks provide both local and long distance routing (Figure 2-37 on page 2-51). These tracks are composed of both short-distance, segmented routing and across-chip routing tracks (segmented at core tile boundaries). The short-distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. These short-distance routing tracks can be used within and between SuperClusters or between modules of nonadjacent SuperClusters. They can be connected to the Output Tracks and to any logic module input (R-cell, C-cell, Buffer, and TX module). The across-chip horizontal and vertical routing provides long-distance routing resources. These resources interface with the rest of the routing structures through Axcelerator Family FPGAs the RX and TX modules (Figure 2-37). The RX module is used to drive signals from the across-chip horizontal and vertical routing to the Output Tracks within the SuperCluster. The TX module is used to drive vertical and horizontal across-chip routing from either short-distance horizontal tracks or from Output Tracks. The TX module can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa. Figure 2-36 * FastConnect Routing Figure 2-37 * Horizontal and Vertical Tracks v2.3 2-51 Axcelerator Family FPGAs Timing Characteristics Table 2-64 * AX125 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Typical Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.10 0.11 0.12 0.15 ns tFC FastConnect Routing Delay, FO1 0.30 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.30 0.35 0.40 0.47 ns tRD2 Routing delay for FO2 0.33 0.38 0.43 0.51 ns tRD3 Routing delay for FO3 0.37 0.43 0.48 0.57 ns tRD4 Routing delay for FO4 0.42 0.48 0.55 0.64 ns tRD5 Routing delay for FO5 0.48 0.55 0.62 0.73 ns tRD6 Routing delay for FO6 0.55 0.64 0.72 0.85 ns tRD7 Routing delay for FO7 0.68 0.79 0.89 1.05 ns tRD8 Routing delay for FO8 0.76 0.88 0.99 1.17 ns tRD16 Routing delay for FO16 1.29 1.49 1.69 1.99 ns tRD32 Routing delay for FO32 2.01 2.32 2.63 3.10 ns '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Typical Typical Typical Typical Units Table 2-65 * AX250 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C Parameter Description Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.10 0.11 0.12 0.15 ns tFC FastConnect Routing Delay, FO1 0.30 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.34 0.39 0.45 0.53 ns tRD2 Routing delay for FO2 0.35 0.41 0.46 0.54 ns tRD3 Routing delay for FO3 0.42 0.48 0.55 0.64 ns tRD4 Routing delay for FO4 0.48 0.56 0.63 0.75 ns tRD5 Routing delay for FO5 0.52 0.60 0.68 0.80 ns tRD6 Routing delay for FO6 0.73 0.84 0.96 1.13 ns tRD7 Routing delay for FO7 0.78 0.90 1.02 1.20 ns tRD8 Routing delay for FO8 0.86 1.00 1.13 1.33 ns tRD16 Routing delay for FO16 1.88 2.17 2.46 2.89 ns tRD32 Routing delay for FO32 3.08 3.55 4.03 4.74 ns 2 -5 2 v2.3 Axcelerator Family FPGAs Table 2-66 * AX500 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Typical Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.10 0.11 0.12 0.15 ns tFC FastConnect Routing Delay, FO1 0.30 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.34 0.39 0.45 0.53 ns tRD2 Routing delay for FO2 0.35 0.41 0.46 0.54 ns tRD3 Routing delay for FO3 0.42 0.48 0.55 0.64 ns tRD4 Routing delay for FO4 0.48 0.56 0.63 0.75 ns tRD5 Routing delay for FO5 0.52 0.60 0.68 0.80 ns tRD6 Routing delay for FO6 0.73 0.84 0.96 1.13 ns tRD7 Routing delay for FO7 0.78 0.90 1.02 1.20 ns tRD8 Routing delay for FO8 0.86 1.00 1.13 1.33 ns tRD16 Routing delay for FO16 1.88 2.17 2.46 2.89 ns tRD32 Routing delay for FO32 3.08 3.55 4.03 4.74 ns Table 2-67 * AX1000 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Typical Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.10 0.12 0.13 0.15 ns tFC FastConnect Routing Delay, FO1 0.30 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.39 0.45 0.51 0.60 ns tRD2 Routing delay for FO2 0.46 0.53 0.60 0.71 ns tRD3 Routing delay for FO3 0.48 0.56 0.63 0.74 ns tRD4 Routing delay for FO4 0.55 0.63 0.71 0.84 ns tRD5 Routing delay for FO5 0.63 0.73 0.82 0.97 ns tRD6 Routing delay for FO6 0.86 0.99 1.13 1.32 ns tRD7 Routing delay for FO7 0.88 1.02 1.15 1.36 ns tRD8 Routing delay for FO8 1.28 1.48 1.68 1.97 ns tRD16 Routing delay for FO16 2.23 2.57 2.91 3.42 ns tRD32 Routing delay for FO32 3.68 4.24 4.81 5.65 ns v2.3 2-53 Axcelerator Family FPGAs Table 2-68 * AX2000 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Typical Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.10 0.12 0.13 0.15 ns tFC FastConnect Routing Delay, FO1 0.30 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.43 0.50 0.56 0.66 ns tRD2 Routing delay for FO2 0.51 0.59 0.67 0.79 ns tRD3 Routing delay for FO3 0.61 0.70 0.80 0.94 ns tRD4 Routing delay for FO4 0.66 0.76 0.87 1.02 ns tRD5 Routing delay for FO5 0.85 0.98 1.11 1.31 ns tRD6 Routing delay for FO6 1.28 1.48 1.68 1.97 ns tRD7 Routing delay for FO7 1.43 1.65 1.87 2.20 ns tRD8 Routing delay for FO8 1.50 1.73 1.96 2.31 ns tRD16 Routing delay for FO16 2.24 2.58 2.92 3.44 ns tRD32 Routing delay for FO32 3.68 4.24 4.81 5.65 ns 2 -5 4 v2.3 Axcelerator Family FPGAs Global Resources Hardwired Clocks One of the most important aspects of any FPGA architecture is its global resources or clocks. The Axcelerator family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other FPGA architectures. The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential modules (R-cells, I/O registers, and embedded RAM/FIFOs) in the device with no antifuse in the path. All four HCLKs are available everywhere on the chip. The AX architecture contains two types of global resources, the HCLK (hardwired clock) and CLK (routed clock). Every Axcelerator device is provided with four HCLKs and four CLKs for a total of eight clocks, regardless of device density. Timing Characteristics Table 2-69 * AX125 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.63 3.02 3.44 4.05 ns tHCKH Input High to Low 2.64 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.50 tHPWL Minimum Pulse Width Low 0.45 tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.58 0.65 0.52 0.05 1.00 0.59 0.06 1.31 870 ns 0.69 0.07 1.15 1000 0.77 ns 0.08 1.54 763 ns ns 649 MHz Table 2-70 * AX250 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units 3.45 ns Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.24 2.57 tHCKH Input High to Low tHPWH Minimum Pulse Width High 0.50 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 2.27 2.61 0.05 1.00 v2.3 2.97 0.06 1.15 1000 2.93 0.07 1.31 870 3.50 0.08 ns 649 MHz 1.54 763 ns ns 2-55 Axcelerator Family FPGAs Table 2-71 * AX500 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.05 2.35 2.68 3.15 ns tHCKH Input High to Low 2.13 2.44 2.79 3.27 ns tHPWH Minimum Pulse Width High 0.50 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.05 1.00 0.06 1.15 1000 0.07 1.31 870 0.08 1.54 763 ns ns 649 MHz Table 2-72 * AX1000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.63 3.02 3.44 4.05 ns tHCKH Input High to Low 2.64 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.50 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.05 1.00 0.06 1.15 1000 0.07 1.31 870 0.08 1.54 ns ns 763 649 '-1' Speed 'Std' Speed MHz Table 2-73 * AX2000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. Min. Max. Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.63 3.02 3.44 4.05 ns tHCKH Input High to Low 2.64 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.50 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 2 -5 6 0.05 1.00 0.06 1.15 1000 v2.3 0.07 1.31 870 0.08 1.54 763 ns ns 649 MHz Axcelerator Family FPGAs Routed Clocks The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere on the chip. Timing Characteristics Table 2-74 * AX125 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. '-2' Speed Max. Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.67 3.08 3.50 4.12 ns tRCKH Input High to Low 2.72 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.49 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.3 0.35 1.00 1.15 1000 0.39 1.31 870 0.46 1.54 ns ns 763 649 '-1' Speed 'Std' Speed MHz Table 2-75 * AX250 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. '-2' Speed Max. Min. Max. Min. Max. Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.19 2.52 2.87 3.37 ns tRCKH Input High to Low 2.25 2.59 2.95 3.47 ns tRPWH Minimum Pulse Width High 0.49 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.3 0.35 1.00 1.15 1000 1.31 870 v2.3 0.39 0.46 1.54 763 ns ns 649 MHz 2-57 Axcelerator Family FPGAs Table 2-76 * AX500 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.00 2.31 2.63 3.09 ns tRCKH Input High to Low 2.12 2.44 2.78 3.27 ns tRPWH Minimum Pulse Width High 0.49 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.3 1.00 0.35 1.15 1000 0.39 1.31 870 0.46 1.54 ns ns 763 649 '-1' Speed 'Std' Speed MHz Table 2-77 * AX1000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. Min. Max. Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.67 3.08 3.50 4.12 ns tRCKH Input High to Low 2.72 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.49 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.3 1 0.35 0.39 1.15 1000 1.31 870 0.46 1.54 ns ns 763 649 '-1' Speed 'Std' Speed MHz Table 2-78 * AX2000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. Min. Max. Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.67 3.08 3.50 4.12 ns tRCKH Input High to Low 2.72 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.49 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.45 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 2 -5 8 0.3 1 0.35 1.15 1000 v2.3 0.39 1.31 870 0.46 1.54 763 ns ns 649 MHz Axcelerator Family FPGAs Global Resource Distribution At the root of each global resource is a PLL. There are two groups of four PLLs for every device. One group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs (Figure 2-38). PLL P N Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 239). PLL P N PLL P N PLL P N PLL Cluster HCLKA HCLKB CLKE CLKF HCLKC HCLKD CLKG CLKH PLL Cluster P N PLL P N PLL P N PLL P N PLL Figure 2-38 * PLL Group HCLK CLK PLL Group ClockTileDist Cluster 4 4 PLL Group Figure 2-39 * Example of HCLK and CLK Distributions on the AX2000 v2.3 2-59 Axcelerator Family FPGAs The ClockTileDist Cluster contains an HCLKMux (HM) module for each of the four HCLK trees and a CLKMux (CM) module for each of the CLK trees. The HCLK branches then propagate horizontally through the middle of the core tile to HCLKColDist (HD) modules in every SuperCluster column. The CLK branches propagate Figure 2-40 * CTD, CD, and HD Module Layout Figure 2-41 * HCLK and CLK Distribution within a Core Tile 2 -6 0 v2.3 vertically through the center of the core tile to CLKRowDist (RD) modules in every SuperCluster row. Together, the HCLK and CLK branches provide for a lowskew global fanout within the core tile (Figure 2-40 and Figure 2-41). Axcelerator Family FPGAs The HM and CM modules can select between: * The HCLK or CLK source respectively * A local signal routed on generic routing resources Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the Ppad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals. An unused input can be tied to ground for power savings. CLKINT and HCLKINT This allows each core tile to have eight clocks independent of the other core tiles in the device. CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals (Figure 2-43). Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be used independently. * The HCLK or CLK source from the HM or CM module respectively * A local signal routed on generic routing resources Clock Network Logic Like the HM and CM modules, the HD and RD modules can select between: CLKINT HCLKINT Figure 2-43 * CLKINT and HCLKINT Again, an unused input can be tied to ground for power savings. PLLRCLK and PLLHCLK PLLRCLK (PLLHCLK) is used to drive global resource CLK (HCLK) from a PLL (Figure 2-44). The AX architecture is capable of supporting a large number of local clocks - 24 segments per HCLK driving north-south and 28 segments per CLK driving east-west per core tile. Actel's Designer software's place-and-route takes advantage of the segmented clock structure found in Axcelerator devices by turning off any unused clock segments. This results in not only better performance but also lower power consumption. RefCLK Clock Network CLK1 PLL FB CLK2 PLLRCLK PLLHCLK Figure 2-44 * PLLRCLK and PLLHCLK Global Resource Access Macros Global resources can be driven by one of three sources: external pad(s), an internal net, or the output of a PLL. These connections can be made by using one of three types of macros: CLKBUF, CLKINT, and PLLCLK. Using Global Resources with PLLs Each global resource has an associated PLL at its root. For example, PLLA can drive HCLKA, PLLE can drive CLKE, etc. (Figure 2-45 on page 2-62). CLKBUF and HCLKBUF In addition, each clock pin of the package can be used to drive either its associated global resource or PLL. For example, package pins CLKEP and CLKEN can drive either the RefCLK input of PLLE or CLKE. CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-42). There are two macros required when interfacing the embedded PLLs with the global resources: PLLINT and PLLOUT. PLLINT P This macro is used to drive the RefCLK input of the PLL internally from user signals. Clock Network PLLOUT N CLKBUF HCLKBUF This macro is used to connect either the CLK1 or CLK2 output of a PLL to the regular routing network (Figure 246 on page 2-62). Figure 2-42 * CLKBUF and HCLKBUF Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are associated with HCLKA, etc. v2.3 2-61 Axcelerator Family FPGAs Implementation Example: Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2 output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both CLKF and CLKG global resources. HCLKAP RefCLK HCLKA Network CLK1 PLLA FB HCLKAN CLK2 PLLHCLK Figure 2-45 * Example of HCLKA driven from a PLL with External Clock Source PLLHCLK PLLINT RefCLK Logic HCLKA Network CLK1 PLLA FB CLK2 Logic PLLOUT Figure 2-46 * Example of PLLINT and PLLOUT Usage Non-Clock Pins INBUF PLLINT P PLLRCLK N RefCLK CLK1 PLLE FB CLK2 CLKINT PLLOUT Logic PLLRCLK RefCLK CLK1 CLKF CLK2 CLKG PLLF FB PLLRCLK Figure 2-47 * Complex Clock Distribution Example 2 -6 2 v2.3 CLKE Axcelerator Family FPGAs Axcelerator Clock Management System Introduction southern edge. The northern group is associated with the four HCLK networks (e.g. PLLA can drive HCLKA), while the southern group is associated with the four CLK networks (e.g. PLLE can drive CLKE). Each member of the Axcelerator family contains eight phase-locked loop (PLL) blocks which perform the following functions: * Programmable Delay (32 steps of 250 ps) * Clock Skew Minimization * Clock Frequency Synthesis Each PLL cell is connected to two I/O pads and a PLL Cluster that interfaces with the FPGA core. Figure 2-48 illustrates a PLL block. The VCCPLL pin should be connected to a 1.5V power supply through a 250 resistor. Furthermore, 0.1 F and 10 F decoupling capacitors should be connected across the VCCPLL and VCOMPPLL pins. Note: The VCOMPPLL pin should never be grounded (Figure 2-2 on page 2-9)! Each PLL has the following key features: * Input Frequency Range - 14 to 200 MHz * Output Frequency Range - 20 MHz to 1 GHz * Output Duty Cycle Range - 45% to 55% * Maximum Long-Term (whichever is greater) * Maximum Short-Term Jitter - 50ps + 1% of Output Frequency * Maximum Acquisition Time (lock) - 20s Jitter - 1% or The I/O pads associated with the PLL can also be configured for regular I/O functions except when it is used as a clock buffer. The I/O pads can be configured in all the modes available to the regular I/O pads in the same I/O bank. In particular, the [H]CLKxP pad can be configured as a differential pair, single-ended, or voltage-referenced standard. The [H]CLKxN pad can only be used as a differential pair with [H]CLKxP. 100ps Physical Implementation The block marked "/i Delay Match" is a fixed delay equal to that of the i divider. The "/j Delay Match" block has the same function as its j divider counterpart. The eight PLL blocks are arranged in two groups of four. One group is located in the center of the northern edge of the chip, while the second group is centered on the DIVJ 6 PowerDown RefCLK Delay Line /i Delay Match PLL FB Delay Line FBMuxSel 5 DelayLine Lock /j CLK1 /j Delay Match CLK2 /i 6 DIVJ LowFreq 3 Osc Figure 2-48 * PLL Block Diagram v2.3 2-63 Axcelerator Family FPGAs Functional Description * Figure 2-48 on page 2-63 illustrates a block diagram of the PLL. The PLL contains two dividers, i and j, that allow frequency scaling of the clock signal: * The i divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64, and the resultant frequency is available at the output of the PLL block. * The j divider divides the PLL output by integer factors ranging from 1 to 64, and the divided clock is available at CLK1. * The two dividers together can implement any combination of multiplication and division up to a maximum frequency of 1 GHz on CLK1. Both the CLK1 and CLK2 outputs have a fixed 50/50 duty cycle. * The output frequencies of the two clocks are given by the following formulas (fREF is the reference clock frequency): fCLK1 = fREF * (DividerI) / (DividerJ) EQ 2-4 fCLK2 = fREF * (DividerI) EQ 2-5 CLK2 provides the PLL output directly--without division The input and output frequency ranges are selected by LowFreq and Osc(2:0), respectively. These functions and their possible values are detailed in Table 2-79. The delay lines shown in Figure 2-48 on page 2-63 are programmable. The feedback clock path can be delayed (using the five DelayLine bits) relative to the reference clock (or vice versa) by up to 3.75 ns in increments of 250 ps. Table 2-79 describes the usage of these bits. The delay increments are independent of frequency, so this results in phase changes that vary with frequency. The delay value is highly dependent on VCC and the speed grade. Figure 2-49 on page 2-65 is a logical diagram of the various control signals to the PLL and shows how the PLL interfaces with the global and routing networks of the FPGA. Note that not all signals are user-accessible. These non-user-accessible signals are used by Actel's place-androute tool to control the configuration of the PLL. The user gains access to these control signals either based upon the connections built in the user's design or through the special macros (Table 2-83 on page 2-67) inserted into the design. For example, connecting the macro PLLOUT to CLK2 will control the OUTSEL signal. Table 2-79 * PLL Interface Signals Signal Name Type User Accessible RefCLK Input Yes Reference Clock for the PLL FB Input Yes Feedback port for the PLL PowerDown Input Yes PLL power down control DIVI[5:0] Input Yes DIVJ[5:0] Input Yes LowFreq Input Yes Allowable Values 0 PLL powered down 1 PLL active 1 to 64, in unsigned binary notation offset by -1 DelayLine[4:0] Input 14-50 MHz Yes Yes Sets value for CLK1 divider 50-200 MHz 1 Input Sets value for feedback divider (multiplier) Input frequency range selector 0 Osc[2:0] Function Output frequency range selector XX0 400-1000 MHZ 001 200-400 MHZ 011 100-200 MHZ 101 50-100 MHZ 111 20-50 MHZ Clock Delay (positive/negative) in increments of 250 ps, with -15 to +15 (increments), in signed- maximum value of 3.75 ns and-magnitude binary representation FBMuxSel Input No Selects the source for the feedback input REFSEL Input No Selects the source for the reference clock OUTSEL Input No Selects the source for the routed net output 2 -6 4 v2.3 Axcelerator Family FPGAs Table 2-79 * PLL Interface Signals (Continued) Signal Name Type User Accessible PLLSEL Input No Allowable Values Function ROOTSEL Input No Lock Output Yes High value indicates PLL has locked CLK1 Output Yes PLL clock output CLK2 Output Yes PLL clock output ROOTSEL & PLLSEL are used to select the source of the global clock network Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are indeterminate. ROOTSEL REFSEL CLKINT CLK1 (PLLn-1) CLK1 (PLLn-1) RefCLK [H]CLKINT 0 1 2 3 CLK1 [H]CLKxP PLL I/O Core net CLK net [H]CLK PLLSEL CLK2 0 FBINT CLK Out (Routed net out pin) 1 FB [H]CLKxN OUTSEL FBMuxSEL To PLLn+1 Note: Not all signals are available to the user. Figure 2-49 * PLL Logical Interface PLL Configurations Regular, LVPECL, or LVDS IOPAD The following rules apply to the different PLL inputs and outputs: Non-clock Pins Reference Clock The RefCLK can be driven by (Figure 2-50): P 1. Global routed clocks (CLKE/F/G/H) or user-created clock network N INBUF RefCLK PLL 2. CLK1 output of an adjacent PLL Any macro from the core, except HCLK nets 3. [H]CLKxP (single-ended or voltage-referenced) 4. [H]CLKxP/[H]CLKxN pair LVPECL or LVDS) (differential modes like RefCLK Logic Feedback Clock The feedback clock can be driven by (Figure 2-51 on page 2-66): PLL For cascading 1. Global routed clocks (CLKE/F/G/H) or user-created clock network PLL CLK1 RefCLK PLL 2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL cell Figure 2-50 * Reference Clock Connections 3. An internal signal from the PLL block v2.3 2-65 Axcelerator Family FPGAs Table 2-81 * North PLL Connections PLLOUT/PLLRCLK CLK1 HCLK1 FB PLL Any macro except HCLK macros FB PLL Figure 2-51 * Feedback Clock Connections CLK2 Routed net HCLK1 Unused HCLK2 HCLK1 HCLK2 Routed net HCLK2 Both HCLK1 and routed net HCLK2 Unused Unused HCLK1 Unused Routed net Unused Both HCLK1 and routed net Unused Unused CLK1 and CLK2 Routed net HCLK1 Both PLL outputs, CLK1 and CLK2, can be used to drive a global resource, an adjacent PLL RefCLK input, or a net in the FPGA core. Not all drive combinations are possible (Table 2-80). Routed net Unused Both HCLK1 and HCLK2 Routed net Both HCLK1 and HCLK2 Unused Both HCLK1 and routed net Unusable Table 2-80 * PLL General Connections Rules Both HCLK2 and routed net HCLK1 Both HCLK2 and routed net Unused CLK1 CLK2 HCLK HCLK HCLK1, HCLK2, and routed net Unusable CLK CLK HCLK Routed net output Routed net output HCLK Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g.CLK1 driving HCLK1, and HCLK2 is not supported). HCLK NONE NONE HCLK CLK NONE Table 2-82 * South PLL Connections CLK1 Routed net NONE CLK1 Unused CLK CLK2 CLK1 CLK2 Routed net CLK2 Both CLK1 and routed net CLK2 Unused Unused CLK1 Unused Routed net Unused Both CLK1 and routed net Unused Unused Routed net CLK1 Routed net Unused Both CLK1 and CLK2 Routed net Both CLK1 and CLK2 Unused Both CLK1 and routed net Unusable Both CLK2 and routed net CLK1 Both CLK2 and routed net Unused CLK1, CLK2, and routed net Unusable Note: The PLL outputs remain Low when REFCLK is constant (either Low or High). Restrictions on CLK1 and CLK2 * * When both are driving global resources, they must be driving the same type of global resource (i.e. either HCLK or CLK). Only one can drive a routed net at any given time. Table 2-81 and Table 2-82 specify all the possible CLK1 and CLK2 connections for the north and south PLLs. HCLK1 and HCLK2 are used to denote the different HCLK networks when two are being driven at the same time by a single PLL (Note that HCLK1 is the primary clock resource associated with the PLL, and HCLK2 is the clock resource associated with the adjacent PLL). Likewise, CLK1 and CLK2 are used to denote the different CLK networks when two are being driven at the same time by a single PLL (Figure 2-48 on page 2-63). 2 -6 6 CLK2 CLK1 v2.3 Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g., CLK1 driving both CLK1 and CLK2 is not supported). Axcelerator Family FPGAs Special PLL Macros Table 2-83 shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing resources. Table 2-83 * PLL Special Macros Macro Name Usage PLLINT Connects RefCLK to a regular routed net or a pad. PLLRCLK Connects CLK1 or CLK2 to the CLK network. PLLHCLK Connects CLK1 or CLK2 to the HCLK network. PLLOUT Connects CLK1 or CLK2 to a regular routed net. Table 2-84 * Electrical Specifications Parameter Value Notes Frequency Ranges Reference Frequency (min.) 14 MHz Lowest input frequency Reference Frequency (max.) 200 MHz Highest input frequency OSC Frequency (min.) 20 MHz Lowest output frequency OSC Frequency (max.) 1 GHz Highest output frequency Jitter Long-Term Jitter (max.) 1% Percentage of period, low reference clock frequencies Long-Term Jitter (max.) 100ps High reference clock frequencies Short-Term Jitter (max.) 50ps+1% Percentage of output frequency Acquisition Time (lock) from Cold Start Acquisition Time (max.)* 400 cycles Acquisition Time (max.)* 1.5 s Period of low reference clock frequencies High reference clock frequencies Power Consumption Analog Supply Current (low freq.) 200A Current at minimum oscillator frequency Analog Supply Current (high freq.) 200A Frequency-dependent current Digital Supply Current (low freq.) 0.5A/MHz Digital Supply Current (high freq.) 1A/MHz Current at maximum oscillator frequency, unloaded Frequency-dependent current Duty Cycle Minimum Output Duty Cycle 45% Maximum Output Duty Cycle 55% Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency. v2.3 2-67 Axcelerator Family FPGAs User Flow There are two methods of including a PLL in a design: * * The recommended method of using a PLL is to create custom PLL blocks using Actel's macro generator, ACTgen, that can be instantiated in a design. The alternative method is to instantiate one of the generic library primitives (PLL or PLLFB) into either a schematic or HDL netlist, using inverters for polarity control and tying all unused address and data bits to ground. Timing Model Lock CLK1 tPCLK* CLK FB CLK2 Note: tPCLK is the delay in the clock signal Figure 2-52 * PLL Model 2 -6 8 v2.3 3 OSC 5 Delay Line FBMux 6 DividerI/DividerJ Configuration Pins 6 Axcelerator Family FPGAs Sample Implementations Frequency Synthesis Figure 2-54 illustrates the PLL using both dividers to synthesize a 133 MHz output clock from a 155 MHz input reference clock. The input frequency of 155 MHz is multiplied by 6 and divided by 7, giving a CLK1 output frequency of 132.86 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. Figure 2-53 illustrates an example where the PLL is used to multiply a 155.5 MHz external clock up to 622 MHz. Note that the same PLL schematic could use an external 350 MHz clock, which is divided down to 155 MHz by the FPGA internal logic. DividerJ 6 PowerDown RefCLK 155.5 MHz Delay Line Lock /i Delay Match CLK1 /j PLL FB Delay Line /i /j Delay Match CLK2 622 MHz FBMuxSel 5 DelayLine 6 DividerI LowFreq 3 Osc /4 Figure 2-53 * Using the PLL 155.5 MHz In, 622 MHz Out /7 DividerJ 6 PowerDown RefCLK Delay Line 155 MHz /i Delay Match 155 MHz Lock 132.8 MHz 930 MHz PLL /j CLK1 FB Delay Line /i 155 MHz /j Delay Match CLK2 Yes 5 FBMuxSel DelayLine 3 6 DividerI LowFreq Osc /6 Figure 2-54 * Using the PLL 155 MHz In, 133 MHz Out v2.3 2-69 Axcelerator Family FPGAs Adjustable Clock Delay Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output clock is accomplished by using the delay line in the feedback path. DividerJ 6 PowerDown Lock RefCLK Delay Line 133 MHz /i Delay Match PLL CLK1 /j FB Delay Line /j /j Delay Match CLK2 133 MHz 5 FBMuxSel DelayLine 6 DividerI 3 LowFreq /1 Figure 2-55 * Using the PLL Delaying the Reference Clock 2 -7 0 v2.3 Osc Axcelerator Family FPGAs Clock Skew Minimization Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (CLK2) feeds a routed clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Axcelerator Family PLL and Clock Management application note for more information. DividerJ 6 Lock PowerDown RefCLK Input Clock /i Delay Match Delay Line 133 MHz 133 MHz PLL FB Delay Line CLK1 /j /i /i Delay Match CLK2 133 MHz FBMuxSel 6 DividerI /1 5 DelayLine Q SET LowFreq 3 Osc D QCLR Clock Network Figure 2-56 * Using the PLL for Clock Deskewing v2.3 2-71 Axcelerator Family FPGAs Embedded Memory The AX architecture provides extensive, high-speed memory resources to the user. Each 4,608 bit block of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either RAM or FIFO. RA [K:0] To meet the needs of high performance designs, the memory blocks operate in synchronous mode for both read and write operations. However, the read and write clocks are completely independent, and each may operate up to and above 500 MHz. RCLK No additional core logic resources are required to cascade the address and data buses when cascading different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading. WEN WCLK The AX memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A block diagram of the memory module is illustrated in Figure 2-57. RW [2:0] During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion. RD [(N-1):0] REN WD [(M-1):0] WA [J:0] PIPE WW [2:0] Figure 2-57 * Axcelerator Memory Module RAM Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion (Table 2-85). Each block has independent read and write ports which enable simultaneous read and write operations. Table 2-85 * Memory Block WxD Options Data-word (in bits) Depth Address Bus Data Bus 1 4,096 RA/WA[11:0] RD/WD[0] 2 2,048 RA/WA[10:0] RD/WD[1:0] 4 1,024 RA/WA[9:0] RD/WD[3:0] 9 512 RA/WA[8:0] RD/WD[8:0] 18 256 RA/WA[7:0] RD/WD[17:0] 36 128 RA/WA[6:0] RD/WD[35:0] 2 -7 2 v2.3 Axcelerator Family FPGAs Clocks The D x W different configurations are: 128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable RW and WW values are shown in Table 2-87. The RCLK and the WCLK have independent source polarity selection and can be sourced by any global or local signal. When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. RAM Configurations The AX architecture allows the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9. Note that the RAM blocks employ little-endian byte order for read and write operations. Both the write width and read width for the RAM blocks can be specified independently and changed dynamically with the WW (write width) and RW (read width) pins. Table 2-86 * RAM Signal Description Signal Direction Description WCLK Input Write clock (can be active on either edge). WA[J:0] Input Write address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15. WD[M-1:0] Input Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. RCLK Input Read clock (can be active on either edge). RA[K:0] Input Read address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. REN Input Read enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD. WEN Input Write enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA. RW[2:0] Input Width of the read operation dataword. WW[2:0] Input Width of the write operation dataword. Pipe Input Sets the pipe option to be on or off. Table 2-87 * Allowable RW and WW Values RW(2:0) WW(2:0) DxW 000 000 4k x 1 001 001 2k x 2 010 010 1k x 4 011 011 512 x 9 100 100 256 x 18 101 101 128 x 36 11x 11x reserved v2.3 2-73 Axcelerator Family FPGAs Modes of Operation higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables this mode. There are two read modes and one write mode: * Read Nonpipelined (synchronous - one clock edge) * Read Pipelined (synchronous - two clock edges) * Write (synchronous - one clock edge) On the write active-clock edge, the write data are written into the SRAM at the write address when WEN is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock. In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the readport active-clock edge and data appears at read-data after the RAM access time. Setting the PIPE to OFF enables this mode. Write and read transfers are described with timing requirements beginning in "Timing Characteristics". The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much Timing Characteristics WD RD WA RA WCLK RCLK WEN REN Figure 2-58 * SRAM Model tWCKP tWCKH tWCKL WCLK tWxxSU WA<11:0>, WD<35:0>, WEN<4:0> Figure 2-59 * RAM Write Timing Waveforms 2 -7 4 v2.3 tWxxHD Axcelerator Family FPGAs tRCKH tRCKP tRCKL RCLK tRxxSU tRxxHD RA<11:0>, REN<4:0> tRCK2RD1 tRCK2RD2 RD <35:0> Figure 2-60 * RAM Read Timing Waveforms Table 2-88 * One RAM Block Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 0.94 1.08 1.23 1.45 ns tWDAHD Write Data Hold vs. WCLK 0.19 0.22 0.25 0.30 ns tWADSU Write Address Setup vs. WCLK 0.94 1.08 1.23 1.45 ns tWADHD Write Address Hold vs. WCLK 0.19 0.22 0.25 0.30 ns tWENSU Write Enable Setup vs. WCLK 0.94 1.08 1.23 1.45 ns tWENHD Write Enable Hold vs. WCLK 0.19 0.22 0.25 0.30 ns tWCKH WCLK Minimum High Pulse Width 0.85 0.98 1.11 1.31 ns tWCLK WCLK Minimum Low Pulse Width 1.00 1.15 1.30 1.53 ns tWCKP WCLK Minimum Period 1.99 2.29 2.61 3.07 ns Read Mode tRADSU Read Address Setup vs. RCLK 0.70 0.81 0.92 1.08 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 0.70 0.81 0.92 1.08 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.21 1.39 1.59 1.86 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.27 2.62 2.98 3.5 ns tRCLKH RCLK Minimum High Pulse Width 0.87 1.00 1.14 1.34 ns tRCLKL RCLK Minimum Low Pulse Width 1.05 1.21 1.38 1.62 ns tRCKP RCLK Minimum Period 2.10 2.42 2.76 3.24 ns v2.3 2-75 Axcelerator Family FPGAs Table 2-89 * Two RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 1.21 1.39 1.59 1.86 ns tWDAHD Write Data Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWADSU Write Address Setup vs. WCLK 1.21 1.39 1.59 1.86 ns tWADHD Write Address Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWENSU Write Enable Setup vs. WCLK 1.21 1.39 1.59 1.86 ns tWENHD Write Enable Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWCKH WCLK Minimum High Pulse Width 0.85 0.98 1.11 1.31 ns tWCLK WCLK Minimum Low Pulse Width 1.99 2.29 2.61 3.07 ns tWCKP WCLK Minimum Period 3.98 4.58 5.22 6.13 ns Read Mode tRADSU Read Address Setup vs. RCLK 1.48 1.7 1.94 2.28 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 1.48 1.7 1.94 2.28 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.31 1.51 1.72 2.02 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.4 2.76 3.14 3.69 ns tRCLKH RCLK Minimum High Pulse Width 0.83 0.95 1.08 1.27 ns tRCLKL RCLK Minimum Low Pulse Width 2.14 2.46 2.8 3.29 ns tRCKP RCLK Minimum Period 4.28 4.92 5.6 6.59 ns 2 -7 6 v2.3 Axcelerator Family FPGAs Table 2-90 * Four RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 2.06 2.37 2.7 3.17 ns tWDAHD Write Data Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWADSU Write Address Setup vs. WCLK 2.06 2.37 2.7 3.17 ns tWADHD Write Address Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWENSU Write Enable Setup vs. WCLK 2.06 2.37 2.7 3.17 ns tWENHD Write Enable Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWCKH WCLK Minimum High Pulse Width 0.85 0.98 1.11 1.31 ns tWCLK WCLK Minimum Low Pulse Width 2.84 3.27 3.72 4.37 ns tWCKP WCLK Minimum Period 5.68 6.53 7.44 8.75 ns Read Mode tRADSU Read Address Setup vs. RCLK 2.68 3.08 3.51 4.13 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 2.68 3.08 3.51 4.13 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 2.16 2.49 2.83 3.33 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.92 3.36 3.82 4.5 ns tRCLKH RCLK Minimum High Pulse Width 0.83 0.95 1.08 1.27 ns tRCLKL RCLK Minimum Low Pulse Width 3.35 3.85 4.39 5.16 ns tRCKP RCLK Minimum Period 6.7 7.7 8.78 10.32 ns v2.3 2-77 Axcelerator Family FPGAs Table 2-91 * Eight RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 5.02 5.78 6.58 7.74 ns tWDAHD Write Data Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWADSU Write Address Setup vs. WCLK 5.02 5.78 6.58 7.74 ns tWADHD Write Address Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWENSU Write Enable Setup vs. WCLK 5.02 5.78 6.58 7.74 ns tWENHD Write Enable Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWCKH WCLK Minimum High Pulse Width 0.85 0.98 1.11 1.31 ns tWCLK WCLK Minimum Low Pulse Width 5.8 6.68 7.6 8.94 ns tWCKP WCLK Minimum Period 11.61 13.35 15.21 17.88 ns Read Mode tRADSU Read Address Setup vs. RCLK 5.87 6.75 7.69 9.04 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 5.87 6.75 7.69 9.04 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.1 3.57 4.06 4.77 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 4.76 5.48 6.24 7.34 ns tRCLKH RCLK Minimum High Pulse Width 0.83 0.95 1.08 1.27 ns tRCLKL RCLK Minimum Low Pulse Width 6.53 7.51 8.55 10.05 ns tRCKP RCLK Minimum Period 13.06 15.02 17.11 20.11 ns 2 -7 8 v2.3 Axcelerator Family FPGAs Table 2-92 * Sixteen RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description '-2' Speed '-1' Speed 'Std' Speed Min. Max. Min. Max. Min. Max. Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 14.38 16.54 18.84 22.15 ns tWDAHD Write Data Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWADSU Write Address Setup vs. WCLK 14.38 16.54 18.84 22.15 ns tWADHD Write Address Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWENSU Write Enable Setup vs. WCLK 14.38 16.54 18.84 22.15 ns tWENHD Write Enable Hold vs. WCLK 0.19 0.22 0.25 0.3 ns tWCKH WCLK Minimum High Pulse Width 0.85 0.98 1.11 1.31 ns tWCLK WCLK Minimum Low Pulse Width 15.16 17.44 19.86 23.35 ns tWCKP WCLK Minimum Period 30.33 34.87 39.73 46.7 ns Read Mode tRADSU Read Address Setup vs. RCLK 15.76 18.13 20.65 24.27 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 15.76 18.13 20.65 24.27 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 11.06 12.71 14.48 17.03 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 12.1 13.91 15.85 18.63 ns tRCLKH RCLK Minimum High Pulse Width 0.83 0.95 1.08 1.27 ns tRCLKL RCLK Minimum Low Pulse Width 16.31 18.75 21.36 25.11 ns tRCKP RCLK Minimum Period 32.61 37.5 42.72 50.22 ns v2.3 2-79 Axcelerator Family FPGAs FIFO Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one write port. This embedded FIFO controller uses no internal FPGA logic and features: * Glitch-free FIFO Flags * Gray-code address counters/pointers to prevent metastability problems * Overflow and underflow control The FIFO block offers programmable almost-empty (AEMPTY) and almost-full (AFULL) flags as well as EMPTY and FULL flags (Figure 2-61): * The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full. * The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty condition. Gray code counters are used to prevent metastability problems associated with flag logic. The depth of the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are synchronous with respect to the RCLK. Both ports are configurable in various sizes from 4k x 1 to 128 x 36, similar to the RAM block size. Each port is fully synchronous. Read and write operations can be completely independent. Data on the appropriate WD pins are written to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output on the appropriate RD pins on every active RCLK edge as long as REN is asserted. The FIFO block may be reset to the empty state. RD [n-1:0] WD [n-1:0] RCLK WCLK RCLK WCLK RAM REN WEN PIPE RA [J:0] WA [J:0] RW[2:0] WW[2:0] WD FREN CNT 16 E FULL = AFULL AFVAL SUB 16 > AEMPTY >= AEVAL FWEN CNT 16 E = CLR Figure 2-61 * Axcelerator RAM with Embedded FIFO Controller 2 -8 0 v2.3 EMPTY WIDTH[2:0] DEPTH[3:0] RD Axcelerator Family FPGAs FIFO Flag Logic The FIFO is user configurable into various DEPTHs and WIDTHs. Figure 2-62 shows the FIFO address counter details. * Bits 11 to 5 are active for all modes. * As the data word size is reduced, more leastsignificant bits are added to the address. * As the number of cascaded blocks increases, the number of significant bits in the address increases. RAM block, whereas bits 13 and 12 will be used to specify the RAM block. The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depends on the configuration. The effective number of threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-93). For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify locations within each FIFO Address Counters Mode when Active Counter Bits FIFO Address Alignment of Threshold bits Cas 16 blks CNTR [15] activate R/W EN[3] Cas 8 blks CNTR [14] activate R/W EN[2] AEVAL/AFVAL[6] Cas 4 blks CNTR [13] activate R/W EN[1] AEVAL/AFVAL[5] CNTR [12] activate R/W EN[0] Cas 2 blks by 36 R/W ADD[11:8] CNTR [11:5] always active R/W ADD[7:5] AEVAL/AFVAL[7] AEVAL/AFVAL[4] AEVAL/AFVAL[3:0] not compared [15:W] [14:W] [12:W] [13:W] 128x36 256x18 512x9 CNTR [4] activate R/W ADD[4] by 9 CNTR [3] activate R/W ADD[3] not compared by 4 CNTR [2] activate R/W ADD[2] not compared by 2 CNTR [1] activate R/W ADD[1] not compared by 1 CNTR [0] activate R/W ADD[0] not compared 4kx1 2kx2 [11:5] [11:4] by 18 1kx4 not compared [11:3] [11:2] CNTR [15:0] [11:1] [11:0] Variable Active Address Space >> REN [4:0], RAD [11:0] >> WEN [4:0], WAD [11:0] Note: Inactive counter bits are set to zero. Figure 2-62 * FIFO Address Counters Table 2-93 * FIFO Flag Logic Mode Inactive AEVAL/AFVAL bits Inactive DIFF bits (set to 0) DIFF comparison to AFVAL/AEVAL Non-cascade [7:4] [15:12] DIFF[11:8] withAE/FVAL[3:0] Cascade 2 blocks [7:5] [15:13] DIFF[12:8] withAE/FVAL[4:0] Cascade 4 blocks [7:6] [15:14] DIFF[13:8] withAE/FVAL[5:0] Cascade 8 blocks [7] [15] DIFF[14:8] withAE/FVAL[6:0] Cascade 16 blocks None None DIFF[15:8] withAE/FVAL[7:0] v2.3 2-81 Axcelerator Family FPGAs Figure 2-63 illustrates flag generation. The Verilog codes for the flags are: assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0; The number of DIFF-bits active depends on the configuration depth and width (Table 2-94). ALMOST EMPTY and ALMOST FULL Logic AEMPTY AEVAL [7:0], GND [7:0] (MSB....LSB) X WCLK WCNTR [15:0] Y 16 X>=Y (16 bit) DIFF [15:0] RCLK RCNTR [15:0] 16 AFULL X AFVAL [7:0], GND [7:0] (MSB....LSB) Y Figure 2-63 * ALMOST-EMPTY and ALMOST-FULL Logic Table 2-94 * Number of Available Configuration Bits Number of Blocks Block DxW Number of AEVAL/AFVAL Bits 1 1x1 4 2 1x2 4 2 2x1 5 4 1x4 4 4 2x2 5 4 4x1 6 8 1x8 4 8 2x4 5 8 4x2 6 8 8x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 2 -8 2 v2.3 Axcelerator Family FPGAs Overflow and Underflow Control The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high. The counter MSB keeps track of the difference between the read address (RA) and the write address (WA). The EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the write address is doublesampled by the read clock prior to comparison with the read address (part A in Figure 2-64). To prevent overflow, the read address is double-sampled by the write clock prior to comparison to the write address (part B in Figure 2-64). Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-85. Glitch Elimination An analog filter is added to each FIFO controller to guarantee glitch-free FIFO-flag logic. A B WA RCLK RA RA = = EMPTY WCLK WA FULL Figure 2-64 * Overflow and Underflow Control FIFO Configurations Clock Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO, the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable word widths, as shown in Table 2-95. As with RAM configuration, the RCLK and WCLK pins have independent polarity selection Table 2-95 * FIFO Width Configurations The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2, 4, 8, and 16 to be specified. Table 2-85 on page 2-72 describes the FIFO depth options for various data width and memory blocks. Interface WIDTH(2:0) WxD 000 1 x 4k 001 2 x 2k 010 4 x 1k 011 9 x 512 100 18 x 256 101 36 x 128 11x reserved Figure 2-65 shows a logic block diagram of the Axcelerator FIFO module. Cascading FIFO Blocks FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be taken into account when building the FIFO blocks manually. However, when using ACTgen, the user only needs to specify the depth and width of the necessary FIFO blocks. ACTgen automatically configures these blocks to optimize performance. DEPTH [3:0] RD [35:0] WIDTH [2:0] PIPE FREN FULL RCLK AEVAL [7:0] EMPTY AFULL AEMPTY AFVAL [7:0] WD [35:0] FWEN WCLK CLR Figure 2-65 * FIFO Block Diagram v2.3 2-83 Axcelerator Family FPGAs Table 2-96 * FIFO Signal Description Signal Direction Description WCLK Input Write clock (active either edge). FWEN Input FIFO write enable. When this signal is asserted, the WD bus data is latched into the FIFO, and the internal write counters are incremented. WD[N-1:0] Input Write data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. FULL Output Active high signal indicating that the FIFO is FULL. When this signal is set, additional write requests are ignored. AFULL Output Active high signal indicating that the FIFO is AFULL. AFVAL Input 8-bit input defining the AFULL value of the FIFO. RCLK Input Read clock (active either edge). FREN Input FIFO read enable. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. EMPTY Output Empty flag indicating that the FIFO is EMPTY. When this signal is asserted, attempts to read the FIFO will be ignored. AEMPTY Output Active high signal indicating that the FIFO is AEMPTY. AEVAL Input 8-bit input defining the almost-empty value of the FIFO. PIPE Input Sets the pipe option on or off. CLR Input Active high clear input. DEPTH Input Determines the depth of the FIFO and the number of FIFOs to be cascaded. WIDTH Input Determines the width of the dataword / width of the FIFO, and the number of the FIFOs to be cascaded. 2 -8 4 v2.3 Axcelerator Family FPGAs Timing Characteristics WD RD AEMPTY EMPTY AFULL FULL FWEN FREN WCLK RCLK Clr Figure 2-66 * FIFO Model tWCKP tWCKH tWCKL WCLK tWSU tWHD WD<35:0>, FWEN tCLR2HF CLR tCLR2xF tCK2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-67 * FIFO Write Timing v2.3 2-85 Axcelerator Family FPGAs tRCKH tRCKP RCLK tRSU tRCKL tRHD FREN tRCK2RD1 tRCK2RD2 RD <35:0> tCLRHF CLR tCLR2xF tCK2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-68 * FIFO Read Timing Table 2-97 * One FIFO Block Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 0.94 1.08 1.23 1.45 ns tWHD Write Hold 0.19 0.22 0.25 0.30 ns tWCKH WCLK High 0.85 0.98 1.11 1.31 ns tWCKL WCLK Low 1.00 1.15 1.30 1.53 ns tWCKP Minimum WCLK Period tRSU Read Setup 0.70 0.81 0.92 1.08 ns tRHD Read Hold 0.00 0.00 0.00 0.00 ns tRCKH RCLK High 0.87 1.00 1.14 1.34 ns tRCKL RCLK Low tRCKP Minimum RCLK period tCLRHF Clear High 0.94 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.75 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.02 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 1.95 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 4.62 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.21 1.39 1.59 1.86 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.27 2.62 2.98 3.5 ns 2 -8 6 2 2.3 1.05 2.1 2.6 1.21 2.42 v2.3 3.06 1.38 2.76 ns 1.62 3.24 ns ns Axcelerator Family FPGAs Table 2-98 * Two FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C Parameter Description '-3' Speed '-2' Speed '-1' Speed 'Std' Speed Min. Min. Min. Min. Max. Max. Max. Max. Units FIFO Module Timing tWSU Write Setup 1.21 1.39 1.59 1.86 ns tWHD Write Hold 0.19 0.22 0.25 0.3 ns tWCKH WCLK High 0.85 0.98 1.11 1.31 ns tWCKL WCLK Low 1.99 2.29 2.61 3.07 ns tWCKP Minimum WCLK Period tRSU Read Setup 1.48 1.7 1.94 2.28 ns tRHD Read Hold 0 0 0 0 ns tRCKH RCLK High 0.83 0.95 1.08 1.27 ns tRCKL RCLK Low 2.14 2.46 2.8 3.29 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.94 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.75 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.02 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 1.95 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 4.62 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.31 1.51 1.72 2.02 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 2.4 2.76 3.14 3.69 ns 3.98 4.58 4.28 5.22 4.92 6.14 5.6 ns 6.58 ns Table 2-99 * Four FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 2.06 2.37 2.7 3.17 ns tWHD Write Hold 0.19 0.22 0.25 0.3 ns tWCKH WCLK High 0.85 0.98 1.11 1.31 ns tWCKL WCLK Low tWCKP Minimum WCLK Period tRSU Read Setup 2.68 3.08 3.51 4.13 ns tRHD Read Hold 0 0 0 0 ns tRCKH RCLK High 0.83 0.95 1.08 1.27 ns tRCKL RCLK Low 3.35 3.85 4.39 5.16 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.94 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.75 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.02 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 1.95 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 4.62 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 2.16 2.49 2.83 3.33 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 2.92 3.36 3.82 4.5 ns 2.84 5.68 3.27 6.54 6.7 7.7 v2.3 3.72 7.44 4.37 8.74 8.78 ns ns 10.32 ns 2-87 Axcelerator Family FPGAs Table 2-100 * Eight FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 5.02 5.78 6.58 7.74 ns tWHD Write Hold 0.19 0.22 0.25 0.3 ns tWCKH WCLK High 0.85 0.98 1.11 1.31 ns tWCKL WCLK Low 5.8 6.68 7.6 8.94 ns tWCKP Minimum WCLK Period tRSU Read Setup 5.87 6.75 7.69 9.04 ns tRHD Read Hold 0 0 0 0 ns tRCKH RCLK High 0.83 0.95 1.08 1.27 ns tRCKL RCLK Low 6.53 7.51 8.55 10.05 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.94 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.75 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.02 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 1.95 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 4.62 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.1 3.57 4.06 4.77 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 4.76 5.48 6.24 7.34 ns 11.6 13.36 13.08 15.2 15.02 17.88 17.1 ns 20.1 ns Table 2-101 * Sixteen FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-3' Speed Parameter Description Min. Max. '-2' Speed Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 14.38 16.54 18.84 22.15 ns tWHD Write Hold 0.19 0.22 0.25 0.3 ns tWCKH WCLK High 0.85 0.98 1.11 1.31 ns tWCKL WCLK Low tWCKP Minimum WCLK Period tRSU Read Setup 15.76 18.13 20.65 24.27 ns tRHD Read Hold 0 0 0 0 ns tRCKH RCLK High 0.83 0.95 1.08 1.27 ns tRCKL RCLK Low 16.31 18.75 21.36 25.11 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.94 1.08 1.23 1.45 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.75 2.02 2.3 2.7 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.02 4.62 5.26 6.19 ns tCK2FF Clock-to-flag (EMPTY/FULL) 1.95 2.24 2.55 3 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 4.62 5.31 6.05 7.11 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 11.06 12.71 14.48 17.03 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 12.1 13.91 15.85 18.63 ns 2 -8 8 15.16 30.32 17.44 34.88 32.62 37.5 v2.3 19.86 39.72 23.35 46.7 42.72 ns ns 50.22 ns Axcelerator Family FPGAs Building RAM and FIFO Modules RAM and FIFO modules can be generated and included in a design in two different ways: * Using the ACTgen Core Generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (please refer to Actel's ACTgen Macros User's Guide for more information). * The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground. v2.3 2-89 Axcelerator Family FPGAs Other Architectural Features Low Power Mode Although designed for high performance, the AX architecture also allows the user to place the device into a low power mode. Each I/O bank in an Axcelerator device can be configured individually, when in low power mode, to tristate all outputs, disable inputs, or both. The low power mode is activated by asserting the LP pin, which is grounded in normal operation. While in the low power mode, the device is still fully functional and all internal logic states are preserved. This allows a user to disable all but a few signals and operate the part in a low-frequency, watchdog mode if desired. Please note, if the I/O bank is not disabled, differential I/Os belonging to the I/O bank will still consume normal power, even when operating in the low power mode. The Axcelerator device will resume normal operation 10s after the LP pin is pulled Low. To further reduce power consumption, the internal charge pump can be bypassed and an external power supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in no DC current draw. The Axcelerator family devices have a dedicated "VPUMP" pin that can be used to access an external charge pump device. In normal chip operation, when using the internal charge pump, VPUMP should be tied to GND. When the voltage level on VPUMP is set to 3.3V, the internal charge pump is turned off, and the VPUMP voltage will be used as the charge pump voltage. Adequate voltage regulation (i.e. high drive, low output impedance, and good decoupling) should be used at VPUMP. In addition, any PLL in use can be powered down to further reduce power consumption. This can be done with the PowerDown pin driven Low. Driving this pin High restarts the PLL with the output clock(s) being stable once lock is restored. JTAG Axcelerator offers a JTAG interface that is compliant with the IEEE 1149.1 standard. The user can employ the JTAG interface for probing a design and performing any JTAG Public Instructions as defined in the Table 2-102. Interface The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up resistors. 2 -9 0 v2.3 Table 2-102 * JTAG Instruction Code Instruction (IR4:IR0) Binary Code Extest 00000 Preload / Sample 00001 Intest 00010 USERCODE 00011 IDCODE 00100 HIGHZ 01110 CLAMP 01111 Diagnostic 10000 Reserved Bypass All others 11111 TRST TRST (Test-Logic Reset) is an active-low, asynchronous reset signal to the TAP controller. The TRST input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the TRST state, it is recommended to connect TRST to ground via a 1 k resistor. There is an optional internal pull-up resistor available for the TRST input that can be set by the user at programming. Care should be exercised when using this option in combination with an external tie-off to ground. An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST," but it only occurs at power-up or during recovery from a VCCA and/ or VCCDA voltage drop. TDO TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or "Shift_IR" state. The least significant bit of the selected register (i.e. IR or DR) is clocked out to TDO first by the falling edge of TCK. TAP Controller The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that controls the Instruction Register (IR) and the Data Registers (such as BSR, IDCODE, USRCODE, BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at the rising edges of TCK. Axcelerator Family FPGAs Special Fuses Instruction Register (IR) The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR." When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111." If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully" flag. Security Actel antifuse FPGAs, with FuseLock technology, offer the highest level of design security available in a programmable logic device. Since antifuse FPGAs are live-at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the device during power-up, thus making device cloning impossible. In addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive and noninvasive attacks against an Axcelerator device that access or bypass these security fuses will destroy access to the rest of the device. (refer to the Design Security in Nonvolatile Flash and Antifuse FPGAs white paper). Data Registers (DRs) Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data registers. Descriptions of the main registers are as follow: Look for this symbol to ensure your valuable IP is secure. 1. IDCODE: TM The IDCODE is a 32-bit hard coded JTAG Silicon Signature. It is a hardwired device ID code, which contains the Actel identity, part number, and version number in a specific JTAG format. u e 2. USERCODE: Figure 2-69 * FuseLock Logo The USERCODE is a 32-bit programmable JTAG Silicon Signature. It is a supplementary identity code for the user to program information to distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. To ensure maximum security in Axcelerator devices, it is recommended that the user program the device security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent internal probing, and the programming interface is also disabled. All JTAG public instructions are still accessible by the user. 3. Boundary-Scan Register (BSR): For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note. Each I/O contains three Boundary-Scan Cells. Each cell has a shift register bit, a latch, and two MUXes. The boundary-scan cells are used for the Output-enable (E), Output (O), and Input (I) registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan cells are then chained serially to form the Boundary-Scan Register (BSR). The length of the BSR is the number of I/Os in the die multiplied by three. Global Set Fuse The Global Set Fuse determines if all R-cells and I/O registers (InReg, OutReg, and EnReg) are either cleared or preset by driving the GCLR and GPSET inputs of all Rcells and I/O Registers (Figure 2-31 on page 2-47). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and GPSET= 0). A local CLR or PRESET will take precedence over this setting. Both pins are pulled High during normal device operation. For use details, see the Libero IDE online help. 4. Bypass Register (BYR): This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to only one bit per device not being tested. It is also selected for all "reserved" or unused instructions. Probing Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB," "PRC," and "PRD." v2.3 2-91 Axcelerator Family FPGAs Silicon Explorer II Probe Interface Programming Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is operating in a prototype or a production system. The user can probe up to four nodes at a time without changing the placement and routing of the design and without using any additional device resources. Highlighted nets in Designer's ChipPlanner can be accessed using Silicon Explorer II in order to observe their real time values. Device programming is supported through the Silicon Sculptor II, a single-site, robust and compact device programmer for the PC. Up to four Silicon Sculptor IIs can be daisy-chained and controlled from a single PC host. With standalone software for the PC, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC when daisy-chained. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals out to external pins, which is necessary when using programmable logic devices from other suppliers. By eliminating multiple place-and-route program cycles, the integrity of the design is maintained throughout the debug process. Each member of the Axcelerator family has four external pads: PRA, PRB, PRC, and PRD. These can be used to bring out four probe signals from the Axcelerator device (note that the AX125 only has two probe signals that can be observed: PRA and PRB). Each core tile has up to two probe signals. To disallow probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on page 2-91). Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the circuit board are achieved using a nine-pin D-Sub connector (Figure 1-9 on page 1-7). Once the design has been placed-and-routed, and the Axcelerator device has been programmed, Silicon Explorer II can be connected and the Explorer software can be launched. Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. The software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. 2 -9 2 v2.3 Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. Each fuse is verified by Silicon Sculptor II to ensure correct programming. Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming was completed properly. Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor II also provides a self-test to test its own hardware extensively. Programming an Axcelerator device using Silicon Sculptor II is similar to programming any other antifuse device. The procedure is as follows: 1. Load the .AFM file. 2. Select the device to be programmed. 3. Begin programming. When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via our In-House Programming Center. In addition, BP programmers that Axcelerator devices. Microsystems offers multi-site provide qualified support for For more details on programming the Axcelerator devices, please refer to the Silicon Sculptor II User's Guide. Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 * 180-Pin CSP (Bottom View) v2.3 3-1 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number Bank 0 180-Pin CSP AX125 Function Pin Number AX125 Function Pin Number IO32NB3F3 H11 IO59NB5F5 N2 IO59PB5F5 P2 IO00NB0F0 B3 IO32PB3F3 H12 IO00PB0F0 A3 IO34NB3F3 K14 IO02NB0F0 B4 IO34PB3F3 J14 IO60NB6F6 M1 IO02PB0F0 A4 IO36NB3F3 K13 IO60PB6F6 N1 IO07NB0F0/HCLKAN B5 IO36PB3F3 J13 IO62NB6F6 K3 IO07PB0F0/HCLKAP A5 IO38NB3F3 L13 IO62PB6F6 L3 IO08NB0F0/HCLKBN B7 IO38PB3F3 L14 IO64NB6F6 L2 IO08PB0F0/HCLKBP B6 IO40NB3F3 M13 IO64PB6F6 L1 IO40PB3F3 M14 IO66NB6F6 K2 Bank 1 Bank 6 IO09NB1F1/HCLKCN C9 IO41NB3F3 K12 IO66PB6F6 K1 IO09PB1F1/HCLKCP C8 IO41PB3F3 J12 IO68NB6F6 H3 IO10NB1F1/HCLKDN A10 IO68PB6F6 J3 IO10PB1F1/HCLKDP B10 IO42NB4F4 P13 IO70NB6F6 G4 IO11NB1F1 B11 IO42PB4F4 N13 IO70PB6F6 H4 IO11PB1F1 A11 IO43NB4F4 L12 IO71NB6F6 J1 IO15NB1F1 B12 IO43PB4F4 M12 IO71PB6F6 J2 IO15PB1F1 A12 IO46NB4F4 P12 IO17NB1F1 D12 IO46PB4F4 N12 IO72NB7F7 G2 IO17PB1F1 D11 IO47NB4F4 N11 IO72PB7F7 H2 IO47PB4F4 P11 IO74NB7F7 F3 Bank 2 Bank 7 IO18NB2F2 C13 IO49NB4F4/CLKEN M11 IO74PB7F7 G3 IO18PB2F2 C12 IO49PB4F4/CLKEP M10 IO76NB7F7 F1 IO19NB2F2 C14 IO50NB4F4/CLKFN N9 IO76PB7F7 F2 IO19PB2F2 B14 IO50PB4F4/CLKFP P9 IO78NB7F7 E1 IO20NB2F2 D13 IO78PB7F7 E2 IO20PB2F2 D14 IO51NB5F5/CLKGN M7 IO79NB7F7 D2 IO22NB2F2 F12 IO51PB5F5/CLKGP M8 IO79PB7F7 D1 IO22PB2F2 E12 IO52NB5F5/CLKHN P5 IO83NB7F7 C1 IO24NB2F2 E13 IO52PB5F5/CLKHP N5 IO83PB7F7 C2 IO24PB2F2 E14 IO53NB5F5 P4 IO26NB2F2 F13 IO53PB5F5 N4 VCCDA B1 IO26PB2F2 F14 IO55NB5F5 P3 GND A1 IO28NB2F2 G12 IO55PB5F5 N3 GND A14 IO28PB2F2 G11 IO56NB5F5 M4 GND A7 IO56PB5F5 M5 GND A8 Bank 3 3 -2 Bank 4 Bank 5 Dedicated I/O IO30NB3F3 H13 IO57NB5F5 M2 GND E10 IO30PB3F3 G13 IO57PB5F5 M3 GND E5 v2.3 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number AX125 Function Pin Number GND E6 VCCPLF L8 GND E9 VCCPLG P6 GND F10 VCCPLH M6 GND F5 VCCDA B13 GND G1 VCCDA D3 GND G14 VCCDA E8 GND H1 VCCDA G5 GND H14 VCCDA H10 GND J10 VCCDA K7 GND J5 VCCDA L11 GND K10 VCCDA L4 GND K5 VCCIB0 D5 GND K6 VCCIB0 D6 GND K9 VCCIB1 D10 GND N14 VCCIB1 D9 GND P1 VCCIB2 E11 GND P14 VCCIB2 F11 GND P7 VCCIB3 J11 GND P8 VCCIB3 K11 GND/LP C3 VCCIB4 L10 PRA D8 VCCIB4 L9 PRB B8 VCCIB5 L5 PRC N8 VCCIB5 L6 PRD N7 VCCIB6 J4 TCK C4 VCCIB6 K4 TDI E3 VCCIB7 E4 TDO C5 VCCIB7 F4 TMS D4 VCCDA A2 TRST B2 VCOMPLA A6 VCCA E7 VCOMPLB D7 VCCA G10 VCOMPLC B9 VCCA H5 VCOMPLD C11 VCCA K8 VCOMPLE P10 VCCPLA C6 VCOMPLF M9 VCCPLB C7 VCOMPLG N6 VCCPLC A9 VCOMPLH L7 VCCPLD C10 VPUMP A13 VCCPLE N10 v2.3 3-3 Axcelerator Family FPGAs 729-Pin PBGA A1 Ball Pad Corner 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG Figure 3-2 * 729-Pin PBGA (Bottom View) 3 -4 v2.3 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number Bank 0 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number IO18PB0F1 C9 IO37NB1F3 C17 IO00NB0F0 E6 IO19NB0F1 E11 IO37PB1F3 C16 IO00PB0F0 F6 IO19PB0F1 F11 IO38NB1F3 B18 IO01NB0F0 G8 IO20NB0F1 G12 IO38PB1F3 B17 IO01PB0F0 G7 IO20PB0F1 H12 IO39NB1F3 A18 IO02NB0F0 D7 IO21NB0F1 D11 IO39PB1F3 A17 IO02PB0F0 E7 IO21PB0F1 D10 IO40NB1F3 H16 IO03NB0F0 D5 IO22NB0F2 A10 IO40PB1F3 G16 IO03PB0F0 E5 IO22PB0F2 A9 IO41NB1F4 B19 IO04NB0F0 G9 IO23NB0F2 B11 IO41PB1F4 A19 IO04PB0F0 H9 IO23PB0F2 B10 IO42NB1F4 C19 IO05NB0F0 E8 IO24NB0F2 G13 IO42PB1F4 C18 IO05PB0F0 F8 IO24PB0F2 H13 IO43NB1F4 D18 IO06NB0F0 C6 IO25NB0F2 C12 IO43PB1F4 D17 IO06PB0F0 D6 IO25PB0F2 C11 IO44NB1F4 H17 IO07NB0F0 B5 IO26NB0F2 E12 IO44PB1F4 G17 IO07PB0F0 C5 IO26PB0F2 D12 IO45NB1F4 F17 IO08NB0F0 A6 IO27NB0F2 E13 IO45PB1F4 E17 IO08PB0F0 A5 IO27PB0F2 F13 IO46NB1F4 B20 IO09NB0F0 E9 IO28NB0F2 G14 IO46PB1F4 A20 IO09PB0F0 F9 IO28PB0F2 H14 IO47NB1F4 C21 IO10NB0F0 G10 IO29NB0F2 A12 IO47PB1F4 C20 IO10PB0F0 H10 IO29PB0F2 B12 IO48NB1F4 H18 IO11NB0F0 B7 IO30NB0F2/HCLKAN C13 IO48PB1F4 G18 IO11PB0F0 B6 IO30PB0F2/HCLKAP D13 IO49NB1F4 F18 IO12NB0F1 C8 IO31NB0F2/HCLKBN F14 IO49PB1F4 E18 IO12PB0F1 C7 IO31PB0F2/HCLKBP E14 IO50NB1F4 D20 IO13NB0F1 E10 IO50PB1F4 D19 IO13PB0F1 F10 IO32NB1F3/HCLKCN C14 IO51NB1F4 A22 IO14NB0F1 G11 IO32PB1F3/HCLKCP B14 IO51PB1F4 A21 IO14PB0F1 H11 IO33NB1F3/HCLKDN D16 IO52NB1F4 B22 IO15NB0F1 D9 IO33PB1F3/HCLKDP D15 IO52PB1F4 B21 IO15PB0F1 D8 IO34NB1F3 B16 IO53NB1F4 F19 IO16NB0F1 A8 IO34PB1F3 A16 IO53PB1F4 E19 IO16PB0F1 A7 IO35NB1F3 E15 IO54NB1F5 F20 IO17NB0F1 B9 IO35PB1F3 F15 IO54PB1F5 E20 IO17PB0F1 B8 IO36NB1F3 H15 IO55NB1F5 E21 IO18NB0F1 C10 IO36PB1F3 G15 IO55PB1F5 D21 Bank 1 v2.3 3-5 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO56NB1F5 H19 IO74PB2F7 K21 IO93PB2F8 P27 IO56PB1F5 G19 IO75NB2F7 G27 IO94NB2F8 N19 IO57NB1F5 D22 IO75PB2F7 F27 IO94PB2F8 N20 IO57PB1F5 C22 IO76NB2F7 K23 IO95NB2F8 P23 IO58NB1F5 B23 IO76PB2F7 K22 IO95PB2F8 P22 IO58PB1F5 A23 IO77NB2F7 H26 IO59NB1F5 D23 IO77PB2F7 H25 IO96NB3F9 P25 IO59PB1F5 C23 IO78NB2F7 K25 IO96PB3F9 P24 IO60NB1F5 G21 IO78PB2F7 K24 IO97NB3F9 R26 IO60PB1F5 G20 IO79NB2F7 J26 IO97PB3F9 R27 IO61NB1F5 E23 IO79PB2F7 J25 IO98NB3F9 P21 IO61PB1F5 E22 IO80NB2F7 M20 IO98PB3F9 P20 IO62NB1F5 F22 IO80PB2F7 L20 IO99NB3F9 R24 IO62PB1F5 F21 IO81NB2F7 J27 IO99PB3F9 R25 IO63NB1F5 H20 IO81PB2F7 H27 IO100NB3F9 T26 IO63PB1F5 J19 IO82NB2F7 L23 IO100PB3F9 T27 IO82PB2F7 L22 IO101NB3F9 T24 Bank 2 3 -6 Bank 3 IO64NB2F6 J21 IO83NB2F7 L25 IO101PB3F9 T25 IO64PB2F6 H21 IO83PB2F7 L24 IO102NB3F9 R20 IO65NB2F6 F24 IO84NB2F7 N21 IO102PB3F9 R21 IO65PB2F6 F23 IO84PB2F7 M21 IO103NB3F9 R23 IO66NB2F6 F26 IO85NB2F8 K27 IO103PB3F9 R22 IO66PB2F6 F25 IO85PB2F8 K26 IO104NB3F9 U26 IO67NB2F6 E26 IO86NB2F8 M23 IO104PB3F9 U27 IO67PB2F6 E25 IO86PB2F8 M22 IO105NB3F9 U24 IO68NB2F6 J22 IO87NB2F8 M25 IO105PB3F9 U25 IO68PB2F6 H22 IO87PB2F8 M24 IO106NB3F9 R19 IO69NB2F6 G24 IO88NB2F8 L27 IO106PB3F9 P19 IO69PB2F6 G23 IO88PB2F8 L26 IO107NB3F10 V26 IO70NB2F6 K20 IO89NB2F8 M27 IO107PB3F10 V27 IO70PB2F6 J20 IO89PB2F8 M26 IO108NB3F10 T23 IO71NB2F6 G26 IO90NB2F8 N23 IO108PB3F10 T22 IO71PB2F6 G25 IO90PB2F8 N22 IO109NB3F10 V24 IO72NB2F6 J24 IO91NB2F8 N25 IO109PB3F10 V25 IO72PB2F6 J23 IO91PB2F8 N24 IO110NB3F10 T20 IO73NB2F6 H24 IO92NB2F8 N27 IO110PB3F10 T21 IO73PB2F6 H23 IO92PB2F8 N26 IO111NB3F10 W26 IO74NB2F7 L21 IO93NB2F8 P26 IO111PB3F10 W27 v2.3 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO112NB3F10 U22 IO130PB4F12 AB23 IO149PB4F13 AB17 IO112PB3F10 U23 IO131NB4F12 AC22 IO150NB4F13 AE18 IO113NB3F10 Y26 IO131PB4F12 AC23 IO150PB4F13 AE19 IO113PB3F10 Y27 IO132NB4F12 AD23 IO151NB4F13 AA16 IO114NB3F10 U20 IO132PB4F12 AD24 IO151PB4F13 Y16 IO114PB3F10 U21 IO133NB4F12 AF23 IO152NB4F14 AG18 IO115NB3F10 W24 IO133PB4F12 AE23 IO152PB4F14 AG19 IO115PB3F10 W25 IO134NB4F12 AC21 IO153NB4F14 AC16 IO116NB3F10 V22 IO134PB4F12 AB21 IO153PB4F14 AB16 IO116PB3F10 V23 IO135NB4F12 AC20 IO154NB4F14 AF17 IO117NB3F10 Y24 IO135PB4F12 AB20 IO154PB4F14 AF18 IO117PB3F10 Y25 IO136NB4F12 AD21 IO155NB4F14 AB15 IO118NB3F11 V20 IO136PB4F12 AD22 IO155PB4F14 AC15 IO118PB3F11 V21 IO137NB4F12 Y19 IO156NB4F14 AE16 IO119NB3F11 AA26 IO137PB4F12 AA19 IO156PB4F14 AE17 IO119PB3F11 AA27 IO138NB4F12 AE21 IO157NB4F14 Y15 IO120NB3F11 W22 IO138PB4F12 AE22 IO157PB4F14 AA15 IO120PB3F11 W23 IO139NB4F13 AF21 IO158NB4F14 AG16 IO121NB3F11 AA24 IO139PB4F13 AF22 IO158PB4F14 AG17 IO121PB3F11 AA25 IO140NB4F13 AG22 IO159NB4F14/CLKEN AF15 IO122NB3F11 W20 IO140PB4F13 AG23 IO159PB4F14/CLKEP AF16 IO122PB3F11 W21 IO141NB4F13 Y18 IO160NB4F14/CLKFN AD14 IO123NB3F11 AB26 IO141PB4F13 AA18 IO160PB4F14/CLKFP AD15 IO123PB3F11 AB27 IO142NB4F13 AE20 IO124NB3F11 Y22 IO142PB4F13 AD20 IO161NB5F15/CLKGN AE14 IO124PB3F11 Y23 IO143NB4F13 AG20 IO161PB5F15/CLKGP AE15 IO125NB3F11 AB24 IO143PB4F13 AG21 IO162NB5F15/CLKHN AC13 IO125PB3F11 AB25 IO144NB4F13 AC19 IO162PB5F15/CLKHP AD13 IO126NB3F11 AA22 IO144PB4F13 AB19 IO163NB5F15 Y14 IO126PB3F11 AA23 IO145NB4F13 AD18 IO163PB5F15 AA14 IO127NB3F11 AC26 IO145PB4F13 AD19 IO164NB5F15 AE13 IO127PB3F11 AC27 IO146NB4F13 AC18 IO164PB5F15 AF13 IO128NB3F11 Y20 IO146PB4F13 AB18 IO165NB5F15 AF12 IO128PB3F11 W19 IO147NB4F13 Y17 IO165PB5F15 AG12 IO147PB4F13 AA17 IO166NB5F15 AD12 Bank 4 Bank 5 IO129NB4F12 AA20 IO148NB4F13 AF19 IO166PB5F15 AE12 IO129PB4F12 Y21 IO148PB4F13 AF20 IO167NB5F15 Y13 IO130NB4F12 AB22 IO149NB4F13 AC17 IO167PB5F15 AA13 v2.3 3-7 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO168NB5F15 AD11 IO187NB5F17 Y9 IO205PB6F19 V8 IO168PB5F15 AE11 IO187PB5F17 AA9 IO206NB6F19 V5 IO169NB5F15 AG11 IO188NB5F17 AD6 IO206PB6F19 V6 IO169PB5F15 AF11 IO188PB5F17 AE6 IO207NB6F19 Y1 IO170NB5F15 AB11 IO189NB5F17 AB6 IO207PB6F19 AA1 IO170PB5F15 AC11 IO189PB5F17 AC6 IO208NB6F19 W4 IO171NB5F16 AF10 IO190NB5F17 AF5 IO208PB6F19 Y4 IO171PB5F16 AG10 IO190PB5F17 AG5 IO209NB6F19 T7 IO172NB5F16 AD10 IO191NB5F17 AA6 IO209PB6F19 U7 IO172PB5F16 AE10 IO191PB5F17 AA7 IO210NB6F19 W2 IO173NB5F16 Y12 IO192NB5F17 Y8 IO210PB6F19 Y2 IO173PB5F16 AA12 IO192PB5F17 AA8 IO211NB6F19 U5 IO174NB5F16 AB10 IO211PB6F19 U6 IO174PB5F16 AC10 IO193NB6F18 W8 IO212NB6F19 V3 IO175NB5F16 AF9 IO193PB6F18 Y7 IO212PB6F19 W3 IO175PB5F16 AG9 IO194NB6F18 AB5 IO213NB6F19 R9 IO176NB5F16 AD9 IO194PB6F18 AC5 IO213PB6F19 T8 IO176PB5F16 AE9 IO195NB6F18 AC2 IO214NB6F20 U4 IO177NB5F16 Y11 IO195PB6F18 AC3 IO214PB6F20 V4 IO177PB5F16 AA11 IO196NB6F18 AC4 IO215NB6F20 T5 IO178NB5F16 AF8 IO196PB6F18 AD4 IO215PB6F20 T6 IO178PB5F16 AG8 IO197NB6F18 Y5 IO216NB6F20 V1 IO179NB5F16 AD8 IO197PB6F18 Y6 IO216PB6F20 W1 IO179PB5F16 AE8 IO198NB6F18 AB3 IO217NB6F20 R7 IO180NB5F16 AB9 IO198PB6F18 AB4 IO217PB6F20 R8 IO180PB5F16 AC9 IO199NB6F18 V7 IO218NB6F20 U2 IO181NB5F17 Y10 IO199PB6F18 W7 IO218PB6F20 V2 IO181PB5F17 AA10 IO200NB6F18 AA4 IO219NB6F20 T1 IO182NB5F17 AF7 IO200PB6F18 AA5 IO219PB6F20 U1 IO182PB5F17 AG7 IO201NB6F18 W5 IO220NB6F20 R5 IO183NB5F17 AD7 IO201PB6F18 W6 IO220PB6F20 R6 IO183PB5F17 AE7 IO202NB6F18 AB1 IO221NB6F20 T3 IO184NB5F17 AC7 IO202PB6F18 AC1 IO221PB6F20 T4 IO184PB5F17 AC8 IO203NB6F19 Y3 IO222NB6F20 R2 IO185NB5F17 AF6 IO203PB6F19 AA3 IO222PB6F20 T2 IO185PB5F17 AG6 IO204NB6F19 AA2 IO223NB6F20 P8 IO186NB5F17 AB7 IO204PB6F19 AB2 IO223PB6F20 P9 IO186PB5F17 AB8 IO205NB6F19 U8 IO224NB6F20 R3 3 -8 Bank 6 v2.3 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO224PB6F20 R4 IO243NB7F22 J2 GND AE1 IO243PB7F22 J1 GND AE2 Bank 7 IO225NB7F21 P1 IO244NB7F22 J4 GND AE25 IO225PB7F21 R1 IO244PB7F22 J3 GND AE26 IO226NB7F21 P3 IO245NB7F22 H2 GND AE27 IO226PB7F21 P2 IO245PB7F22 H1 GND AE3 IO227NB7F21 N7 IO246NB7F22 H4 GND AE5 IO227PB7F21 P7 IO246PB7F22 H3 GND AF1 IO228NB7F21 P5 IO247NB7F23 L8 GND AF2 IO228PB7F21 P4 IO247PB7F23 L7 GND AF25 IO229NB7F21 N2 IO248NB7F23 J6 GND AF26 IO229PB7F21 N1 IO248PB7F23 K6 GND AF27 IO230NB7F21 N6 IO249NB7F23 H5 GND AF3 IO230PB7F21 P6 IO249PB7F23 J5 GND AG1 IO231NB7F21 N9 IO250NB7F23 G2 GND AG2 IO231PB7F21 N8 IO250PB7F23 G1 GND AG25 IO232NB7F21 N4 IO251NB7F23 K8 GND AG26 IO232PB7F21 N3 IO251PB7F23 K7 GND AG27 IO233NB7F21 M2 IO252NB7F23 G4 GND AG3 IO233PB7F21 M1 IO252PB7F23 G3 GND B1 IO234NB7F21 M4 IO253NB7F23 F2 GND B2 IO234PB7F21 M3 IO253PB7F23 F1 GND B25 IO235NB7F21 M5 IO254NB7F23 G6 GND B26 IO235PB7F21 N5 IO254PB7F23 H6 GND B27 IO236NB7F22 L2 IO255NB7F23 F5 GND B3 IO236PB7F22 L1 IO255PB7F23 G5 GND C1 IO237NB7F22 L4 IO256NB7F23 F3 GND C2 IO237PB7F22 L3 IO256PB7F23 F4 GND C25 IO238NB7F22 L6 IO257NB7F23 H7 GND C26 IO238PB7F22 M6 IO257PB7F23 J7 GND C27 IO239NB7F22 M8 GND C3 IO239PB7F22 M7 GND A1 GND E27 IO240NB7F22 K2 GND A2 GND L11 IO240PB7F22 K1 GND A25 GND L12 IO241NB7F22 K4 GND A26 GND L13 IO241PB7F22 K3 GND A27 GND L14 IO242NB7F22 K5 GND A3 GND L15 IO242PB7F22 L5 GND AC24 GND L16 Dedicated I/O v2.3 3-9 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND L17 GND U13 VCCPLG AB13 GND M11 GND U14 VCCPLH AG13 GND M12 GND U15 VCCDA A11 GND M13 GND U16 VCCDA AB12 GND M14 GND U17 VCCDA AC12 GND M15 GND/LP J8 VCCDA AC25 GND M16 NC U3 VCCDA AD16 GND M17 PRA J14 VCCDA AD17 GND N11 PRB D14 VCCDA E16 GND N12 PRC V14 VCCDA E2 GND N13 PRD AB14 VCCDA E24 GND N14 TCK E4 VCCDA F12 GND N15 TDI D4 VCCDA F16 GND N16 TDO J9 VCCDA F7 GND N17 TMS H8 VCCDA K14 GND P11 TRST E3 VCCDA P10 GND P12 VCCA AA21 VCCDA P18 GND P13 VCCA AD5 VCCDA W14 GND P14 VCCA E1 VCCDA W9 GND P15 VCCA G22 VCCIB0 A4 GND P16 VCCA K10 VCCIB0 B4 GND P17 VCCA K11 VCCIB0 C4 GND R11 VCCA K17 VCCIB0 J10 GND R12 VCCA K18 VCCIB0 J11 GND R13 VCCA L10 VCCIB0 J12 GND R14 VCCA L18 VCCIB0 K12 GND R15 VCCA U10 VCCIB0 K13 GND R16 VCCA U18 VCCIB1 A24 GND R17 VCCA V10 VCCIB1 B24 GND T11 VCCA V11 VCCIB1 C24 GND T12 VCCA V17 VCCIB1 J16 GND T13 VCCA V18 VCCIB1 J17 GND T14 VCCPLA A13 VCCIB1 J18 GND T15 VCCPLB J13 VCCIB1 K15 GND T16 VCCPLC B15 VCCIB1 K16 GND T17 VCCPLD C15 VCCIB2 D25 GND U11 VCCPLE AG14 VCCIB2 D26 GND U12 VCCPLF AF14 VCCIB2 D27 3 -1 0 v2.3 Axcelerator Family FPGAs 729-Pin PBGA 729-Pin PBGA AX1000 Function Pin Number AX1000 Function Pin Number VCCIB2 K19 VCCIB7 D2 VCCIB2 L19 VCCIB7 D3 VCCIB2 M18 VCCIB7 K9 VCCIB2 M19 VCCIB7 L9 VCCIB2 N18 VCCIB7 M10 VCCIB3 AD25 VCCIB7 M9 VCCIB3 AD26 VCCIB7 N10 VCCIB3 AD27 VCOMPLA B13 VCCIB3 R18 VCOMPLB A14 VCCIB3 T18 VCOMPLC A15 VCCIB3 T19 VCOMPLD J15 VCCIB3 U19 VCOMPLE AG15 VCCIB3 V19 VCOMPLF W15 VCCIB4 AE24 VCOMPLG AC14 VCCIB4 AF24 VCOMPLH W13 VCCIB4 AG24 VPUMP D24 VCCIB4 V15 VCCIB4 V16 VCCIB4 W16 VCCIB4 W17 VCCIB4 W18 VCCIB5 AE4 VCCIB5 AF4 VCCIB5 AG4 VCCIB5 V12 VCCIB5 V13 VCCIB5 W10 VCCIB5 W11 VCCIB5 W12 VCCIB6 AD1 VCCIB6 AD2 VCCIB6 AD3 VCCIB6 R10 VCCIB6 T10 VCCIB6 T9 VCCIB6 U9 VCCIB6 V9 VCCIB7 D1 v2.3 3-11 Axcelerator Family FPGAs 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Figure 3-3 * 256-Pin FBGA (Bottom View) 3 -1 2 v2.3 Axcelerator Family FPGAs 256-Pin FBGA 256-Pin FBGA AX125 Function Pin Number Bank 0 256-Pin FBGA AX125 Function Pin Number AX125 Function Pin Number IO21PB2F2 B16 IO44PB4F4 T15 IO01NB0F0 B4 IO22NB2F2 H13 IO45NB4F4 R12 IO01PB0F0 B3 IO22PB2F2 G13 IO45PB4F4 R13 IO03NB0F0 A4 IO23NB2F2 E16 IO46NB4F4 P11 IO03PB0F0 A3 IO23PB2F2 D16 IO46PB4F4 P12 IO04NB0F0 B6 IO25NB2F2 H15 IO47PB4F4 T11 IO04PB0F0 B5 IO25PB2F2 G15 IO48NB4F4 T12 IO06NB0F0 A6 IO26NB2F2 H14 IO48PB4F4 T13 IO06PB0F0 A5 IO26PB2F2 G14 IO49NB4F4/CLKEN R9 IO07NB0F0/HCLKAN B8 IO27NB2F2 G16 IO49PB4F4/CLKEP R10 IO07PB0F0/HCLKAP B7 IO27PB2F2 F16 IO50NB4F4/CLKFN T8 IO08NB0F0/HCLKBN A9 IO28NB2F2 K15 IO50PB4F4/CLKFP T9 IO08PB0F0/HCLKBP A8 IO28PB2F2 K16 IO29NB2F2 J16 IO51NB5F5/CLKGN P7 IO29PB2F2 H16 IO51PB5F5/CLKGP P8 IO52NB5F5/CLKHN R6 Bank 1 Bank 5 IO09NB1F1/HCLKCN C10 IO09PB1F1/HCLKCP C9 IO10NB1F1/HCLKDN B11 IO30NB3F3 K13 IO52PB5F5/CLKHP R7 IO10PB1F1/HCLKDP B10 IO30PB3F3 J13 IO54NB5F5 T5 IO12NB1F1 A13 IO31NB3F3 K14 IO54PB5F5 T6 IO12PB1F1 A12 IO31PB3F3 J14 IO55NB5F5 P5 IO13NB1F1 B13 IO33NB3F3 L15 IO55PB5F5 P6 IO13PB1F1 B12 IO33PB3F3 L16 IO56NB5F5 T3 IO14NB1F1 C12 IO35NB3F3 P16 IO56PB5F5 T4 IO14PB1F1 C11 IO35PB3F3 N16 IO57NB5F5 R3 IO15NB1F1 A15 IO36PB3F3 M16 IO57PB5F5 R4 IO15PB1F1 B14 IO37NB3F3 P15 IO58NB5F5 R1 IO16NB1F1 C15 IO37PB3F3 R16 IO58PB5F5 T2 IO16PB1F1 C14 IO39NB3F3 N15 IO59NB5F5 N4 IO17NB1F1 D13 IO39PB3F3 M15 IO59PB5F5 N5 IO17PB1F1 D12 IO40NB3F3 M13 IO40PB3F3 L13 IO60NB6F6 L4 Bank 2 Bank 3 Bank 6 IO18NB2F2 F13 IO41NB3F3 M14 IO60PB6F6 M4 IO18PB2F2 E13 IO41PB3F3 L14 IO61NB6F6 L3 IO19NB2F2 F14 IO61PB6F6 M3 IO19PB2F2 E14 IO42NB4F4 N12 IO63NB6F6 P2 IO20NB2F2 F15 IO42PB4F4 N13 IO63PB6F6 N2 IO20PB2F2 E15 IO43NB4F4 T14 IO64NB6F6 J4 IO21NB2F2 C16 IO43PB4F4 R14 IO64PB6F6 K4 Bank 4 v2.3 3-13 Axcelerator Family FPGAs 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA AX125 Function Pin Number AX125 Function Pin Number AX125 Function Pin Number IO65NB6F6 N1 GND D15 PRD P9 IO65PB6F6 P1 GND E12 TCK D5 IO67NB6F6 L2 GND E5 TDI C6 IO67PB6F6 M2 GND F11 TDO C4 IO69NB6F6 L1 GND F6 TMS C3 IO69PB6F6 M1 GND G10 TRST C5 IO70NB6F6 J3 GND G7 VCCA D14 IO70PB6F6 K3 GND G8 VCCA F10 IO71NB6F6 J2 GND G9 VCCA F4 IO71PB6F6 K2 GND H10 VCCA F7 GND H7 VCCA F8 Bank 7 IO72NB7F7 J1 GND H8 VCCA F9 IO72PB7F7 K1 GND H9 VCCA G11 IO73NB7F7 G2 GND J10 VCCA G6 IO73PB7F7 H2 GND J7 VCCA H11 IO74NB7F7 G3 GND J8 VCCA H6 IO74PB7F7 H3 GND J9 VCCA J11 IO75NB7F7 E1 GND K10 VCCA J6 IO75PB7F7 F1 GND K7 VCCA K11 IO76NB7F7 G1 GND K8 VCCA K6 IO77NB7F7 E2 GND K9 VCCA L10 IO77PB7F7 F2 GND L11 VCCA L7 IO78NB7F7 G4 GND L6 VCCA L8 IO78PB7F7 H4 GND M12 VCCA L9 IO79NB7F7 C1 GND M5 VCCA N3 IO79PB7F7 D1 GND P13 VCCA P14 IO81NB7F7 C2 GND P3 VCCPLA C7 IO81PB7F7 B1 GND R15 VCCPLB D6 IO82NB7F7 D2 GND R2 VCCPLC A10 IO82PB7F7 D3 GND T1 VCCPLD D10 IO83NB7F7 E3 GND T16 VCCPLE P10 IO83PB7F7 F3 GND/LP D4 VCCPLF N11 NC A11 VCCPLG T7 Dedicated I/O 3 -1 4 VCCDA E4 NC R11 VCCPLH N7 GND A1 NC R5 VCCDA A2 GND A16 PRA D8 VCCDA C13 GND B15 PRB C8 VCCDA D9 GND B2 PRC N9 VCCDA H1 v2.3 Axcelerator Family FPGAs 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA AX250 Function Pin Number IO33PB2F2 E15 B4 IO35NB2F2 H13 IO01PB0F0 B3 IO35PB2F2 G13 P4 IO03NB0F0 A4 IO36NB2F2 E16 VCCIB0 E6 IO03PB0F0 A3 IO36PB2F2 D16 VCCIB0 E7 IO05NB0F0 B6 IO38NB2F2 H15 VCCIB0 E8 IO05PB0F0 B5 IO38PB2F2 G15 VCCIB1 E10 IO07NB0F0 A6 IO39NB2F2 H14 VCCIB1 E11 IO07PB0F0 A5 IO39PB2F2 G14 VCCIB1 E9 IO12NB0F0/HCLKAN B8 IO40NB2F2 G16 VCCIB2 F12 IO12PB0F0/HCLKAP B7 IO40PB2F2 F16 VCCIB2 G12 IO13NB0F0/HCLKBN A9 IO43NB2F2 K15 VCCIB2 H12 IO13PB0F0/HCLKBP A8 IO43PB2F2 K16 VCCIB3 J12 IO44NB2F2 J16 VCCIB3 K12 IO14NB1F1/HCLKCN C10 IO44PB2F2 H16 VCCIB3 L12 IO14PB1F1/HCLKCP C9 VCCIB4 M10 IO15NB1F1/HCLKDN B11 IO45NB3F3 K13 VCCIB4 M11 IO15PB1F1/HCLKDP B10 IO45PB3F3 J13 VCCIB4 M9 IO17NB1F1 A13 IO46NB3F3 K14 VCCIB5 M6 IO17PB1F1 A12 IO46PB3F3 J14 VCCIB5 M7 IO19NB1F1 B13 IO52NB3F3 L15 VCCIB5 M8 IO19PB1F1 B12 IO52PB3F3 L16 VCCIB6 J5 IO21NB1F1 C12 IO54NB3F3 P16 VCCIB6 K5 IO21PB1F1 C11 IO54PB3F3 N16 VCCIB6 L5 IO23NB1F1 A15 IO55PB3F3 M16 VCCIB7 F5 IO23PB1F1 B14 IO56NB3F3 P15 VCCIB7 G5 IO26NB1F1 C15 IO56PB3F3 R16 VCCIB7 H5 IO26PB1F1 C14 IO58NB3F3 N15 VCOMPLA A7 IO27NB1F1 D13 IO58PB3F3 M15 VCOMPLB D7 IO27PB1F1 D12 IO59NB3F3 M13 VCOMPLC B9 IO59PB3F3 L13 VCOMPLD D11 IO29NB2F2 F13 IO61NB3F3 M14 VCOMPLE T10 IO29PB2F2 E13 IO61PB3F3 L14 VCOMPLF N10 IO30NB2F2 F14 VCOMPLG R8 IO30PB2F2 E14 IO62NB4F4 N12 VCOMPLH N6 IO32NB2F2 C16 IO62PB4F4 N13 VPUMP A14 IO32PB2F2 B16 IO63NB4F4 T14 IO33NB2F2 F15 IO63PB4F4 R14 AX125 Function Pin Number VCCDA J15 VCCDA N14 IO01NB0F0 VCCDA N8 VCCDA AX250 Function Pin Number Bank 0 Bank 1 Bank 2 v2.3 Bank 3 Bank 4 3-15 Axcelerator Family FPGAs 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA AX250 Function Pin Number AX250 Function Pin Number AX250 Function Pin Number IO66PB4F4 T15 IO98NB6F6 N1 GND D15 IO67NB4F4 R12 IO98PB6F6 P1 GND E12 IO67PB4F4 R13 IO100NB6F6 L2 GND E5 IO69NB4F4 P11 IO100PB6F6 M2 GND F11 IO69PB4F4 P12 IO102NB6F6 L1 GND F6 IO70PB4F4 T11 IO102PB6F6 M1 GND G10 IO73NB4F4 T12 IO103NB6F6 J3 GND G7 IO73PB4F4 T13 IO103PB6F6 K3 GND G8 IO74NB4F4/CLKEN R9 IO104NB6F6 J2 GND G9 IO74PB4F4/CLKEP R10 IO104PB6F6 K2 GND H10 IO75NB4F4/CLKFN T8 GND H7 IO75PB4F4/CLKFP T9 Bank 5 Bank 7 IO107NB7F7 J1 GND H8 IO107PB7F7 K1 GND H9 IO76NB5F5/CLKGN P7 IO108NB7F7 G2 GND J10 IO76PB5F5/CLKGP P8 IO108PB7F7 H2 GND J7 IO77NB5F5/CLKHN R6 IO111NB7F7 G3 GND J8 IO77PB5F5/CLKHP R7 IO111PB7F7 H3 GND J9 IO79NB5F5 T5 IO112NB7F7 E1 GND K10 IO79PB5F5 T6 IO112PB7F7 F1 GND K7 IO81NB5F5 P5 IO113NB7F7 G1 GND K8 IO81PB5F5 P6 IO114NB7F7 E2 GND K9 IO83NB5F5 T3 IO114PB7F7 F2 GND L11 IO83PB5F5 T4 IO115NB7F7 G4 GND L6 IO85NB5F5 R3 IO115PB7F7 H4 GND M12 IO85PB5F5 R4 IO116NB7F7 C1 GND M5 IO88NB5F5 R1 IO116PB7F7 D1 GND P13 IO88PB5F5 T2 IO117NB7F7 C2 GND P3 IO89NB5F5 N4 IO117PB7F7 B1 GND R15 IO89PB5F5 N5 IO118NB7F7 D2 GND R2 IO118PB7F7 D3 GND T1 Bank 6 3 -1 6 IO91NB6F6 L4 IO119NB7F7 E3 GND T16 IO91PB6F6 M4 IO119PB7F7 F3 GND/LP D4 IO92NB6F6 L3 PRA D8 IO92PB6F6 M3 VCCDA E4 PRB C8 IO94NB6F6 P2 GND A1 PRC N9 IO94PB6F6 N2 GND A16 PRD P9 IO97NB6F6 J4 GND B15 TCK D5 IO97PB6F6 K4 GND B2 TDI C6 Dedicated I/O v2.3 Axcelerator Family FPGAs 256-Pin FBGA 256-Pin FBGA AX250 Function Pin Number AX250 Function Pin Number TDO C4 VCCDA N8 TMS C3 VCCDA P4 TRST C5 VCCDA R11 VCCA D14 VCCDA R5 VCCA F10 VCCIB0 E6 VCCA F4 VCCIB0 E7 VCCA F7 VCCIB0 E8 VCCA F8 VCCIB1 E10 VCCA F9 VCCIB1 E11 VCCA G11 VCCIB1 E9 VCCA G6 VCCIB2 F12 VCCA H11 VCCIB2 G12 VCCA H6 VCCIB2 H12 VCCA J11 VCCIB3 J12 VCCA J6 VCCIB3 K12 VCCA K11 VCCIB3 L12 VCCA K6 VCCIB4 M10 VCCA L10 VCCIB4 M11 VCCA L7 VCCIB4 M9 VCCA L8 VCCIB5 M6 VCCA L9 VCCIB5 M7 VCCA N3 VCCIB5 M8 VCCA P14 VCCIB6 J5 VCCPLA C7 VCCIB6 K5 VCCPLB D6 VCCIB6 L5 VCCPLC A10 VCCIB7 F5 VCCPLD D10 VCCIB7 G5 VCCPLE P10 VCCIB7 H5 VCCPLF N11 VCOMPLA A7 VCCPLG T7 VCOMPLB D7 VCCPLH N7 VCOMPLC B9 VCCDA A11 VCOMPLD D11 VCCDA A2 VCOMPLE T10 VCCDA C13 VCOMPLF N10 VCCDA D9 VCOMPLG R8 VCCDA H1 VCOMPLH N6 VCCDA J15 VPUMP A14 VCCDA N14 v2.3 3-17 Axcelerator Family FPGAs 324-Pin FBGA A1 Ball Pad Corner 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V Figure 3-4 * 324-Pin FBGA (Bottom View) 3 -1 8 v2.3 Axcelerator Family FPGAs 324-Pin FBGA 324-Pin FBGA AX125 Function Pin Number Bank 0 AX125 Function 324-Pin FBGA Pin Number Bank 2 AX125 Function Pin Number IO36NB3F3 P16 IO00NB0F0 C5 IO18NB2F2 G14 IO36PB3F3 N16 IO00PB0F0 C4 IO18PB2F2 F14 IO37NB3F3 R17 IO01NB0F0 A3 IO19NB2F2 D16 IO37PB3F3 P17 IO01PB0F0 A2 IO19PB2F2 D15 IO38NB3F3 N14 IO02NB0F0 C7 IO20NB2F2 C18 IO38PB3F3 M14 IO02PB0F0 C6 IO20PB2F2 B18 IO39NB3F3 U18 IO03NB0F0 B5 IO21NB2F2 D17 IO39PB3F3 T18 IO03PB0F0 B4 IO21PB2F2 C17 IO40NB3F3 R16 IO04NB0F0 A5 IO22NB2F2 F17 IO40PB3F3 T17 IO04PB0F0 A4 IO22PB2F2 E17 IO41NB3F3 P13 IO05NB0F0 A7 IO23NB2F2 G16 IO41PB3F3 P14 IO05PB0F0 A6 IO23PB2F2 F16 IO06NB0F0 B7 IO24NB2F2 E18 IO42NB4F4 T13 IO06PB0F0 B6 IO24PB2F2 D18 IO42PB4F4 T14 IO07NB0F0/HCLKAN C9 IO25NB2F2 G18 IO43NB4F4 U15 IO07PB0F0/HCLKAP C8 IO25PB2F2 F18 IO43PB4F4 T15 IO08NB0F0/HCLKBN B10 IO26NB2F2 H17 IO44NB4F4 U13 IO08PB0F0/HCLKBP B9 IO26PB2F2 G17 IO44PB4F4 U14 IO27NB2F2 J16 IO45NB4F4 V15 Bank 1 Bank 4 IO09NB1F1/HCLKCN D11 IO27PB2F2 H16 IO45PB4F4 V16 IO09PB1F1/HCLKCP D10 IO28NB2F2 J18 IO46NB4F4 V13 IO10NB1F1/HCLKDN C12 IO28PB2F2 H18 IO46PB4F4 V14 IO10PB1F1/HCLKDP C11 IO29NB2F2 K17 IO47NB4F4 V12 IO11NB1F1 A15 IO29PB2F2 J17 IO47PB4F4 U12 IO11PB1F1 A14 IO48NB4F4 V10 IO12NB1F1 B14 IO30NB3F3 N18 IO48PB4F4 V11 IO12PB1F1 B13 IO30PB3F3 M18 IO49NB4F4/CLKEN T10 IO13NB1F1 A17 IO31NB3F3 L18 IO49PB4F4/CLKEP T11 IO13PB1F1 A16 IO31PB3F3 K18 IO50NB4F4/CLKFN U9 IO14NB1F1 D13 IO32NB3F3 L16 IO50PB4F4/CLKFP U10 IO14PB1F1 D12 IO32PB3F3 L17 IO15NB1F1 C14 IO33NB3F3 R18 IO51NB5F5/CLKGN R8 IO15PB1F1 C13 IO33PB3F3 P18 IO51PB5F5/CLKGP R9 IO16NB1F1 B16 IO34NB3F3 N15 IO52NB5F5/CLKHN T7 IO16PB1F1 C15 IO34PB3F3 M15 IO52PB5F5/CLKHP T8 IO17NB1F1 E14 IO35NB3F3 M16 IO53NB5F5 U6 IO17PB1F1 E13 IO35PB3F3 M17 IO53PB5F5 U7 Bank 3 v2.3 Bank 5 3-19 Axcelerator Family FPGAs 324-Pin FBGA AX125 Function Pin Number AX125 Function Pin Number AX125 Function Pin Number IO54NB5F5 V8 IO72NB7F7 H4 GND H11 IO54PB5F5 V9 IO72PB7F7 J4 GND H8 IO55NB5F5 V6 IO73NB7F7 K2 GND H9 IO55PB5F5 V7 IO73PB7F7 L2 GND J10 IO56NB5F5 U4 IO74NB7F7 H2 GND J11 IO56PB5F5 U5 IO74PB7F7 H1 GND J8 IO57NB5F5 T4 IO75NB7F7 H3 GND J9 IO57PB5F5 T5 IO75PB7F7 J3 GND K10 IO58NB5F5 V4 IO76NB7F7 F2 GND K11 IO58PB5F5 V5 IO76PB7F7 G2 GND K8 IO59NB5F5 V2 IO77NB7F7 F1 GND K9 IO59PB5F5 V3 IO77PB7F7 G1 GND L10 IO78NB7F7 D2 GND L11 Bank 6 IO60NB6F6 P5 IO78PB7F7 E2 GND L8 IO60PB6F6 P6 IO79NB7F7 F3 GND L9 IO61NB6F6 T2 IO79PB7F7 G3 GND M12 IO61PB6F6 U3 IO80NB7F7 E3 GND M7 IO62NB6F6 T1 IO80PB7F7 E4 GND N13 IO62PB6F6 U1 IO81NB7F7 D1 GND N6 IO63NB6F6 P1 IO81PB7F7 E1 GND R14 IO63PB6F6 R1 IO82NB7F7 D3 GND R4 IO64NB6F6 R3 IO82PB7F7 C2 GND T16 IO64PB6F6 P3 IO83NB7F7 B1 GND T3 IO65NB6F6 P2 IO83PB7F7 C1 GND U17 IO65PB6F6 R2 GND U2 IO66NB6F6 M3 VCCDA F5 GND V1 IO66PB6F6 N3 GND A1 GND V18 IO67NB6F6 M2 GND A18 GND/LP E5 IO67PB6F6 N2 GND B17 NC A10 IO68NB6F6 M1 GND B2 NC A11 IO68PB6F6 N1 GND C16 NC A12 IO69NB6F6 K4 GND C3 NC A13 IO69PB6F6 L4 GND E16 NC A8 IO70NB6F6 K1 GND F13 NC A9 IO70PB6F6 L1 GND F6 NC B12 IO71NB6F6 K3 GND G12 NC F15 IO71PB6F6 L3 GND G7 NC F4 GND H10 NC G15 Bank 7 3 -2 0 324-Pin FBGA 324-Pin FBGA Dedicated I/O v2.3 Axcelerator Family FPGAs 324-Pin FBGA AX125 Function 324-Pin FBGA 324-Pin FBGA Pin Number AX125 Function Pin Number AX125 Function Pin Number NC G4 VCCA G11 VCCIB1 F11 NC H14 VCCA G5 VCCIB1 F12 NC H15 VCCA G8 VCCIB2 G13 NC H5 VCCA G9 VCCIB2 H13 NC J1 VCCA H12 VCCIB2 J13 NC J14 VCCA H7 VCCIB3 K13 NC J15 VCCA J12 VCCIB3 L13 NC J5 VCCA J7 VCCIB3 M13 NC K14 VCCA K12 VCCIB4 N10 NC K15 VCCA K7 VCCIB4 N11 NC K5 VCCA L12 VCCIB4 N12 NC L14 VCCA L7 VCCIB5 N7 NC L15 VCCA M10 VCCIB5 N8 NC L5 VCCA M11 VCCIB5 N9 NC M4 VCCA M8 VCCIB6 K6 NC M5 VCCA M9 VCCIB6 L6 NC N17 VCCA P4 VCCIB6 M6 NC N4 VCCA R15 VCCIB7 G6 NC N5 VCCPLA D8 VCCIB7 H6 NC R12 VCCPLB E7 VCCIB7 J6 NC R13 VCCPLC B11 VCOMPLA B8 NC R6 VCCPLD E11 VCOMPLB E8 NC R7 VCCPLE R11 VCOMPLC C10 NC T12 VCCPLF P12 VCOMPLD E12 NC T6 VCCPLG U8 VCOMPLE U11 NC U16 VCCPLH P8 VCOMPLF P11 NC V17 VCCDA B3 VCOMPLG T9 PRA E9 VCCDA D14 VCOMPLH P7 PRB D9 VCCDA E10 VPUMP B15 PRC P10 VCCDA J2 PRD R10 VCCDA K16 TCK E6 VCCDA P15 TDI D7 VCCDA P9 TDO D5 VCCDA R5 TMS D4 VCCIB0 F7 TRST D6 VCCIB0 F8 VCCA E15 VCCIB0 F9 VCCA G10 VCCIB1 F10 v2.3 3-21 Axcelerator Family FPGAs 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Figure 3-5 * 484-Pin FBGA (Bottom View) 3 -2 2 v2.3 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA AX250 Function Pin Number Bank 0 AX250 Function 484-Pin FBGA Pin Number AX250 Function Pin Number IO18NB1F1 A14 IO36PB2F2 F21 IO00NB0F0 D7 IO18PB1F1 A13 IO37NB2F2 K19 IO00PB0F0 D6 IO19NB1F1 A16 IO37PB2F2 J19 IO01NB0F0 E7 IO19PB1F1 A15 IO38NB2F2 J20 IO01PB0F0 E6 IO20NB1F1 B16 IO38PB2F2 H20 IO02NB0F0 C5 IO20PB1F1 B15 IO39NB2F2 L16 IO02PB0F0 C4 IO21NB1F1 C17 IO39PB2F2 K16 IO03NB0F0 C7 IO21PB1F1 C16 IO40NB2F2 J21 IO03PB0F0 C6 IO22NB1F1 F15 IO40PB2F2 H21 IO04NB0F0 E9 IO22PB1F1 F14 IO41NB2F2 L17 IO04PB0F0 E8 IO23NB1F1 D16 IO41PB2F2 K17 IO05NB0F0 D9 IO23PB1F1 D15 IO42NB2F2 J22 IO05PB0F0 D8 IO24NB1F1 E16 IO42PB2F2 H22 IO06NB0F0 B7 IO24PB1F1 E15 IO43NB2F2 L18 IO06PB0F0 B6 IO25NB1F1 F18 IO43PB2F2 K18 IO07NB0F0 C9 IO25PB1F1 F17 IO44NB2F2 L20 IO07PB0F0 C8 IO26NB1F1 D18 IO44PB2F2 K20 IO08NB0F0 A7 IO26PB1F1 E17 IO08PB0F0 A6 IO27NB1F1 G16 IO45NB3F3 M19 IO09NB0F0 B9 IO27PB1F1 G15 IO45PB3F3 L19 IO09PB0F0 B8 IO46NB3F3 M21 IO10NB0F0 A9 IO28NB2F2 F19 IO46PB3F3 L21 IO10PB0F0 A8 IO28PB2F2 E19 IO47NB3F3 N17 IO11NB0F0 B10 IO29NB2F2 J16 IO47PB3F3 M17 IO11PB0F0 A10 IO29PB2F2 H16 IO48NB3F3 N18 IO12NB0F0/HCLKAN E11 IO30NB2F2 E20 IO48PB3F3 N19 IO12PB0F0/HCLKAP E10 IO30PB2F2 D20 IO49NB3F3 N16 IO13NB0F0/HCLKBN D12 IO31NB2F2 J17 IO49PB3F3 M16 IO13PB0F0/HCLKBP D11 IO31PB2F2 H17 IO50NB3F3 N20 IO32NB2F2 G20 IO50PB3F3 M20 Bank 1 Bank 2 Bank 3 IO14NB1F1/HCLKCN F13 IO32PB2F2 F20 IO51NB3F3 P21 IO14PB1F1/HCLKCP F12 IO33NB2F2 H19 IO51PB3F3 N21 IO15NB1F1/HCLKDN E14 IO33PB2F2 G19 IO52NB3F3 P18 IO15PB1F1/HCLKDP E13 IO34NB2F2 E22 IO52PB3F3 P19 IO16NB1F1 C13 IO34PB2F2 D22 IO53NB3F3 R20 IO16PB1F1 C12 IO35NB2F2 J18 IO53PB3F3 P20 IO17NB1F1 B14 IO35PB2F2 H18 IO54NB3F3 T21 IO17PB1F1 B13 IO36NB2F2 G21 IO54PB3F3 R21 v2.3 3-23 Axcelerator Family FPGAs 484-Pin FBGA AX250 Function 484-Pin FBGA Pin Number Pin Number AX250 Function Pin Number IO55NB3F3 R17 IO73PB4F4 AB13 IO91PB6F6 R7 IO55PB3F3 P17 IO74NB4F4/CLKEN V12 IO92NB6F6 U5 IO56NB3F3 U20 IO74PB4F4/CLKEP V13 IO92PB6F6 T5 IO56PB3F3 T20 IO75NB4F4/CLKFN W11 IO93NB6F6 P6 IO57NB3F3 T18 IO75PB4F4/CLKFP W12 IO93PB6F6 R6 IO57PB3F3 R18 IO94NB6F6 T4 IO58NB3F3 U19 IO76NB5F5/CLKGN U10 IO94PB6F6 U4 IO58PB3F3 T19 IO76PB5F5/CLKGP U11 IO95NB6F6 P5 IO59NB3F3 R16 IO77NB5F5/CLKHN V9 IO95PB6F6 R5 IO59PB3F3 P16 IO77PB5F5/CLKHP V10 IO96NB6F6 T3 IO60NB3F3 W20 IO78NB5F5 AA9 IO96PB6F6 U3 IO60PB3F3 V20 IO78PB5F5 AA10 IO97NB6F6 P3 IO61NB3F3 U18 IO79NB5F5 AB9 IO97PB6F6 R3 IO61PB3F3 V19 IO79PB5F5 AB10 IO98NB6F6 R2 IO80NB5F5 AA7 IO98PB6F6 T2 Bank 4 3 -2 4 AX250 Function 484-Pin FBGA Bank 5 IO62NB4F4 T15 IO80PB5F5 AA8 IO99NB6F6 P4 IO62PB4F4 T16 IO81NB5F5 W8 IO99PB6F6 R4 IO63NB4F4 W17 IO81PB5F5 W9 IO100NB6F6 P1 IO63PB4F4 V17 IO82NB5F5 AB5 IO100PB6F6 R1 IO64NB4F4 V15 IO82PB5F5 AB6 IO101NB6F6 M7 IO64PB4F4 V16 IO83NB5F5 AA5 IO101PB6F6 N7 IO65NB4F4 Y19 IO83PB5F5 AA6 IO102NB6F6 N2 IO65PB4F4 W18 IO84NB5F5 U8 IO102PB6F6 P2 IO66NB4F4 AB18 IO84PB5F5 U9 IO103NB6F6 M6 IO66PB4F4 AB19 IO85NB5F5 Y6 IO103PB6F6 N6 IO67NB4F4 W15 IO85PB5F5 Y7 IO104NB6F6 M4 IO67PB4F4 W16 IO86NB5F5 W6 IO104PB6F6 N4 IO68NB4F4 U14 IO86PB5F5 W7 IO105NB6F6 M5 IO68PB4F4 U15 IO87NB5F5 Y4 IO105PB6F6 N5 IO69NB4F4 AA16 IO87PB5F5 Y5 IO106NB6F6 M3 IO69PB4F4 AA17 IO88NB5F5 V6 IO106PB6F6 N3 IO70NB4F4 AB14 IO88PB5F5 V7 IO70PB4F4 AB15 IO89NB5F5 T7 IO107NB7F7 M2 IO71NB4F4 Y14 IO89PB5F5 T8 IO107PB7F7 N1 IO71PB4F4 W14 IO108NB7F7 L3 IO72NB4F4 AA14 IO90NB6F6 V4 IO108PB7F7 L2 IO72PB4F4 AA15 IO90PB6F6 W5 IO109NB7F7 K2 IO73NB4F4 AA13 IO91NB6F6 P7 IO109PB7F7 K1 Bank 6 v2.3 Bank 7 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA AX250 Function Pin Number AX250 Function 484-Pin FBGA Pin Number AX250 Function Pin Number IO110NB7F7 K5 GND AA21 GND M22 IO110PB7F7 L5 GND AA22 GND N10 IO111NB7F7 K6 GND AB1 GND N11 IO111PB7F7 L6 GND AB11 GND N12 IO112NB7F7 K4 GND AB12 GND N13 IO112PB7F7 K3 GND AB2 GND P14 IO113NB7F7 K7 GND AB21 GND P9 IO113PB7F7 L7 GND AB22 GND R15 IO114NB7F7 H1 GND B1 GND R8 IO114PB7F7 J1 GND B2 GND U16 IO115NB7F7 H2 GND B21 GND U6 IO115PB7F7 J2 GND B22 GND V18 IO116NB7F7 H4 GND C20 GND V5 IO116PB7F7 J4 GND C3 GND W19 IO117NB7F7 H5 GND D19 GND W4 IO117PB7F7 J5 GND D4 GND Y20 IO118NB7F7 F2 GND E18 GND Y3 IO118PB7F7 G2 GND E5 GND/LP G7 IO119NB7F7 H6 GND G18 NC A17 IO119PB7F7 J6 GND H15 NC A18 IO120NB7F7 F1 GND H8 NC A19 IO120PB7F7 G1 GND J14 NC A4 IO121NB7F7 F4 GND J9 NC A5 IO121PB7F7 G4 GND K10 NC AA11 IO122NB7F7 G5 GND K11 NC AA12 IO122PB7F7 G6 GND K12 NC AA18 IO123NB7F7 F5 GND K13 NC AA19 IO123PB7F7 E4 GND L1 NC AA4 GND L10 NC AB16 Dedicated I/O VCCDA H7 GND L11 NC AB17 GND A1 GND L12 NC AB4 GND A11 GND L13 NC AB7 GND A12 GND L22 NC AB8 GND A2 GND M1 NC B11 GND A21 GND M10 NC B12 GND A22 GND M11 NC B17 GND AA1 GND M12 NC B18 GND AA2 GND M13 NC B19 v2.3 3-25 Axcelerator Family FPGAs 484-Pin FBGA AX250 Function 3 -2 6 484-Pin FBGA Pin Number AX250 Function 484-Pin FBGA Pin Number AX250 Function Pin Number NC B4 NC V3 VCCA N9 NC B5 NC W1 VCCA P10 NC C10 NC W2 VCCA P11 NC C11 NC W21 VCCA P12 NC C14 NC W22 VCCA P13 NC C15 NC W3 VCCA T6 NC C18 NC Y10 VCCA U17 NC C19 NC Y11 VCCPLA F10 NC D1 NC Y12 VCCPLB G9 NC D2 NC Y13 VCCPLC D13 NC D21 NC Y15 VCCPLD G13 NC D3 NC Y16 VCCPLE U13 NC E1 NC Y17 VCCPLF T14 NC E2 NC Y18 VCCPLG W10 NC E21 NC Y8 VCCPLH T10 NC E3 NC Y9 VCCDA D14 NC F22 PRA G11 VCCDA D5 NC F3 PRB F11 VCCDA F16 NC G22 PRC T12 VCCDA G12 NC G3 PRD U12 VCCDA L4 NC H3 TCK G8 VCCDA M18 NC J3 TDI F9 VCCDA T11 NC K21 TDO F7 VCCDA T17 NC K22 TMS F6 VCCDA U7 NC N22 TRST F8 VCCDA V14 NC P22 VCCA G17 VCCDA V8 NC R19 VCCA J10 VCCIB0 A3 NC R22 VCCA J11 VCCIB0 B3 NC T1 VCCA J12 VCCIB0 H10 NC T22 VCCA J13 VCCIB0 H11 NC U1 VCCA J7 VCCIB0 H9 NC U2 VCCA K14 VCCIB1 A20 NC U21 VCCA K9 VCCIB1 B20 NC U22 VCCA L14 VCCIB1 H12 NC V1 VCCA L9 VCCIB1 H13 NC V2 VCCA M14 VCCIB1 H14 NC V21 VCCA M9 VCCIB2 C21 NC V22 VCCA N14 VCCIB2 C22 v2.3 Axcelerator Family FPGAs 484-Pin FBGA AX250 Function 484-Pin FBGA 484-Pin FBGA Pin Number AX500 Function Pin Number Bank 0 AX500 Function Pin Number IO20PB0F1/HCLKBP D11 VCCIB2 J15 VCCIB2 K15 IO00NB0F0 E3 VCCIB2 L15 IO00PB0F0 D3 IO21NB1F2/HCLKCN F13 VCCIB3 M15 IO01NB0F0 E7 IO21PB1F2/HCLKCP F12 VCCIB3 N15 IO01PB0F0 E6 IO22NB1F2/HCLKDN E14 VCCIB3 P15 IO02NB0F0 C5 IO22PB1F2/HCLKDP E13 VCCIB3 Y21 IO02PB0F0 C4 IO24NB1F2 A14 VCCIB3 Y22 IO03NB0F0 D7 IO24PB1F2 A13 VCCIB4 AA20 IO03PB0F0 D6 IO25NB1F2 B14 VCCIB4 AB20 IO04NB0F0 B5 IO25PB1F2 B13 VCCIB4 R12 IO04PB0F0 B4 IO26NB1F2 C15 VCCIB4 R13 IO05NB0F0 C7 IO27NB1F2 A16 VCCIB4 R14 IO05PB0F0 C6 IO27PB1F2 A15 VCCIB5 AA3 IO06NB0F0 A5 IO28NB1F2 B16 VCCIB5 AB3 IO06PB0F0 A4 IO28PB1F2 B15 VCCIB5 R10 IO07NB0F0 A7 IO29NB1F2 D16 VCCIB5 R11 IO07PB0F0 A6 IO29PB1F2 D15 VCCIB5 R9 IO08NB0F0 B7 IO30NB1F2 A18 VCCIB6 M8 IO08PB0F0 B6 IO30PB1F2 A17 VCCIB6 N8 IO10NB0F0 B9 IO31NB1F2 F15 VCCIB6 P8 IO10PB0F0 B8 IO31PB1F2 F14 VCCIB6 Y1 IO11NB0F0 E9 IO32NB1F3 C17 VCCIB6 Y2 IO11PB0F0 E8 IO32PB1F3 C16 VCCIB7 C1 IO12NB0F1 D9 IO33NB1F3 E16 VCCIB7 C2 IO12PB0F1 D8 IO33PB1F3 E15 VCCIB7 J8 IO13NB0F1 C9 IO34NB1F3 B18 VCCIB7 K8 IO13PB0F1 C8 IO34PB1F3 B17 VCCIB7 L8 IO14NB0F1 A9 IO35NB1F3 B19 VCOMPLA D10 IO14PB0F1 A8 IO35PB1F3 A19 VCOMPLB G10 IO15NB0F1 B10 IO36NB1F3 C19 VCOMPLC E12 IO15PB0F1 A10 IO36PB1F3 C18 VCOMPLD G14 IO16NB0F1 B12 IO37NB1F3 F18 VCOMPLE W13 IO16PB0F1 B11 IO37PB1F3 F17 VCOMPLF T13 IO18NB0F1 C13 IO38NB1F3 D18 VCOMPLG V11 IO18PB0F1 C12 IO38PB1F3 E17 VCOMPLH T9 IO19NB0F1/HCLKAN E11 IO39NB1F3 E21 VPUMP D17 IO19PB0F1/HCLKAP E10 IO39PB1F3 D21 IO20NB0F1/HCLKBN D12 IO40NB1F3 E20 v2.3 Bank 1 3-27 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO40PB1F3 D20 IO60NB2F5 M21 IO79NB3F7 T18 IO41NB1F3 G16 IO60PB2F5 L21 IO79PB3F7 R18 IO41PB1F3 G15 IO61NB2F5 L16 IO80NB3F7 W20 IO61PB2F5 K16 IO80PB3F7 V20 Bank 2 3 -2 8 IO42NB2F4 F19 IO62NB2F5 M19 IO81NB3F7 U19 IO42PB2F4 E19 IO62PB2F5 L19 IO81PB3F7 T19 IO43NB2F4 J16 IO82NB3F7 U18 IO43PB2F4 H16 IO63NB3F6 N16 IO82PB3F7 V19 IO44NB2F4 E22 IO63PB3F6 M16 IO83NB3F7 R16 IO44PB2F4 D22 IO64NB3F6 P22 IO83PB3F7 P16 IO45NB2F4 H19 IO64PB3F6 N22 IO45PB2F4 G19 IO65NB3F6 N20 IO84NB4F8 AB18 IO46NB2F4 G22 IO65PB3F6 M20 IO84PB4F8 AB19 IO46PB2F4 F22 IO66NB3F6 P21 IO85NB4F8 T15 IO47NB2F4 J17 IO66PB3F6 N21 IO85PB4F8 T16 IO47PB2F4 H17 IO67NB3F6 N18 IO86NB4F8 AA18 IO48NB2F4 G20 IO67PB3F6 N19 IO86PB4F8 AA19 IO48PB2F4 F20 IO68NB3F6 T22 IO87NB4F8 W17 IO49NB2F4 J18 IO68PB3F6 R22 IO87PB4F8 V17 IO49PB2F4 H18 IO69NB3F6 N17 IO88NB4F8 Y19 IO50NB2F4 G21 IO69PB3F6 M17 IO88PB4F8 W18 IO50PB2F4 F21 IO70NB3F6 T21 IO89NB4F8 U14 IO51NB2F4 K19 IO70PB3F6 R21 IO89PB4F8 U15 IO51PB2F4 J19 IO71NB3F6 P18 IO90NB4F8 Y17 IO52NB2F5 J21 IO71PB3F6 P19 IO90PB4F8 Y18 IO52PB2F5 H21 IO72NB3F6 R20 IO91NB4F8 V15 IO53NB2F5 J20 IO72PB3F6 P20 IO91PB4F8 V16 IO53PB2F5 H20 IO73PB3F6 R19 IO92PB4F8 AB17 IO54NB2F5 J22 IO74NB3F7 V21 IO93NB4F8 Y15 IO54PB2F5 H22 IO74PB3F7 U21 IO93PB4F8 Y16 IO55NB2F5 L17 IO75NB3F7 V22 IO94NB4F9 AA16 IO55PB2F5 K17 IO75PB3F7 U22 IO94PB4F9 AA17 IO56NB2F5 K21 IO76NB3F7 U20 IO95NB4F9 AB14 IO56PB2F5 K22 IO76PB3F7 T20 IO95PB4F9 AB15 IO58NB2F5 L20 IO77NB3F7 R17 IO96NB4F9 W15 IO58PB2F5 K20 IO77PB3F7 P17 IO96PB4F9 W16 IO59NB2F5 L18 IO78NB3F7 W21 IO97NB4F9 AA13 IO59PB2F5 K18 IO78PB3F7 W22 IO97PB4F9 AB13 Bank 3 v2.3 Bank 4 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO98NB4F9 AA14 IO119NB5F11 AA4 IO139NB6F13 N2 IO98PB4F9 AA15 IO119PB5F11 AB4 IO139PB6F13 P2 IO100NB4F9 Y14 IO120NB5F11 Y4 IO140NB6F13 P3 IO100PB4F9 W14 IO120PB5F11 Y5 IO140PB6F13 R3 IO101NB4F9 Y12 IO121NB5F11 W6 IO141NB6F13 M6 IO101PB4F9 Y13 IO121PB5F11 W7 IO141PB6F13 N6 IO102NB4F9 AA11 IO122NB5F11 V3 IO142NB6F13 P1 IO102PB4F9 AA12 IO122PB5F11 W3 IO142PB6F13 R1 IO103NB4F9/CLKEN V12 IO123NB5F11 T7 IO143NB6F13 M5 IO103PB4F9/CLKEP V13 IO123PB5F11 T8 IO143PB6F13 N5 IO104NB4F9/CLKFN W11 IO124NB5F11 V4 IO144NB6F13 M4 IO104PB4F9/CLKFP W12 IO124PB5F11 W5 IO144PB6F13 N4 IO125NB5F11 V6 IO145NB6F13 M7 IO125PB5F11 V7 IO145PB6F13 N7 IO146NB6F13 M3 IO146PB6F13 N3 Bank 5 IO105NB5F10/CLKGN U10 IO105PB5F10/CLKGP U11 IO106NB5F10/CLKHN V9 IO126NB6F12 V2 IO106PB5F10/CLKHP V10 IO126PB6F12 W2 IO107NB5F10 Y10 IO127NB6F12 P7 IO147NB7F14 K7 IO107PB5F10 Y11 IO127PB6F12 R7 IO147PB7F14 L7 IO108NB5F10 AA9 IO128NB6F12 V1 IO148NB7F14 M2 IO108PB5F10 AA10 IO128PB6F12 W1 IO148PB7F14 N1 IO110NB5F10 AB9 IO129NB6F12 U5 IO149NB7F14 K5 IO110PB5F10 AB10 IO129PB6F12 T5 IO149PB7F14 L5 IO111NB5F10 Y8 IO130NB6F12 T1 IO150NB7F14 L3 IO111PB5F10 Y9 IO130PB6F12 U1 IO150PB7F14 L2 IO112NB5F10 AB7 IO131NB6F12 P6 IO151NB7F14 K6 IO113NB5F10 W8 IO131PB6F12 R6 IO151PB7F14 L6 IO113PB5F10 W9 IO132NB6F12 T4 IO152NB7F14 K2 IO114NB5F11 AA7 IO132PB6F12 U4 IO152PB7F14 K1 IO114PB5F11 AA8 IO133NB6F12 U2 IO153NB7F14 K4 IO115NB5F11 AB5 IO134NB6F12 T3 IO153PB7F14 K3 IO115PB5F11 AB6 IO134PB6F12 U3 IO154NB7F14 H3 IO116NB5F11 Y6 IO135NB6F12 P5 IO154PB7F14 J3 IO116PB5F11 Y7 IO135PB6F12 R5 IO155NB7F14 H5 IO117NB5F11 U8 IO136NB6F13 R2 IO155PB7F14 J5 IO117PB5F11 U9 IO136PB6F13 T2 IO156NB7F14 H4 IO118NB5F11 AA5 IO138NB6F13 P4 IO156PB7F14 J4 IO118PB5F11 AA6 IO138PB6F13 R4 IO157NB7F14 H2 Bank 6 v2.3 Bank 7 3-29 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO157PB7F14 J2 GND AB22 GND R15 IO158NB7F15 H1 GND B1 GND R8 IO158PB7F15 J1 GND B2 GND U16 IO159NB7F15 F1 GND B21 GND U6 IO159PB7F15 G1 GND B22 GND V18 IO160NB7F15 F2 GND C20 GND V5 IO160PB7F15 G2 GND C3 GND W19 IO161NB7F15 H6 GND D19 GND W4 IO161PB7F15 J6 GND D4 GND Y20 IO162NB7F15 F3 GND E18 GND Y3 IO162PB7F15 G3 GND E5 GND/LP G7 IO163NB7F15 G5 GND G18 NC AB8 IO163PB7F15 G6 GND H15 NC AB16 IO164NB7F15 D1 GND H8 NC C10 IO164PB7F15 E1 GND J14 NC C11 IO165NB7F15 F4 GND J9 NC C14 IO165PB7F15 G4 GND K10 PRA G11 IO166NB7F15 D2 GND K11 PRB F11 IO166PB7F15 E2 GND K12 PRC T12 IO167NB7F15 F5 GND K13 PRD U12 IO167PB7F15 E4 GND L1 TCK G8 GND L10 TDI F9 Dedicated I/O 3 -3 0 VCCDA H7 GND L11 TDO F7 GND A1 GND L12 TMS F6 GND A11 GND L13 TRST F8 GND A12 GND L22 VCCA G17 GND A2 GND M1 VCCA J10 GND A21 GND M10 VCCA J11 GND A22 GND M11 VCCA J12 GND AA1 GND M12 VCCA J13 GND AA2 GND M13 VCCA J7 GND AA21 GND M22 VCCA K14 GND AA22 GND N10 VCCA K9 GND AB1 GND N11 VCCA L14 GND AB11 GND N12 VCCA L9 GND AB12 GND N13 VCCA M14 GND AB2 GND P14 VCCA M9 GND AB21 GND P9 VCCA N14 v2.3 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number VCCA N9 VCCIB2 J15 VCCA P10 VCCIB2 K15 VCCA P11 VCCIB2 L15 VCCA P12 VCCIB3 M15 VCCA P13 VCCIB3 N15 VCCA T6 VCCIB3 P15 VCCA U17 VCCIB3 Y21 VCCPLA F10 VCCIB3 Y22 VCCPLB G9 VCCIB4 AA20 VCCPLC D13 VCCIB4 AB20 VCCPLD G13 VCCIB4 R12 VCCPLE U13 VCCIB4 R13 VCCPLF T14 VCCIB4 R14 VCCPLG W10 VCCIB5 AA3 VCCPLH T10 VCCIB5 AB3 VCCDA D14 VCCIB5 R10 VCCDA D5 VCCIB5 R11 VCCDA F16 VCCIB5 R9 VCCDA G12 VCCIB6 M8 VCCDA L4 VCCIB6 N8 VCCDA M18 VCCIB6 P8 VCCDA T11 VCCIB6 Y1 VCCDA T17 VCCIB6 Y2 VCCDA U7 VCCIB7 C1 VCCDA V14 VCCIB7 C2 VCCDA V8 VCCIB7 J8 VCCIB0 A3 VCCIB7 K8 VCCIB0 B3 VCCIB7 L8 VCCIB0 H10 VCOMPLA D10 VCCIB0 H11 VCOMPLB G10 VCCIB0 H9 VCOMPLC E12 VCCIB1 A20 VCOMPLD G14 VCCIB1 B20 VCOMPLE W13 VCCIB1 H12 VCOMPLF T13 VCCIB1 H13 VCOMPLG V11 VCCIB1 H14 VCOMPLH T9 VCCIB2 C21 VPUMP D17 VCCIB2 C22 v2.3 3-31 Axcelerator Family FPGAs 484-Pin FBGA AX1000 Function 484-Pin FBGA Pin Number Bank 0 484-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number IO32PB1F3/HCLKCP F12 IO68NB2F6 J16 IO01NB0F0 E3 IO33NB1F3/HCLKDN E14 IO68PB2F6 H16 IO01PB0F0 D3 IO33PB1F3/HCLKDP E13 IO70NB2F6 J17 IO02NB0F0 E7 IO34NB1F3 C13 IO70PB2F6 H17 IO02PB0F0 E6 IO34PB1F3 C12 IO74NB2F7 J18 IO05NB0F0 D2 IO37NB1F3 B14 IO74PB2F7 H18 IO05PB0F0 E2 IO37PB1F3 B13 IO75NB2F7 G20 IO06NB0F0 C5 IO38NB1F3 A16 IO75PB2F7 F20 IO06PB0F0 C4 IO38PB1F3 A15 IO79NB2F7 H19 IO12NB0F1 D7 IO40NB1F3 C15 IO79PB2F7 G19 IO12PB0F1 D6 IO42NB1F4 A18 IO80NB2F7 L16 IO13NB0F1 B5 IO42PB1F4 A17 IO80PB2F7 K16 IO13PB0F1 B4 IO43NB1F4 B16 IO84NB2F7 L17 IO14NB0F1 E9 IO43PB1F4 B15 IO84PB2F7 K17 IO14PB0F1 E8 IO44NB1F4 B18 IO85NB2F8 G21 IO15NB0F1 C7 IO44PB1F4 B17 IO85PB2F8 F21 IO15PB0F1 C6 IO45NB1F4 B19 IO86NB2F8 G22 IO16NB0F1 A5 IO45PB1F4 A19 IO86PB2F8 F22 IO16PB0F1 A4 IO46NB1F4 C19 IO87NB2F8 J20 IO17NB0F1 B7 IO46PB1F4 C18 IO87PB2F8 H20 IO17PB0F1 B6 IO48NB1F4 F15 IO88NB2F8 L18 IO18NB0F1 A7 IO48PB1F4 F14 IO88PB2F8 K18 IO18PB0F1 A6 IO49NB1F4 D16 IO89NB2F8 K19 IO19NB0F1 C9 IO49PB1F4 D15 IO89PB2F8 J19 IO19PB0F1 C8 IO50NB1F4 C17 IO90NB2F8 J21 IO20NB0F1 D9 IO50PB1F4 C16 IO90PB2F8 H21 IO20PB0F1 D8 IO51NB1F4 E22 IO91NB2F8 J22 IO21NB0F1 B9 IO51PB1F4 D22 IO91PB2F8 H22 IO21PB0F1 B8 IO52NB1F4 E16 IO93NB2F8 K21 IO22NB0F2 A9 IO52PB1F4 E15 IO93PB2F8 K22 IO22PB0F2 A8 IO57NB1F5 E21 IO94NB2F8 L20 IO23NB0F2 B10 IO57PB1F5 D21 IO94PB2F8 K20 IO23PB0F2 A10 IO60NB1F5 G16 IO95NB2F8 M21 IO95PB2F8 L21 IO26NB0F2 A14 IO60PB1F5 G15 IO26PB0F2 A13 IO61NB1F5 D18 IO29NB0F2 B12 IO61PB1F5 E17 IO29PB0F2 B11 IO63NB1F5 E20 IO96PB3F9 M16 IO30NB0F2/HCLKAN E11 IO63PB1F5 D20 IO97NB3F9 M19 IO96NB3F9 N16 IO30PB0F2/HCLKAP E10 IO97PB3F9 L19 IO31NB0F2/HCLKBN D12 IO64NB2F6 F18 IO98NB3F9 P22 IO31PB0F2/HCLKBP D11 IO64PB2F6 F17 IO98PB3F9 N22 IO67NB2F6 F19 IO99NB3F9 N20 IO67PB2F6 E19 IO99PB3F9 M20 Bank 1 IO32NB1F3/HCLKCN 3 -3 2 F13 Bank 2 Bank 3 v2.3 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO100NB3F9 N17 IO140NB4F13 U18 IO171NB5F16 W8 IO100PB3F9 M17 IO140PB4F13 V19 IO171PB5F16 W9 IO101NB3F9 P21 IO142NB4F13 W20 IO172NB5F16 Y8 IO101PB3F9 N21 IO142PB4F13 V20 IO172PB5F16 Y9 IO103NB3F9 R20 IO143NB4F13 W15 IO173NB5F16 U8 IO103PB3F9 P20 IO143PB4F13 W16 IO173PB5F16 U9 IO104NB3F9 N18 IO144NB4F13 AA18 IO174NB5F16 AA7 IO104PB3F9 N19 IO144PB4F13 AA19 IO174PB5F16 AA8 IO105NB3F9 T22 IO145NB4F13 U14 IO175NB5F16 AB5 IO105PB3F9 R22 IO145PB4F13 U15 IO175PB5F16 AB6 IO106NB3F9 R17 IO146NB4F13 Y15 IO176NB5F16 AA5 IO106PB3F9 P17 IO146PB4F13 Y16 IO176PB5F16 AA6 IO107NB3F10 T21 IO147NB4F13 AB18 IO177NB5F16 AA4 IO107PB3F10 R21 IO147PB4F13 AB19 IO177PB5F16 AB4 IO110NB3F10 V22 IO149NB4F13 Y14 IO178NB5F16 Y6 IO110PB3F10 U22 IO149PB4F13 W14 IO178PB5F16 Y7 IO113NB3F10 V21 IO150NB4F13 AA16 IO179NB5F16 T7 IO113PB3F10 U21 IO150PB4F13 AA17 IO179PB5F16 T8 IO114NB3F10 P18 IO152NB4F14 AA14 IO180NB5F16 W6 IO114PB3F10 P19 IO152PB4F14 AA15 IO180PB5F16 W7 IO116PB3F10 R19 IO154NB4F14 AB14 IO181NB5F17 Y4 IO117NB3F10 U20 IO154PB4F14 AB15 IO181PB5F17 Y5 IO117PB3F10 T20 IO155NB4F14 AA13 IO184NB5F17 AB7 IO118NB3F11 T18 IO155PB4F14 AB13 IO187NB5F17 V3 IO118PB3F11 R18 IO158NB4F14 Y12 IO187PB5F17 W3 IO121NB3F11 U19 IO158PB4F14 Y13 IO188NB5F17 V4 IO121PB3F11 T19 IO159NB4F14/CLKEN V12 IO188PB5F17 W5 IO124NB3F11 R16 IO159PB4F14/CLKEP V13 IO192NB5F17 V6 IO192PB5F17 V7 IO124PB3F11 P16 IO160NB4F14/CLKFN W11 IO127NB3F11 W21 IO160PB4F14/CLKFP W12 IO127PB3F11 W22 Bank 4 Bank 5 Bank 6 IO194NB6F18 V2 IO161NB5F15/CLKGN U10 IO194PB6F18 W2 AB17 IO161PB5F15/CLKGP U11 IO195NB6F18 U5 IO132NB4F12 Y19 IO162NB5F15/CLKHN V9 IO195PB6F18 T5 IO132PB4F12 W18 IO162PB5F15/CLKHP V10 IO200NB6F18 T4 IO133NB4F12 W17 IO163NB5F15 Y10 IO200PB6F18 U4 IO133PB4F12 V17 IO163PB5F15 Y11 IO201NB6F18 P6 IO135NB4F12 T15 IO167NB5F15 AA11 IO201PB6F18 R6 IO129PB4F12 IO135PB4F12 T16 IO167PB5F15 AA12 IO203NB6F19 U2 IO138NB4F12 Y17 IO169NB5F15 AA9 IO204NB6F19 T3 IO138PB4F12 Y18 IO169PB5F15 AA10 IO204PB6F19 U3 IO139NB4F13 V15 IO170NB5F15 AB9 IO205NB6F19 P5 IO139PB4F13 V16 IO170PB5F15 AB10 IO205PB6F19 R5 v2.3 3-33 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO208NB6F19 V1 IO234NB7F21 F1 GND B2 IO208PB6F19 W1 IO234PB7F21 G1 GND B21 IO209NB6F19 P7 IO235NB7F21 F2 GND B22 IO209PB6F19 R7 IO235PB7F21 G2 GND C20 IO212NB6F19 P4 IO236NB7F22 H3 GND C3 IO212PB6F19 R4 IO236PB7F22 J3 GND D19 IO214NB6F20 P3 IO237NB7F22 K7 GND D4 IO214PB6F20 R3 IO237PB7F22 L7 GND E18 IO215NB6F20 M6 IO241NB7F22 H6 GND E5 IO215PB6F20 N6 IO241PB7F22 J6 GND G18 IO216NB6F20 R2 IO242NB7F22 H4 GND H15 IO216PB6F20 T2 IO242PB7F22 J4 GND H8 IO217NB6F20 T1 IO243NB7F22 H5 GND J14 IO217PB6F20 U1 IO243PB7F22 J5 GND J9 IO219NB6F20 M5 IO246NB7F22 F3 GND K10 IO219PB6F20 N5 IO246PB7F22 G3 GND K11 IO220NB6F20 P1 IO250NB7F23 F4 GND K12 IO220PB6F20 R1 IO250PB7F23 G4 GND K13 IO221NB6F20 N2 IO253NB7F23 G5 GND L1 IO221PB6F20 P2 IO253PB7F23 G6 GND L10 IO222NB6F20 M3 IO254NB7F23 D1 GND L11 IO222PB6F20 N3 IO254PB7F23 E1 GND L12 IO223NB6F20 M7 IO257NB7F23 F5 GND L13 IO257PB7F23 E4 GND L22 GND M1 H7 GND M10 IO223PB6F20 N7 IO224NB6F20 M4 IO224PB6F20 N4 VCCDA GND A1 GND M11 IO225NB7F21 M2 GND A11 GND M12 Bank 7 3 -3 4 Dedicated I/O IO225PB7F21 N1 GND A12 GND M13 IO226NB7F21 K2 GND A2 GND M22 IO226PB7F21 K1 GND A21 GND N10 IO228NB7F21 L3 GND A22 GND N11 IO228PB7F21 L2 GND AA1 GND N12 IO229NB7F21 K5 GND AA2 GND N13 IO229PB7F21 L5 GND AA21 GND P14 IO230NB7F21 H1 GND AA22 GND P9 IO230PB7F21 J1 GND AB1 GND R15 IO231NB7F21 H2 GND AB11 GND R8 IO231PB7F21 J2 GND AB12 GND U16 IO232NB7F21 K4 GND AB2 GND U6 IO232PB7F21 K3 GND AB21 GND V18 IO233NB7F21 K6 GND AB22 GND V5 IO233PB7F21 L6 GND B1 GND W19 v2.3 Axcelerator Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND W4 VCCDA C10 VCCIB5 R9 GND Y20 VCCDA C11 VCCIB6 M8 GND Y3 VCCDA C14 VCCIB6 N8 GND/LP G7 VCCDA D14 VCCIB6 P8 PRA G11 VCCDA D5 VCCIB6 Y1 PRB F11 VCCDA F16 VCCIB6 Y2 PRC T12 VCCDA G12 VCCIB7 C1 PRD U12 VCCDA L4 VCCIB7 C2 TCK G8 VCCDA M18 VCCIB7 J8 TDI F9 VCCDA T11 VCCIB7 K8 TDO F7 VCCDA T17 VCCIB7 L8 TMS F6 VCCDA U7 VCOMPLA D10 TRST F8 VCCDA V14 VCOMPLB G10 VCCA G17 VCCDA V8 VCOMPLC E12 VCCA J10 VCCIB0 A3 VCOMPLD G14 VCCA J11 VCCIB0 B3 VCOMPLE W13 VCCA J12 VCCIB0 H10 VCOMPLF T13 VCCA J13 VCCIB0 H11 VCOMPLG V11 VCCA J7 VCCIB0 H9 VCOMPLH T9 VCCA K14 VCCIB1 A20 VPUMP D17 VCCA K9 VCCIB1 B20 VCCA L14 VCCIB1 H12 VCCA L9 VCCIB1 H13 VCCA M14 VCCIB1 H14 VCCA M9 VCCIB2 C21 VCCA N14 VCCIB2 C22 VCCA N9 VCCIB2 J15 VCCA P10 VCCIB2 K15 VCCA P11 VCCIB2 L15 VCCA P12 VCCIB3 M15 VCCA P13 VCCIB3 N15 VCCA T6 VCCIB3 P15 VCCA U17 VCCIB3 Y21 VCCPLA F10 VCCIB3 Y22 VCCPLB G9 VCCIB4 AA20 VCCPLC D13 VCCIB4 AB20 VCCPLD G13 VCCIB4 R12 VCCPLE U13 VCCIB4 R13 VCCPLF T14 VCCIB4 R14 VCCPLG W10 VCCIB5 AA3 VCCPLH T10 VCCIB5 AB3 VCCDA AB16 VCCIB5 R10 VCCDA AB8 VCCIB5 R11 v2.3 3-35 Axcelerator Family FPGAs 676-Pin FBGA A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Figure 3-6 * 676-Pin FBGA (Bottom View) 3 -3 6 v2.3 Axcelerator Family FPGAs 676-Pin FBGA AX500 Function 676-Pin FBGA Pin Number 676-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number IO19NB0F1/HCLKAN A12 IO38NB1F3 B23 IO00NB0F0 F8 IO19PB0F1/HCLKAP B12 IO38PB1F3 A23 IO00PB0F0 E8 IO20NB0F1/HCLKBN C13 IO39NB1F3 E21 IO01NB0F0 A5 IO20PB0F1/HCLKBP B13 IO39PB1F3 E20 IO01PB0F0 A4 IO40NB1F3 D23 IO02NB0F0 E7 IO21NB1F2/HCLKCN C15 IO40PB1F3 C23 IO02PB0F0 E6 IO21PB1F2/HCLKCP C14 IO41NB1F3 D25 IO03NB0F0 D6 IO22NB1F2/HCLKDN A15 IO41PB1F3 C25 IO03PB0F0 D5 IO22PB1F2/HCLKDP B15 IO04NB0F0 B5 IO23NB1F2 F15 IO42NB2F4 G24 IO04PB0F0 C5 IO23PB1F2 G15 IO42PB2F4 G23 IO05NB0F0 B6 IO24NB1F2 B16 IO43NB2F4 G26 IO05PB0F0 C6 IO24PB1F2 A16 IO43PB2F4 F26 IO06NB0F0 C7 IO25NB1F2 A18 IO44NB2F4 F25 IO06PB0F0 D7 IO25PB1F2 A17 IO44PB2F4 E25 IO07NB0F0 A7 IO26NB1F2 D16 IO45NB2F4 J21 IO07PB0F0 A6 IO26PB1F2 E16 IO45PB2F4 J22 IO08NB0F0 C8 IO27NB1F2 F16 IO46NB2F4 H25 IO08PB0F0 D8 IO27PB1F2 G16 IO46PB2F4 G25 IO09NB0F0 F10 IO28NB1F2 C18 IO47NB2F4 K23 IO09PB0F0 F9 IO28PB1F2 C17 IO47PB2F4 J23 IO10NB0F0 B8 IO29NB1F2 B19 IO48NB2F4 J24 IO10PB0F0 B7 IO29PB1F2 B18 IO48PB2F4 H24 IO11NB0F0 D10 IO30NB1F2 D19 IO49NB2F4 K21 Bank 0 Bank 1 Bank 2 IO11PB0F0 E10 IO30PB1F2 C19 IO49PB2F4 K22 IO12NB0F1 B9 IO31NB1F2 F17 IO50NB2F4 K25 IO12PB0F1 C9 IO31PB1F2 E17 IO50PB2F4 J25 IO13NB0F1 F11 IO32NB1F3 B20 IO51NB2F4 L20 IO13PB0F1 G11 IO32PB1F3 A20 IO51PB2F4 L21 IO14NB0F1 D11 IO33NB1F3 B22 IO52NB2F5 K26 IO14PB0F1 E11 IO33PB1F3 B21 IO52PB2F5 J26 IO15NB0F1 B10 IO34NB1F3 D20 IO53NB2F5 L23 IO15PB0F1 C10 IO34PB1F3 C20 IO53PB2F5 L22 IO16NB0F1 A10 IO35NB1F3 D21 IO54NB2F5 L24 IO16PB0F1 A9 IO35PB1F3 C21 IO54PB2F5 K24 IO17NB0F1 F12 IO36NB1F3 D22 IO55NB2F5 M20 IO17PB0F1 G12 IO36PB1F3 C22 IO55PB2F5 M21 IO18NB0F1 C12 IO37NB1F3 F19 IO56NB2F5 L26 IO18PB0F1 C11 IO37PB1F3 E19 IO56PB2F5 L25 v2.3 3-37 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA AX500 Function Pin Number AX500 Function IO57NB2F5 M23 IO57PB2F5 M22 IO58NB2F5 Pin Number AX500 Function Pin Number IO76NB3F7 Y23 IO95NB4F9 AC17 IO76PB3F7 W23 IO95PB4F9 AC18 M26 IO77NB3F7 V21 IO96NB4F9 AD18 IO58PB2F5 M25 IO77PB3F7 U21 IO96PB4F9 AD19 IO59NB2F5 N22 IO78NB3F7 AB25 IO97NB4F9 AA16 IO59PB2F5 N23 IO78PB3F7 AA25 IO97PB4F9 Y16 IO60NB2F5 N24 IO79NB3F7 AC26 IO98NB4F9 AE17 IO60PB2F5 M24 IO79PB3F7 AB26 IO98PB4F9 AE18 IO61NB2F5 N20 IO80NB3F7 AC24 IO99NB4F9 AC16 IO61PB2F5 N21 IO80PB3F7 AB24 IO99PB4F9 AB16 IO62NB2F5 P25 IO81NB3F7 AB23 IO100NB4F9 AF17 IO62PB2F5 N25 IO81PB3F7 AA23 IO100PB4F9 AF18 IO82NB3F7 AA22 IO101NB4F9 AA15 Bank 3 3 -3 8 676-Pin FBGA IO63NB3F6 T26 IO82PB3F7 Y22 IO101PB4F9 Y15 IO63PB3F6 R26 IO83NB3F7 AE26 IO102NB4F9 AC15 IO64NB3F6 R24 IO83PB3F7 AD26 IO102PB4F9 AB15 IO64PB3F6 P24 IO103NB4F9/CLKEN AE16 IO65NB3F6 P20 IO84NB4F8 AB21 IO103PB4F9/CLKEP AF16 IO65PB3F6 P21 IO84PB4F8 AA21 IO104NB4F9/CLKFN AE14 IO66NB3F6 T25 IO85NB4F8 AE23 IO104PB4F9/CLKFP AE15 IO66PB3F6 R25 IO85PB4F8 AE24 IO67NB3F6 T23 IO86NB4F8 AC21 IO105NB5F10/CLKGN AE12 IO67PB3F6 R23 IO86PB4F8 AC22 IO105PB5F10/CLKGP AE13 IO68NB3F6 V26 IO87NB4F8 AF22 IO106NB5F10/CLKHN AE11 Bank 4 Bank 5 IO68PB3F6 U26 IO87PB4F8 AF23 IO106PB5F10/CLKHP AF11 IO69NB3F6 V25 IO88NB4F8 AD22 IO107NB5F10 Y12 IO69PB3F6 U25 IO88PB4F8 AD23 IO107PB5F10 AA13 IO70NB3F6 Y25 IO89NB4F8 AC19 IO108NB5F10 AC12 IO70PB3F6 W25 IO89PB4F8 AC20 IO108PB5F10 AB12 IO71NB3F6 W24 IO90NB4F8 AE21 IO109NB5F10 AC10 IO71PB3F6 V24 IO90PB4F8 AE22 IO109PB5F10 AC11 IO72NB3F6 V23 IO91NB4F8 AA17 IO110NB5F10 AF9 IO72PB3F6 U23 IO91PB4F8 AA18 IO110PB5F10 AF10 IO73NB3F6 T21 IO92NB4F8 AD20 IO111NB5F10 Y11 IO73PB3F6 T20 IO92PB4F8 AD21 IO111PB5F10 AA12 IO74NB3F7 AA26 IO93NB4F8 AF20 IO112NB5F10 AE9 IO74PB3F7 Y26 IO93PB4F8 AF21 IO112PB5F10 AE10 IO75NB3F7 AA24 IO94NB4F9 AE19 IO113NB5F10 AC9 IO75PB3F7 Y24 IO94PB4F9 AE20 IO113PB5F10 AD9 v2.3 Axcelerator Family FPGAs 676-Pin FBGA AX500 Function 676-Pin FBGA Pin Number AX500 Function IO114NB5F11 AF6 IO114PB5F11 AF7 IO115NB5F11 676-Pin FBGA Pin Number AX500 Function Pin Number IO133NB6F12 V4 IO152NB7F14 M5 IO133PB6F12 W4 IO152PB7F14 M4 AA10 IO134NB6F12 V3 IO153NB7F14 M7 IO115PB5F11 AB10 IO134PB6F12 W3 IO153PB7F14 M6 IO116NB5F11 AE7 IO135NB6F12 V1 IO154NB7F14 K2 IO116PB5F11 AE8 IO135PB6F12 V2 IO154PB7F14 L2 IO117NB5F11 AD7 IO136NB6F13 U4 IO155NB7F14 K3 IO117PB5F11 AD8 IO136PB6F13 U5 IO155PB7F14 L3 IO118NB5F11 AC7 IO137NB6F13 T6 IO156NB7F14 L5 IO118PB5F11 AC8 IO137PB6F13 T7 IO156PB7F14 L4 IO119NB5F11 AD6 IO138NB6F13 T5 IO157NB7F14 L6 IO119PB5F11 AE6 IO138PB6F13 T4 IO157PB7F14 L7 IO120NB5F11 AE5 IO139NB6F13 R6 IO158NB7F15 J1 IO120PB5F11 AF5 IO139PB6F13 R7 IO158PB7F15 K1 IO121NB5F11 AF4 IO140NB6F13 T3 IO159NB7F15 J4 IO121PB5F11 AE4 IO140PB6F13 U3 IO159PB7F15 K4 IO122NB5F11 AC5 IO141NB6F13 U1 IO160NB7F15 H2 IO122PB5F11 AC6 IO141PB6F13 U2 IO160PB7F15 J2 IO123NB5F11 AD4 IO142NB6F13 R2 IO161NB7F15 K6 IO123PB5F11 AD5 IO142PB6F13 T2 IO161PB7F15 K5 IO124NB5F11 AB6 IO143NB6F13 P3 IO162NB7F15 H3 IO124PB5F11 AB7 IO143PB6F13 R3 IO162PB7F15 J3 IO125NB5F11 AE3 IO144NB6F13 P5 IO163NB7F15 G2 IO125PB5F11 AF3 IO144PB6F13 P4 IO163PB7F15 G1 IO145NB6F13 P6 IO164NB7F15 G4 IO126NB6F12 Bank 6 AB3 IO145PB6F13 P7 IO164PB7F15 H4 IO126PB6F12 AC3 IO146NB6F13 R1 IO165NB7F15 F3 IO127NB6F12 AA2 IO146PB6F13 T1 IO165PB7F15 G3 IO127PB6F12 AB2 IO166NB7F15 E2 IO128NB6F12 AC2 IO147NB7F14 N6 IO166PB7F15 F2 IO128PB6F12 AD2 IO147PB7F14 N7 IO167NB7F15 F5 IO129NB6F12 Y1 IO148NB7F14 N5 IO167PB7F15 G5 IO129PB6F12 AA1 IO148PB7F14 N4 IO130NB6F12 Y3 IO149NB7F14 N2 GND A1 IO130PB6F12 AA3 IO149PB7F14 N3 GND A13 IO131NB6F12 U6 IO150NB7F14 L1 GND A14 IO131PB6F12 V6 IO150PB7F14 M1 GND A19 IO132NB6F12 W2 IO151NB7F14 M2 GND A26 IO132PB6F12 Y2 IO151PB7F14 M3 GND A8 Bank 7 v2.3 Dedicated I/O 3-39 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number GND AC23 GND L16 GND T11 GND AC4 GND L17 GND T12 GND AD24 GND M10 GND T13 GND AD3 GND M11 GND T14 GND AE2 GND M12 GND T15 GND AE25 GND M13 GND T16 GND AF1 GND M14 GND T17 GND AF13 GND M15 GND U10 GND AF14 GND M16 GND U11 GND AF19 GND M17 GND U12 GND AF26 GND N1 GND U13 GND AF8 GND N10 GND U14 GND B2 GND N11 GND U15 GND B25 GND N12 GND U16 GND B26 GND N13 GND U17 GND C24 GND N14 GND V18 GND C3 GND N15 GND V9 GND G20 GND N16 GND W1 GND G7 GND N17 GND W19 GND H1 GND N26 GND W26 GND H19 GND P1 GND W8 GND H26 GND P10 GND Y20 GND H8 GND P11 GND Y7 GND J18 GND P12 GND/LP C2 GND J9 GND P13 NC A11 GND K10 GND P14 NC A21 GND K11 GND P15 NC A22 GND K12 GND P16 NC A24 GND K13 GND P17 NC A25 GND K14 GND P26 NC AA11 GND K15 GND R10 NC AA19 GND K16 GND R11 NC AA20 GND K17 GND R12 NC AA4 GND L10 GND R13 NC AA5 GND L11 GND R14 NC AA6 GND L12 GND R15 NC AA7 GND L13 GND R16 NC AA8 GND L14 GND R17 NC AA9 GND L15 GND T10 NC AB1 3 -4 0 v2.3 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number NC AB11 NC E9 NC Y6 NC AB17 NC F1 PRA E13 NC AB18 NC F18 PRB B14 NC AB19 NC F20 PRC Y14 NC AB20 NC F21 PRD AD14 NC AB8 NC F22 TCK E5 NC AB9 NC F23 TDI B3 NC AC1 NC F24 TDO G6 NC AC13 NC F4 TMS D4 NC AC14 NC F6 TRST A2 NC AC25 NC F7 VCCA AB4 NC AD1 NC G21 VCCA AF24 NC AD11 NC G22 VCCA C1 NC AD16 NC H21 VCCA C26 NC AD25 NC H22 VCCA J10 NC AE1 NC H23 VCCA J11 NC AF2 NC H5 VCCA J12 NC AF25 NC H6 VCCA J13 NC B11 NC J5 VCCA J14 NC B24 NC J6 VCCA J15 NC B4 NC P22 VCCA J16 NC C16 NC R20 VCCA J17 NC C4 NC R21 VCCA K18 NC D1 NC R22 VCCA K9 NC D13 NC R4 VCCA L18 NC D14 NC R5 VCCA L9 NC D17 NC T22 VCCA M18 NC D18 NC T24 VCCA M9 NC D2 NC U22 VCCA N18 NC D26 NC U24 VCCA N9 NC D3 NC V22 VCCA P18 NC D9 NC V5 VCCA P9 NC E1 NC W21 VCCA R18 R9 NC E18 NC W22 VCCA NC E23 NC W5 VCCA T18 NC E24 NC W6 VCCA T9 NC E26 NC Y21 VCCA U18 NC E3 NC Y4 VCCA U9 NC E4 NC Y5 VCCA V10 v2.3 3-41 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number 3 -4 2 VCCA V11 VCCIB2 K20 VCCIB7 K7 VCCA V12 VCCIB2 L19 VCCIB7 K8 VCCA V13 VCCIB2 M19 VCCIB7 L8 VCCA V14 VCCIB2 N19 VCCIB7 M8 VCCA V15 VCCIB3 P19 VCCIB7 N8 VCCA V16 VCCIB3 R19 VCCPLA E12 VCCA V17 VCCIB3 T19 VCCPLB F13 VCCDA A3 VCCIB3 U19 VCCPLC E15 VCCDA AB22 VCCIB3 U20 VCCPLD G14 VCCDA AB5 VCCIB3 V19 VCCPLE AF15 VCCDA AD10 VCCIB3 V20 VCCPLF AA14 VCCDA AD13 VCCIB3 W20 VCCPLG AF12 VCCDA AD17 VCCIB4 W14 VCCPLH AB13 VCCDA B1 VCCIB4 W15 VCOMPLA D12 VCCDA B17 VCCIB4 W16 VCOMPLB G13 VCCDA D24 VCCIB4 W17 VCOMPLC D15 VCCDA E14 VCCIB4 W18 VCOMPLD F14 VCCDA P2 VCCIB4 Y17 VCOMPLE AD15 VCCDA P23 VCCIB4 Y18 VCOMPLF AB14 VCCIB0 G10 VCCIB4 Y19 VCOMPLG AD12 VCCIB0 G8 VCCIB5 W10 VCOMPLH Y13 VCCIB0 G9 VCCIB5 W11 VPUMP E22 VCCIB0 H10 VCCIB5 W12 VCCIB0 H11 VCCIB5 W13 VCCIB0 H12 VCCIB5 W9 VCCIB0 H13 VCCIB5 Y10 VCCIB0 H9 VCCIB5 Y8 VCCIB1 G17 VCCIB5 Y9 VCCIB1 G18 VCCIB6 P8 VCCIB1 G19 VCCIB6 R8 VCCIB1 H14 VCCIB6 T8 VCCIB1 H15 VCCIB6 U7 VCCIB1 H16 VCCIB6 U8 VCCIB1 H17 VCCIB6 V7 VCCIB1 H18 VCCIB6 V8 VCCIB2 H20 VCCIB6 W7 VCCIB2 J19 VCCIB7 H7 VCCIB2 J20 VCCIB7 J7 VCCIB2 K19 VCCIB7 J8 v2.3 Axcelerator Family FPGAs 676-Pin FBGA AX1000 Function 676-Pin FBGA Pin Number 676-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number IO24NB0F2 D11 IO51NB1F4 D19 IO00NB0F0 B4 IO24PB0F2 E11 IO51PB1F4 C19 IO00PB0F0 C4 IO26NB0F2 C12 IO52NB1F4 D20 IO02NB0F0 E7 IO26PB0F2 C11 IO52PB1F4 C20 IO02PB0F0 E6 IO28NB0F2 F12 IO54NB1F5 B22 IO03NB0F0 D6 IO28PB0F2 G12 IO54PB1F5 B21 IO03PB0F0 D5 IO30NB0F2/HCLKAN A12 IO55NB1F5 D21 IO04NB0F0 B5 IO30PB0F2/HCLKAP B12 IO55PB1F5 C21 IO04PB0F0 C5 IO31NB0F2/HCLKBN C13 IO56NB1F5 F19 IO05NB0F0 A5 IO31PB0F2/HCLKBP B13 IO05PB0F0 A4 IO06NB0F0 F7 IO32NB1F3/HCLKCN IO06PB0F0 F6 IO07NB0F0 Bank 0 IO56PB1F5 E19 IO57NB1F5 B23 C15 IO57PB1F5 A23 IO32PB1F3/HCLKCP C14 IO58NB1F5 D22 B6 IO33NB1F3/HCLKDN A15 IO58PB1F5 C22 IO07PB0F0 C6 IO33PB1F3/HCLKDP B15 IO59NB1F5 B24 IO08NB0F0 C7 IO35NB1F3 B16 IO59PB1F5 A24 IO08PB0F0 D7 IO35PB1F3 A16 IO60NB1F5 E21 IO10NB0F0 F8 IO36NB1F3 F15 IO60PB1F5 E20 IO10PB0F0 E8 IO36PB1F3 G15 IO62NB1F5 D23 IO11NB0F0 A7 IO38NB1F3 F16 IO62PB1F5 C23 IO11PB0F0 A6 IO38PB1F3 G16 IO63NB1F5 F21 IO12NB0F1 C8 IO40NB1F3 A18 IO63PB1F5 F20 IO12PB0F1 D8 IO40PB1F3 A17 IO13NB0F1 B8 IO41NB1F4 C18 Bank 1 Bank 2 IO64NB2F6 H21 IO13PB0F1 B7 IO41PB1F4 C17 IO64PB2F6 G21 IO14NB0F1 D9 IO42NB1F4 D16 IO65NB2F6 G22 IO14PB0F1 E9 IO42PB1F4 E16 IO65PB2F6 F22 IO16NB0F1 F10 IO44NB1F4 D18 IO66NB2F6 F24 IO16PB0F1 F9 IO44PB1F4 D17 IO66PB2F6 F23 IO18NB0F1 B9 IO45NB1F4 B19 IO67NB2F6 E24 IO18PB0F1 C9 IO45PB1F4 B18 IO67PB2F6 E23 IO19NB0F1 A10 IO46NB1F4 B20 IO68NB2F6 H23 IO19PB0F1 A9 IO46PB1F4 A20 IO68PB2F6 H22 IO20NB0F1 D10 IO48NB1F4 F17 IO69NB2F6 D25 IO20PB0F1 E10 IO48PB1F4 E17 IO69PB2F6 C25 IO21NB0F1 B10 IO49NB1F4 A22 IO70NB2F6 G24 IO21PB0F1 C10 IO49PB1F4 A21 IO70PB2F6 G23 IO22NB0F2 F11 IO50NB1F4 E18 IO71NB2F6 F25 IO22PB0F2 G11 IO50PB1F4 F18 IO71PB2F6 E25 v2.3 3-43 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number IO72NB2F6 G26 IO95PB2F8 N25 IO72PB2F6 F26 IO73NB2F6 E26 IO98NB3F9 IO73PB2F6 D26 IO74NB2F7 3 -4 4 AX1000 Function Pin Number IO119PB3F11 AA25 IO120NB3F11 W22 P20 IO120PB3F11 V22 IO98PB3F9 P21 IO121NB3F11 Y23 J21 IO99NB3F9 R24 IO121PB3F11 W23 IO74PB2F7 J22 IO99PB3F9 P24 IO122NB3F11 AA24 IO75NB2F7 J24 IO100NB3F9 R22 IO122PB3F11 Y24 IO75PB2F7 H24 IO100PB3F9 P22 IO123NB3F11 AE26 IO76NB2F7 K23 IO101NB3F9 T26 IO123PB3F11 AD26 Bank 3 IO76PB2F7 J23 IO101PB3F9 R26 IO124NB3F11 Y21 IO77NB2F7 H25 IO102NB3F9 R21 IO124PB3F11 W21 IO77PB2F7 G25 IO102PB3F9 R20 IO125NB3F11 AD25 IO78NB2F7 K25 IO103NB3F9 T25 IO125PB3F11 AC25 IO78PB2F7 J25 IO103PB3F9 R25 IO126NB3F11 AB23 IO80NB2F7 K21 IO105NB3F9 V26 IO126PB3F11 AA23 IO80PB2F7 K22 IO105PB3F9 U26 IO127NB3F11 AC24 IO81NB2F7 K26 IO106NB3F9 T23 IO127PB3F11 AB24 IO81PB2F7 J26 IO106PB3F9 R23 IO128NB3F11 AA22 IO82NB2F7 L24 IO107NB3F10 U24 IO128PB3F11 Y22 IO82PB2F7 K24 IO107PB3F10 T24 IO83NB2F7 L23 IO108NB3F10 U22 IO129NB4F12 AB21 IO83PB2F7 L22 IO108PB3F10 T22 IO129PB4F12 AA21 IO84NB2F7 L20 IO109NB3F10 V25 IO131NB4F12 AD22 IO84PB2F7 L21 IO109PB3F10 U25 IO131PB4F12 AD23 IO86NB2F8 L26 IO110NB3F10 T21 IO132NB4F12 AE23 IO86PB2F8 L25 IO110PB3F10 T20 IO132PB4F12 AE24 IO88NB2F8 M23 IO112NB3F10 V23 IO133NB4F12 AB20 IO88PB2F8 M22 IO112PB3F10 U23 IO133PB4F12 AA20 IO89NB2F8 M26 IO113NB3F10 Y25 IO134NB4F12 AC21 IO89PB2F8 M25 IO113PB3F10 W25 IO134PB4F12 AC22 IO90NB2F8 M20 IO114NB3F10 V21 IO135NB4F12 AF22 IO90PB2F8 M21 IO114PB3F10 U21 IO135PB4F12 AF23 IO91NB2F8 N24 IO115NB3F10 W24 IO137NB4F12 AB19 Bank 4 IO91PB2F8 M24 IO115PB3F10 V24 IO137PB4F12 AA19 IO92NB2F8 N22 IO116NB3F10 AA26 IO139NB4F13 AC19 IO92PB2F8 N23 IO116PB3F10 Y26 IO139PB4F13 AC20 IO94NB2F8 N20 IO118NB3F11 AC26 IO140NB4F13 AE21 IO94PB2F8 N21 IO118PB3F11 AB26 IO140PB4F13 AE22 IO95NB2F8 P25 IO119NB3F11 AB25 IO141NB4F13 AD20 v2.3 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA AX1000 Function Pin Number 676-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number IO141PB4F13 AD21 IO167PB5F15 AA12 IO192NB5F17 AA6 IO143NB4F13 AB17 IO168NB5F15 AF9 IO192PB5F17 AA7 IO143PB4F13 AB18 IO168PB5F15 AF10 IO144NB4F13 AE19 IO169NB5F15 AB11 IO193NB6F18 Y5 IO144PB4F13 AE20 IO169PB5F15 AA11 IO193PB6F18 AA5 IO145NB4F13 AC17 IO171NB5F16 AE9 IO194NB6F18 AB3 IO145PB4F13 AC18 IO171PB5F16 AE10 IO194PB6F18 AC3 IO146NB4F13 AD18 IO173NB5F16 AC10 IO195NB6F18 Y4 IO146PB4F13 AD19 IO173PB5F16 AC11 IO195PB6F18 AA4 IO147NB4F13 AA17 IO174NB5F16 AE7 IO196NB6F18 AC2 IO147PB4F13 AA18 IO174PB5F16 AE8 IO196PB6F18 AD2 IO148NB4F13 AF20 IO175NB5F16 AC9 IO197NB6F18 W6 IO148PB4F13 AF21 IO175PB5F16 AD9 IO197PB6F18 Y6 IO149NB4F13 AA16 IO176NB5F16 AF6 IO198NB6F18 AD1 IO149PB4F13 Y16 IO176PB5F16 AF7 IO198PB6F18 AE1 IO151NB4F13 AC16 IO177NB5F16 AA10 IO199NB6F18 AA2 IO151PB4F13 AB16 IO177PB5F16 AB10 IO199PB6F18 AB2 IO153NB4F14 AE17 IO179NB5F16 AD7 IO200NB6F18 Y3 IO153PB4F14 AE18 IO179PB5F16 AD8 IO200PB6F18 AA3 IO154NB4F14 AF17 IO180NB5F16 AC7 IO201NB6F18 V5 IO154PB4F14 AF18 IO180PB5F16 AC8 IO201PB6F18 W5 IO155NB4F14 AA15 IO181NB5F17 AA9 IO202NB6F18 AB1 IO155PB4F14 Y15 IO181PB5F17 AB9 IO202PB6F18 AC1 IO157NB4F14 AC15 IO183NB5F17 AD6 IO203NB6F19 V4 Bank 6 IO157PB4F14 AB15 IO183PB5F17 AE6 IO203PB6F19 W4 IO159NB4F14/CLKEN AE16 IO184NB5F17 AE5 IO204NB6F19 V3 IO159PB4F14/CLKEP AF16 IO184PB5F17 AF5 IO204PB6F19 W3 IO160NB4F14/CLKFN AE14 IO185NB5F17 AA8 IO205NB6F19 U6 IO160PB4F14/CLKFP AE15 IO185PB5F17 AB8 IO205PB6F19 V6 IO187NB5F17 AC5 IO206NB6F19 W2 Bank 5 IO161NB5F15/CLKGN AE12 IO187PB5F17 AC6 IO206PB6F19 Y2 IO161PB5F15/CLKGP AE13 IO188NB5F17 AD4 IO207NB6F19 U4 IO162NB5F15/CLKHN AE11 IO188PB5F17 AD5 IO207PB6F19 U5 IO162PB5F15/CLKHP AF11 IO189NB5F17 AB6 IO208NB6F19 Y1 IO163NB5F15 AC12 IO189PB5F17 AB7 IO208PB6F19 AA1 IO163PB5F15 AB12 IO190NB5F17 AF4 IO209NB6F19 T6 IO165NB5F15 Y12 IO190PB5F17 AE4 IO209PB6F19 T7 IO165PB5F15 AA13 IO191NB5F17 AE3 IO211NB6F19 T3 IO167NB5F15 Y11 IO191PB5F17 AF3 IO211PB6F19 U3 v2.3 3-45 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA AX1000 Function Pin Number AX1000 Function IO212NB6F19 V1 IO212PB6F19 V2 IO213NB6F19 Pin Number AX1000 Function Pin Number IO237NB7F22 L6 GND A14 IO237PB7F22 L7 GND A19 T5 IO238NB7F22 K3 GND A26 IO213PB6F19 T4 IO238PB7F22 L3 GND A8 IO214NB6F20 U1 IO240NB7F22 J1 GND AC23 IO214PB6F20 U2 IO240PB7F22 K1 GND AC4 IO215NB6F20 R6 IO241NB7F22 K6 GND AD24 IO215PB6F20 R7 IO241PB7F22 K5 GND AD3 IO217NB6F20 R5 IO242NB7F22 H2 GND AE2 IO217PB6F20 R4 IO242PB7F22 J2 GND AE25 IO218NB6F20 R2 IO243NB7F22 J4 GND AF1 IO218PB6F20 T2 IO243PB7F22 K4 GND AF13 IO219NB6F20 P3 IO244NB7F22 H3 GND AF14 IO219PB6F20 R3 IO244PB7F22 J3 GND AF19 IO220NB6F20 R1 IO245NB7F22 G2 GND AF26 IO220PB6F20 T1 IO245PB7F22 G1 GND AF8 IO221NB6F20 P6 IO247NB7F23 J6 GND B2 IO221PB6F20 P7 IO247PB7F23 J5 GND B25 IO223NB6F20 P5 IO248NB7F23 E1 GND B26 IO223PB6F20 P4 IO248PB7F23 F1 GND C24 IO249NB7F23 E2 GND C3 Bank 7 3 -4 6 676-Pin FBGA IO225NB7F21 N5 IO249PB7F23 F2 GND G20 IO225PB7F21 N4 IO250NB7F23 G4 GND G7 IO226NB7F21 N2 IO250PB7F23 H4 GND H1 IO226PB7F21 N3 IO251NB7F23 F3 GND H19 IO227NB7F21 N6 IO251PB7F23 G3 GND H26 IO227PB7F21 N7 IO253NB7F23 H6 GND H8 IO229NB7F21 M7 IO253PB7F23 H5 GND J18 IO229PB7F21 M6 IO254NB7F23 D2 GND J9 IO231NB7F21 M5 IO254PB7F23 D1 GND K10 IO231PB7F21 M4 IO255NB7F23 E4 GND K11 IO232NB7F21 L1 IO255PB7F23 F4 GND K12 IO232PB7F21 M1 IO256NB7F23 D3 GND K13 IO233NB7F21 M2 IO256PB7F23 E3 GND K14 IO233PB7F21 M3 IO257NB7F23 F5 GND K15 IO235NB7F21 K2 IO257PB7F23 G5 GND K16 IO235PB7F21 L2 GND K17 IO236NB7F22 L5 GND A1 GND L10 IO236PB7F22 L4 GND A13 GND L11 Dedicated I/O v2.3 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND L12 GND R15 TCK E5 GND L13 GND R16 TDI B3 GND L14 GND R17 TDO G6 GND L15 GND T10 TMS D4 GND L16 GND T11 TRST A2 GND L17 GND T12 VCCA AB4 GND M10 GND T13 VCCA AF24 GND M11 GND T14 VCCA C1 GND M12 GND T15 VCCA C26 GND M13 GND T16 VCCA J10 GND M14 GND T17 VCCA J11 GND M15 GND U10 VCCA J12 GND M16 GND U11 VCCA J13 GND M17 GND U12 VCCA J14 GND N1 GND U13 VCCA J15 GND N10 GND U14 VCCA J16 GND N11 GND U15 VCCA J17 GND N12 GND U16 VCCA K18 GND N13 GND U17 VCCA K9 GND N14 GND V18 VCCA L18 GND N15 GND V9 VCCA L9 GND N16 GND W1 VCCA M18 GND N17 GND W19 VCCA M9 GND N26 GND W26 VCCA N18 GND P1 GND W8 VCCA N9 GND P10 GND Y20 VCCA P18 GND P11 GND Y7 VCCA P9 GND P12 GND/LP C2 VCCA R18 GND P13 NC A25 VCCA R9 GND P14 NC AC13 VCCA T18 GND P15 NC AC14 VCCA T9 GND P16 NC AF2 VCCA U18 GND P17 NC AF25 VCCA U9 V10 GND P26 NC D13 VCCA GND R10 NC D14 VCCA V11 GND R11 PRA E13 VCCA V12 GND R12 PRB B14 VCCA V13 GND R13 PRC Y14 VCCA V14 GND R14 PRD AD14 VCCA V15 v2.3 3-47 Axcelerator Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number 3 -4 8 VCCA V16 VCCIB1 H15 VCCIB6 U7 VCCA V17 VCCIB1 H16 VCCIB6 U8 VCCPLA E12 VCCIB1 H17 VCCIB6 V7 VCCPLB F13 VCCIB1 H18 VCCIB6 V8 VCCPLC E15 VCCIB2 H20 VCCIB6 W7 VCCPLD G14 VCCIB2 J19 VCCIB7 H7 VCCPLE AF15 VCCIB2 J20 VCCIB7 J7 VCCPLF AA14 VCCIB2 K19 VCCIB7 J8 VCCPLG AF12 VCCIB2 K20 VCCIB7 K7 VCCPLH AB13 VCCIB2 L19 VCCIB7 K8 VCCDA A11 VCCIB2 M19 VCCIB7 L8 VCCDA A3 VCCIB2 N19 VCCIB7 M8 VCCDA AB22 VCCIB3 P19 VCCIB7 N8 VCCDA AB5 VCCIB3 R19 VCOMPLA D12 VCCDA AD10 VCCIB3 T19 VCOMPLB G13 VCCDA AD11 VCCIB3 U19 VCOMPLC D15 VCCDA AD13 VCCIB3 U20 VCOMPLD F14 VCCDA AD16 VCCIB3 V19 VCOMPLE AD15 VCCDA AD17 VCCIB3 V20 VCOMPLF AB14 VCCDA B1 VCCIB3 W20 VCOMPLG AD12 VCCDA B11 VCCIB4 W14 VCOMPLH Y13 VCCDA B17 VCCIB4 W15 VPUMP E22 VCCDA C16 VCCIB4 W16 VCCDA D24 VCCIB4 W17 VCCDA E14 VCCIB4 W18 VCCDA P2 VCCIB4 Y17 VCCDA P23 VCCIB4 Y18 VCCIB0 G10 VCCIB4 Y19 VCCIB0 G8 VCCIB5 W10 VCCIB0 G9 VCCIB5 W11 VCCIB0 H10 VCCIB5 W12 VCCIB0 H11 VCCIB5 W13 VCCIB0 H12 VCCIB5 W9 VCCIB0 H13 VCCIB5 Y10 VCCIB0 H9 VCCIB5 Y8 VCCIB1 G17 VCCIB5 Y9 VCCIB1 G18 VCCIB6 P8 VCCIB1 G19 VCCIB6 R8 VCCIB1 H14 VCCIB6 T8 v2.3 Axcelerator Family FPGAs 896-Pin FBGA A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Figure 3-7 * 896-Pin FBGA (Bottom View) v2.3 3-49 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number Bank 0 3 -5 0 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number IO18PB0F1 E11 IO37NB1F3 B19 IO00NB0F0 D6 IO19NB0F1 C12 IO37PB1F3 A19 IO00PB0F0 E6 IO19PB0F1 C11 IO38NB1F3 H18 IO01NB0F0 A5 IO20NB0F1 F12 IO38PB1F3 J18 IO01PB0F0 B5 IO20PB0F1 G12 IO39NB1F3 B20 IO02NB0F0 G9 IO21NB0F1 D12 IO39PB1F3 A20 IO02PB0F0 G8 IO21PB0F1 E12 IO40NB1F3 C20 IO03NB0F0 F8 IO22NB0F2 H13 IO40PB1F3 C19 IO03PB0F0 F7 IO22PB0F2 J13 IO41NB1F4 E20 IO04NB0F0 D7 IO23NB0F2 A12 IO41PB1F4 E19 IO04PB0F0 E7 IO23PB0F2 A11 IO42NB1F4 F18 IO05NB0F0 C7 IO24NB0F2 F13 IO42PB1F4 G18 IO05PB0F0 C6 IO24PB0F2 G13 IO43NB1F4 A22 IO06NB0F0 H9 IO25NB0F2 B13 IO43PB1F4 A21 IO06PB0F0 H8 IO25PB0F2 B12 IO44NB1F4 F20 IO07NB0F0 D8 IO26NB0F2 E14 IO44PB1F4 F19 IO07PB0F0 E8 IO26PB0F2 E13 IO45NB1F4 D21 IO08NB0F0 E9 IO27NB0F2 B14 IO45PB1F4 D20 IO08PB0F0 F9 IO27PB0F2 A14 IO46NB1F4 D22 IO09NB0F0 A7 IO28NB0F2 H14 IO46PB1F4 C22 IO09PB0F0 B7 IO28PB0F2 J14 IO47NB1F4 A25 IO10NB0F0 H10 IO29NB0F2 B15 IO47PB1F4 A24 IO10PB0F0 G10 IO29PB0F2 A15 IO48NB1F4 H19 IO11NB0F0 C9 IO30NB0F2/HCLKAN C14 IO48PB1F4 G19 IO11PB0F0 C8 IO30PB0F2/HCLKAP D14 IO49NB1F4 C24 IO12NB0F1 E10 IO31NB0F2/HCLKBN E15 IO49PB1F4 C23 IO12PB0F1 F10 IO31PB0F2/HCLKBP D15 IO50NB1F4 G20 IO13NB0F1 D10 IO50PB1F4 H20 IO13PB0F1 D9 IO32NB1F3/HCLKCN E17 IO51NB1F4 F21 IO14NB0F1 F11 IO32PB1F3/HCLKCP E16 IO51PB1F4 E21 IO14PB0F1 G11 IO33NB1F3/HCLKDN C17 IO52NB1F4 F22 IO15NB0F1 A10 IO33PB1F3/HCLKDP D17 IO52PB1F4 E22 IO15PB0F1 A9 IO34NB1F3 A17 IO53NB1F4 B25 IO16NB0F1 H12 IO34PB1F3 B17 IO53PB1F4 B24 IO16PB0F1 H11 IO35NB1F3 D18 IO54NB1F5 D24 IO17NB0F1 B11 IO35PB1F3 C18 IO54PB1F5 D23 IO17PB0F1 B10 IO36NB1F3 H17 IO55NB1F5 F23 IO18NB0F1 D11 IO36PB1F3 J17 IO55PB1F5 E23 Bank 1 v2.3 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO56NB1F5 H21 IO74PB2F7 L24 IO93PB2F8 R30 IO56PB1F5 G21 IO75NB2F7 L26 IO94NB2F8 R22 IO57NB1F5 D25 IO75PB2F7 K26 IO94PB2F8 R23 IO57PB1F5 C25 IO76NB2F7 M25 IO95NB2F8 T27 IO58NB1F5 F24 IO76PB2F7 L25 IO95PB2F8 R27 IO58PB1F5 E24 IO77NB2F7 K27 IO59NB1F5 D26 IO77PB2F7 J27 IO96NB3F9 T29 IO59PB1F5 C26 IO78NB2F7 M27 IO96PB3F9 T30 IO60NB1F5 G23 IO78PB2F7 L27 IO97NB3F9 U29 IO60PB1F5 G22 IO79NB2F7 K30 IO97PB3F9 U30 IO61NB1F5 B27 IO79PB2F7 K29 IO98NB3F9 T22 IO61PB1F5 A27 IO80NB2F7 M23 IO98PB3F9 T23 IO62NB1F5 F25 IO80PB2F7 M24 IO99NB3F9 U26 IO62PB1F5 E25 IO81NB2F7 M28 IO99PB3F9 T26 IO63NB1F5 H23 IO81PB2F7 L28 IO100NB3F9 U24 IO63PB1F5 H22 IO82NB2F7 N26 IO100PB3F9 T24 IO82PB2F7 M26 IO101NB3F9 V28 Bank 2 Bank 3 IO64NB2F6 K23 IO83NB2F7 N25 IO101PB3F9 U28 IO64PB2F6 J23 IO83PB2F7 N24 IO102NB3F9 U23 IO65NB2F6 J24 IO84NB2F7 N22 IO102PB3F9 U22 IO65PB2F6 H24 IO84PB2F7 N23 IO103NB3F9 V27 IO66NB2F6 H26 IO85NB2F8 M29 IO103PB3F9 U27 IO66PB2F6 H25 IO85PB2F8 L29 IO104NB3F9 W29 IO67NB2F6 G26 IO86NB2F8 N28 IO104PB3F9 V29 IO67PB2F6 G25 IO86PB2F8 N27 IO105NB3F9 Y28 IO68NB2F6 K25 IO87NB2F8 P29 IO105PB3F9 W28 IO68PB2F6 K24 IO87PB2F8 P30 IO106NB3F9 V25 IO69NB2F6 F27 IO88NB2F8 P25 IO106PB3F9 U25 IO69PB2F6 E27 IO88PB2F8 P24 IO107NB3F10 W26 IO70NB2F6 J26 IO89NB2F8 P28 IO107PB3F10 V26 IO70PB2F6 J25 IO89PB2F8 P27 IO108NB3F10 W24 IO71NB2F6 H27 IO90NB2F8 P22 IO108PB3F10 V24 IO71PB2F6 G27 IO90PB2F8 P23 IO109NB3F10 Y27 IO72NB2F6 J28 IO91NB2F8 R26 IO109PB3F10 W27 IO72PB2F6 H28 IO91PB2F8 P26 IO110NB3F10 V23 IO73NB2F6 G28 IO92NB2F8 R24 IO110PB3F10 V22 IO73PB2F6 F28 IO92PB2F8 R25 IO111NB3F10 AA29 IO74NB2F7 L23 IO93NB2F8 R29 IO111PB3F10 Y29 v2.3 3-51 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO112NB3F10 Y25 IO130PB4F12 AK27 IO149PB4F13 AB18 IO112PB3F10 W25 IO131NB4F12 AF24 IO150NB4F13 AK21 IO113NB3F10 AB27 IO131PB4F12 AF25 IO150PB4F13 AJ21 IO113PB3F10 AA27 IO132NB4F12 AG25 IO151NB4F13 AE18 IO114NB3F10 Y23 IO132PB4F12 AG26 IO151PB4F13 AD18 IO114PB3F10 W23 IO133NB4F12 AD22 IO152NB4F14 AJ20 IO115NB3F10 AA26 IO133PB4F12 AC22 IO152PB4F14 AK20 IO115PB3F10 Y26 IO134NB4F12 AE23 IO153NB4F14 AG19 IO116NB3F10 AC28 IO134PB4F12 AE24 IO153PB4F14 AG20 IO116PB3F10 AB28 IO135NB4F12 AH24 IO154NB4F14 AH19 IO117NB3F10 AE29 IO135PB4F12 AH25 IO154PB4F14 AH20 IO117PB3F10 AD29 IO136NB4F12 AJ25 IO155NB4F14 AC17 IO118NB3F11 AE28 IO136PB4F12 AJ26 IO155PB4F14 AB17 IO118PB3F11 AD28 IO137NB4F12 AD21 IO156NB4F14 AK19 IO119NB3F11 AD27 IO137PB4F12 AC21 IO156PB4F14 AJ19 IO119PB3F11 AC27 IO138NB4F12 AK24 IO157NB4F14 AE17 IO120NB3F11 AA24 IO138PB4F12 AK25 IO157PB4F14 AD17 IO120PB3F11 Y24 IO139NB4F13 AE21 IO158NB4F14 AJ17 IO121NB3F11 AB25 IO139PB4F13 AE22 IO158PB4F14 AJ18 IO121PB3F11 AA25 IO140NB4F13 AG23 IO159NB4F14/CLKEN AG18 IO122NB3F11 AC26 IO140PB4F13 AG24 IO159PB4F14/CLKEP AH18 IO122PB3F11 AB26 IO141NB4F13 AF22 IO160NB4F14/CLKFN AG16 IO123NB3F11 AG28 IO141PB4F13 AF23 IO160PB4F14/CLKFP AG17 IO123PB3F11 AF28 IO142NB4F13 AJ23 IO124NB3F11 AB23 IO142PB4F13 AJ24 IO161NB5F15/CLKGN AG14 IO124PB3F11 AA23 IO143NB4F13 AD19 IO161PB5F15/CLKGP AG15 IO125NB3F11 AF27 IO143PB4F13 AD20 IO162NB5F15/CLKHN AG13 IO125PB3F11 AE27 IO144NB4F13 AG21 IO162PB5F15/CLKHP AH13 IO126NB3F11 AD25 IO144PB4F13 AG22 IO163NB5F15 AE14 IO126PB3F11 AC25 IO145NB4F13 AE19 IO163PB5F15 AD14 IO127NB3F11 AE26 IO145PB4F13 AE20 IO164NB5F15 AJ12 IO127PB3F11 AD26 IO146NB4F13 AF20 IO164PB5F15 AJ13 IO128NB3F11 AC24 IO146PB4F13 AF21 IO165NB5F15 AB14 IO128PB3F11 AB24 IO147NB4F13 AC19 IO165PB5F15 AC15 IO147PB4F13 AC20 IO166NB5F15 AK11 Bank 4 3 -5 2 Bank 5 IO129NB4F12 AD23 IO148NB4F13 AH22 IO166PB5F15 AK12 IO129PB4F12 AC23 IO148PB4F13 AH23 IO167NB5F15 AB13 IO130NB4F12 AK26 IO149NB4F13 AC18 IO167PB5F15 AC14 v2.3 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO168NB5F15 AH11 IO187NB5F17 AE7 IO205PB6F19 Y8 IO168PB5F15 AH12 IO187PB5F17 AE8 IO206NB6F19 AA4 IO169NB5F15 AD13 IO188NB5F17 AF6 IO206PB6F19 AB4 IO169PB5F15 AC13 IO188PB5F17 AF7 IO207NB6F19 W6 IO170NB5F15 AJ10 IO189NB5F17 AD8 IO207PB6F19 W7 IO170PB5F15 AJ11 IO189PB5F17 AD9 IO208NB6F19 AB3 IO171NB5F16 AG11 IO190NB5F17 AH6 IO208PB6F19 AC3 IO171PB5F16 AG12 IO190PB5F17 AG6 IO209NB6F19 V8 IO172NB5F16 AK9 IO191NB5F17 AG5 IO209PB6F19 V9 IO172PB5F16 AK10 IO191PB5F17 AH5 IO210NB6F19 AA2 IO173NB5F16 AE12 IO192NB5F17 AC8 IO210PB6F19 AA1 IO173PB5F16 AE13 IO192PB5F17 AC9 IO211NB6F19 V5 IO174NB5F16 AG9 IO211PB6F19 W5 IO174PB5F16 AG10 IO193NB6F18 AB7 IO212NB6F19 Y3 IO175NB5F16 AE11 IO193PB6F18 AC7 IO212PB6F19 Y4 IO175PB5F16 AF11 IO194NB6F18 AD5 IO213NB6F19 V7 IO176NB5F16 AH8 IO194PB6F18 AE5 IO213PB6F19 V6 IO176PB5F16 AH9 IO195NB6F18 AB6 IO214NB6F20 W3 IO177NB5F16 AC12 IO195PB6F18 AC6 IO214PB6F20 W4 IO177PB5F16 AD12 IO196NB6F18 AE4 IO215NB6F20 U8 IO178NB5F16 AJ7 IO196PB6F18 AF4 IO215PB6F20 U9 IO178PB5F16 AJ8 IO197NB6F18 AA8 IO216NB6F20 W1 IO179NB5F16 AF9 IO197PB6F18 AB8 IO216PB6F20 W2 IO179PB5F16 AF10 IO198NB6F18 AF3 IO217NB6F20 U7 IO180NB5F16 AE9 IO198PB6F18 AG3 IO217PB6F20 U6 IO180PB5F16 AE10 IO199NB6F18 AC4 IO218NB6F20 U4 IO181NB5F17 AC11 IO199PB6F18 AD4 IO218PB6F20 V4 IO181PB5F17 AD11 IO200NB6F18 AB5 IO219NB6F20 T5 IO182NB5F17 AK6 IO200PB6F18 AC5 IO219PB6F20 U5 IO182PB5F17 AK7 IO201NB6F18 Y7 IO220NB6F20 U3 IO183NB5F17 AF8 IO201PB6F18 AA7 IO220PB6F20 V3 IO183PB5F17 AG8 IO202NB6F18 AD3 IO221NB6F20 T8 IO184NB5F17 AG7 IO202PB6F18 AE3 IO221PB6F20 T9 IO184PB5F17 AH7 IO203NB6F19 Y6 IO222NB6F20 U2 IO185NB5F17 AC10 IO203PB6F19 AA6 IO222PB6F20 V2 IO185PB5F17 AD10 IO204NB6F19 Y5 IO223NB6F20 T7 IO186NB5F17 AJ5 IO204PB6F19 AA5 IO223PB6F20 T6 IO186PB5F17 AJ6 IO205NB6F19 W8 IO224NB6F20 R2 Bank 6 v2.3 3-53 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO224PB6F20 T2 IO243NB7F22 L6 GND AA21 IO243PB7F22 M6 GND AA28 Bank 7 3 -5 4 IO225NB7F21 R7 IO244NB7F22 K5 GND AA3 IO225PB7F21 R6 IO244PB7F22 L5 GND AB2 IO226NB7F21 R4 IO245NB7F22 J4 GND AB22 IO226PB7F21 R5 IO245PB7F22 J3 GND AB29 IO227NB7F21 R8 IO246NB7F22 G2 GND AB9 IO227PB7F21 R9 IO246PB7F22 H2 GND AC1 IO228NB7F21 P1 IO247NB7F23 L8 GND AC30 IO228PB7F21 R1 IO247PB7F23 L7 GND AE25 IO229NB7F21 P9 IO248NB7F23 G3 GND AE6 IO229PB7F21 P8 IO248PB7F23 H3 GND AF26 IO230NB7F21 N2 IO249NB7F23 G4 GND AF5 IO230PB7F21 P2 IO249PB7F23 H4 GND AG27 IO231NB7F21 P7 IO250NB7F23 J6 GND AG4 IO231PB7F21 P6 IO250PB7F23 K6 GND AH10 IO232NB7F21 N3 IO251NB7F23 H5 GND AH15 IO232PB7F21 P3 IO251PB7F23 J5 GND AH16 IO233NB7F21 P4 IO252NB7F23 F2 GND AH21 IO233PB7F21 P5 IO252PB7F23 F1 GND AH28 IO234NB7F21 L1 IO253NB7F23 K8 GND AH3 IO234PB7F21 M1 IO253PB7F23 K7 GND AJ1 IO235NB7F21 M4 IO254NB7F23 F4 GND AJ2 IO235PB7F21 N4 IO254PB7F23 F3 GND AJ22 IO236NB7F22 N7 IO255NB7F23 G6 GND AJ29 IO236PB7F22 N6 IO255PB7F23 H6 GND AJ30 IO237NB7F22 N8 IO256NB7F23 F5 GND AJ9 IO237PB7F22 N9 IO256PB7F23 G5 GND AK13 IO238NB7F22 M5 IO257NB7F23 H7 GND AK18 IO238PB7F22 N5 IO257PB7F23 J7 GND AK2 IO239NB7F22 L2 GND AK23 IO239PB7F22 M2 GND A13 GND AK29 IO240NB7F22 L3 GND A18 GND AK8 IO240PB7F22 M3 GND A2 GND B1 IO241NB7F22 M8 GND A23 GND B2 IO241PB7F22 M7 GND A29 GND B22 IO242NB7F22 K4 GND A8 GND B29 IO242PB7F22 L4 GND AA10 GND B30 Dedicated I/O v2.3 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND B9 GND N17 GND U18 GND C10 GND N18 GND U19 GND C15 GND N19 GND V1 GND C16 GND N30 GND V12 GND C21 GND P12 GND V13 GND C28 GND P13 GND V14 GND C3 GND P14 GND V15 GND D27 GND P15 GND V16 GND D28 GND P16 GND V17 GND D4 GND P17 GND V18 GND E26 GND P18 GND V19 GND E5 GND P19 GND V30 GND H1 GND R12 GND W12 GND H30 GND R13 GND W13 GND J2 GND R14 GND W14 GND J22 GND R15 GND W15 GND J29 GND R16 GND W16 GND J9 GND R17 GND W17 GND K10 GND R18 GND W18 GND K21 GND R19 GND W19 GND K28 GND R28 GND Y11 GND K3 GND R3 GND Y20 GND L11 GND T12 GND/LP E4 GND L20 GND T13 NC A16 GND M12 GND T14 NC A26 GND M13 GND T15 NC A4 GND M14 GND T16 NC A6 GND M15 GND T17 NC AA30 GND M16 GND T18 NC AB1 GND M17 GND T19 NC AB30 GND M18 GND T28 NC AC2 GND M19 GND T3 NC AC29 GND N1 GND U12 NC AD1 GND N12 GND U13 NC AD2 GND N13 GND U14 NC AD30 GND N14 GND U15 NC AE1 GND N15 GND U16 NC AE15 GND N16 GND U17 NC AE16 v2.3 3-55 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number NC AE2 NC E2 VCCA L13 NC AE30 NC E29 VCCA L14 NC AF1 NC E30 VCCA L15 NC AF2 NC F15 VCCA L16 NC AF29 NC F16 VCCA L17 NC AF30 NC F29 VCCA L18 NC AG1 NC F30 VCCA L19 NC AG2 NC G1 VCCA M11 NC AG29 NC G29 VCCA M20 NC AG30 NC G30 VCCA N11 NC AH27 NC H29 VCCA N20 NC AH4 NC J1 VCCA P11 NC AJ14 NC J30 VCCA P20 NC AJ15 NC K1 VCCA R11 NC AJ16 NC K2 VCCA R20 NC AJ27 NC L30 VCCA T11 NC AJ4 NC M30 VCCA T20 NC AK14 NC N29 VCCA U11 NC AK15 NC T1 VCCA U20 NC AK16 NC U1 VCCA V11 NC AK17 NC W30 VCCA V20 NC AK22 NC Y1 VCCA W11 NC AK4 NC Y2 VCCA W20 NC AK5 NC Y30 VCCA Y12 NC B16 PRA G15 VCCA Y13 NC B18 PRB D16 VCCA Y14 NC B21 PRC AB16 VCCA Y15 NC B23 PRD AF16 VCCA Y16 NC B26 TCK G7 VCCA Y17 NC B4 TDI D5 VCCA Y18 NC B6 TDO J8 VCCA Y19 NC B8 TMS F6 VCCPLA G14 NC C27 TRST C4 VCCPLB H15 NC D1 VCCA AD6 VCCPLC G17 NC D2 VCCA AH26 VCCPLD J16 NC D29 VCCA E28 VCCPLE AH17 NC D30 VCCA E3 VCCPLF AC16 NC E1 VCCA L12 VCCPLG AH14 3 -5 6 v2.3 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number VCCPLH AD15 VCCIB2 C29 VCCIB5 AJ3 VCCDA AD24 VCCIB2 C30 VCCIB5 AK3 VCCDA AD7 VCCIB2 K22 VCCIB6 AA9 VCCDA AF12 VCCIB2 L21 VCCIB6 AH1 VCCDA AF13 VCCIB2 L22 VCCIB6 AH2 VCCDA AF15 VCCIB2 M21 VCCIB6 T10 VCCDA AF18 VCCIB2 M22 VCCIB6 U10 VCCDA AF19 VCCIB2 N21 VCCIB6 V10 VCCDA C13 VCCIB2 P21 VCCIB6 W10 VCCDA C5 VCCIB2 R21 VCCIB6 W9 VCCDA D13 VCCIB3 AA22 VCCIB6 Y10 VCCDA D19 VCCIB3 AH29 VCCIB6 Y9 VCCDA D3 VCCIB3 AH30 VCCIB7 C1 VCCDA E18 VCCIB3 T21 VCCIB7 C2 VCCDA F26 VCCIB3 U21 VCCIB7 K9 VCCDA G16 VCCIB3 V21 VCCIB7 L10 VCCDA T25 VCCIB3 W21 VCCIB7 L9 VCCDA T4 VCCIB3 W22 VCCIB7 M10 VCCIB0 A3 VCCIB3 Y21 VCCIB7 M9 VCCIB0 B3 VCCIB3 Y22 VCCIB7 N10 VCCIB0 J10 VCCIB4 AA16 VCCIB7 P10 VCCIB0 J11 VCCIB4 AA17 VCCIB7 R10 VCCIB0 J12 VCCIB4 AA18 VCOMPLA F14 VCCIB0 K11 VCCIB4 AA19 VCOMPLB J15 VCCIB0 K12 VCCIB4 AA20 VCOMPLC F17 VCCIB0 K13 VCCIB4 AB19 VCOMPLD H16 VCCIB0 K14 VCCIB4 AB20 VCOMPLE AF17 VCCIB0 K15 VCCIB4 AB21 VCOMPLF AD16 VCCIB1 A28 VCCIB4 AJ28 VCOMPLG AF14 VCCIB1 B28 VCCIB4 AK28 VCOMPLH AB15 VCCIB1 J19 VCCIB5 AA11 VPUMP G24 VCCIB1 J20 VCCIB5 AA12 VCCIB1 J21 VCCIB5 AA13 VCCIB1 K16 VCCIB5 AA14 VCCIB1 K17 VCCIB5 AA15 VCCIB1 K18 VCCIB5 AB10 VCCIB1 K19 VCCIB5 AB11 VCCIB1 K20 VCCIB5 AB12 v2.3 3-57 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number Bank 0 AX2000 Function Pin Number AX2000 Function Pin Number IO18PB0F1 C8 IO42NB0F3/HCLKBN E15 IO42PB0F3/HCLKBP D15 IO00NB0F0 B4 IO19NB0F1 D11 IO00PB0F0 A4 IO19PB0F1 E11 IO01NB0F0 F8 IO20PB0F1 B8 IO43NB1F4/HCLKCN E17 IO01PB0F0 F7 IO21NB0F1 H12 IO43PB1F4/HCLKCP E16 IO02NB0F0 D6 IO21PB0F1 H11 IO44NB1F4/HCLKDN C17 IO02PB0F0 E6 IO23NB0F2 A10 IO44PB1F4/HCLKDP D17 IO04NB0F0 A5 IO23PB0F2 A9 IO45NB1F4 A16 IO04PB0F0 B5 IO25NB0F2 F12 IO45PB1F4 B16 IO05NB0F0 H8 IO25PB0F2 G12 IO47NB1F4 H17 IO05PB0F0 G8 IO26NB0F2 B11 IO47PB1F4 J17 IO06NB0F0 D7 IO26PB0F2 B10 IO48NB1F4 A17 IO06PB0F0 E7 IO27NB0F2 D12 IO48PB1F4 B17 IO07NB0F0 D8 IO27PB0F2 E12 IO49NB1F4 H18 IO07PB0F0 E8 IO28NB0F2 C12 IO49PB1F4 J18 IO08NB0F0 C7 IO28PB0F2 C11 IO51NB1F4 F18 IO08PB0F0 C6 IO30NB0F2 A12 IO51PB1F4 G18 IO09NB0F0 G9 IO30PB0F2 A11 IO52NB1F4 B18 IO09PB0F0 H9 IO31NB0F2 F13 IO53NB1F4 D18 IO10NB0F0 A6 IO31PB0F2 G13 IO53PB1F4 C18 IO10PB0F0 B6 IO33NB0F2 H13 IO55NB1F5 H19 IO11NB0F0 H10 IO33PB0F2 J13 IO55PB1F5 G19 IO11PB0F0 G10 IO34NB0F3 B13 IO56NB1F5 B19 IO12NB0F1 E9 IO34PB0F3 B12 IO56PB1F5 A19 IO12PB0F1 F9 IO37NB0F3 E14 IO57NB1F5 E20 IO13NB0F1 E10 IO37PB0F3 E13 IO57PB1F5 E19 IO13PB0F1 F10 IO38NB0F3 B14 IO58NB1F5 C20 IO15NB0F1 F11 IO38PB0F3 A14 IO58PB1F5 C19 IO15PB0F1 G11 IO39NB0F3 H14 IO59NB1F5 B20 IO16NB0F1 A7 IO39PB0F3 J14 IO59PB1F5 A20 IO16PB0F1 B7 IO40NB0F3 B15 IO61NB1F5 F20 IO17NB0F1 D10 IO40PB0F3 A15 IO61PB1F5 F19 IO17PB0F1 D9 IO41NB0F3/HCLKAN C14 IO62NB1F5 A22 IO18NB0F1 C9 IO41PB0F3/HCLKAP D14 IO62PB1F5 A21 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -5 8 896-Pin FBGA * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 Bank 1 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO63NB1F5 D21 IO83NB1F7 F24 IO99PB2F9 L24 IO63PB1F5 D20 IO83PB1F7 E24 IO100NB2F9 K27 IO65NB1F6 G20 IO84NB1F7 D26 IO100PB2F9 J27 IO65PB1F6 H20 IO84PB1F7 C26 IO101PB2F9 J30 IO66NB1F6 B23 IO85NB1F7 F25 IO102NB2F9 E30 IO66PB1F6 B21 IO85PB1F7 E25 IO102PB2F9 D30 IO67NB1F6 H21 IO103NB2F9 L26 IO67PB1F6 G21 IO86NB2F8 G26 IO103PB2F9 K26 IO68NB1F6 D22 IO86PB2F8 G25 IO104NB2F9 F29 IO68PB1F6 C22 IO87NB2F8 K23 IO105NB2F9 M25 IO69NB1F6 A25 IO87PB2F8 J23 IO105PB2F9 L25 IO69PB1F6 A24 IO88NB2F8 J24 IO106NB2F9 K30 IO70NB1F6 F22 IO88PB2F8 H24 IO106PB2F9 K29 IO70PB1F6 E22 IO89NB2F8 E29 IO107NB2F10 M23 IO71NB1F6 F21 IO89PB2F8 D29 IO107PB2F10 M24 IO71PB1F6 E21 IO90NB2F8 F27 IO109NB2F10 M27 IO73NB1F6 C24 IO90PB2F8 E27 IO109PB2F10 L27 IO73PB1F6 C23 IO91NB2F8 H26 IO110NB2F10 M28 IO74NB1F6 D24 IO91PB2F8 H25 IO110PB2F10 L28 IO74PB1F6 D23 IO92NB2F8 G28 IO111NB2F10 N22 IO75NB1F6 H23 IO92PB2F8 F28 IO111PB2F10 N23 IO75PB1F6 H22 IO93NB2F8 J26 IO112NB2F10 M29 IO76NB1F7 B25 IO93PB2F8 J25 IO112PB2F10 L29 IO76PB1F7 B24 IO94NB2F8 H27 IO113NB2F10 N26 IO78NB1F7 B26 IO94PB2F8 G27 IO113PB2F10 M26 IO78PB1F7 A26 IO95NB2F8 H29 IO114NB2F10 M30 IO79NB1F7 F23 IO95PB2F8 G29 IO114PB2F10 L30 IO79PB1F7 E23 IO96NB2F9 G30 IO115NB2F10 N28 IO80NB1F7 D25 IO96PB2F9 F30 IO115PB2F10 N27 IO80PB1F7 C25 IO97NB2F9 K25 IO117NB2F10 N25 IO81NB1F7 G23 IO97PB2F9 K24 IO117PB2F10 N24 IO81PB1F7 G22 IO98NB2F9 J28 IO118NB2F11 N29 IO82NB1F7 B27 IO98PB2F9 H28 IO119NB2F11 P22 IO82PB1F7 A27 IO99NB2F9 L23 IO119PB2F11 P23 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Bank 2 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-59 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO121NB2F11 P25 IO139PB3F13 U25 IO159NB3F14 AB25 IO121PB2F11 P24 IO141NB3F13 V23 IO159PB3F14 AA25 IO122NB2F11 P28 IO141PB3F13 V22 IO160NB3F14 AE30 IO122PB2F11 P27 IO142NB3F13 W29 IO160PB3F14 AD30 IO123NB2F11 R26 IO142PB3F13 V29 IO161NB3F15 AE29 IO123PB2F11 P26 IO143NB3F13 W26 IO161PB3F15 AD29 IO124NB2F11 P29 IO143PB3F13 V26 IO162NB3F15 AD27 IO124PB2F11 P30 IO145NB3F13 W24 IO162PB3F15 AC27 IO125NB2F11 R22 IO145PB3F13 V24 IO163NB3F15 AC26 IO125PB2F11 R23 IO146NB3F13 W27 IO163PB3F15 AB26 IO127NB2F11 R24 IO146PB3F13 W28 IO164NB3F15 AE28 IO127PB2F11 R25 IO147NB3F13 Y28 IO164PB3F15 AD28 IO128NB2F11 R29 IO147PB3F13 Y27 IO165NB3F15 AC24 IO128PB2F11 R30 IO148NB3F13 Y30 IO165PB3F15 AB24 IO148PB3F13 W30 IO166NB3F15 AG28 Bank 3 IO129NB3F12 T27 IO149NB3F13 Y25 IO166PB3F15 AF28 IO129PB3F12 R27 IO149PB3F13 W25 IO167NB3F15 AE26 IO130NB3F12 T29 IO150NB3F14 AA29 IO167PB3F15 AD26 IO130PB3F12 T30 IO150PB3F14 Y29 IO168NB3F15 AD25 IO131NB3F12 T22 IO151NB3F14 AC29 IO168PB3F15 AC25 IO131PB3F12 T23 IO152NB3F14 AA26 IO169NB3F15 AF27 IO132NB3F12 U26 IO152PB3F14 Y26 IO169PB3F15 AE27 IO132PB3F12 T26 IO153NB3F14 Y23 IO170NB3F15 AB23 IO133NB3F12 U24 IO153PB3F14 W23 IO170PB3F15 AA23 IO133PB3F12 T24 IO154NB3F14 AB30 IO135NB3F12 U23 IO154PB3F14 AA30 IO171NB4F16 AG29 IO135PB3F12 U22 IO155NB3F14 AB27 IO171PB4F16 AG30 IO136NB3F12 U29 IO155PB3F14 AA27 IO172NB4F16 AF24 IO136PB3F12 U30 IO156NB3F14 AC28 IO172PB4F16 AF25 IO137NB3F12 V28 IO156PB3F14 AB28 IO173NB4F16 AG25 IO137PB3F12 U28 IO157NB3F14 AA24 IO173PB4F16 AG26 IO138NB3F12 V27 IO157PB3F14 Y24 IO174NB4F16 AJ25 IO138PB3F12 U27 IO158NB3F14 AF29 IO174PB4F16 AJ26 IO139NB3F13 V25 IO158PB3F14 AF30 IO175NB4F16 AK26 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -6 0 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 Bank 4 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO175PB4F16 AK27 IO196PB4F18 AD20 IO216PB5F20 AC15 IO176NB4F16 AE23 IO197NB4F18 AJ20 IO217NB5F20 AK15 IO176PB4F16 AE24 IO197PB4F18 AK20 IO217PB5F20 AJ15 IO177NB4F16 AH24 IO198NB4F18 AC19 IO218NB5F20 AE14 IO177PB4F16 AH25 IO198PB4F18 AC20 IO218PB5F20 AD14 IO178NB4F16 AD23 IO199NB4F18 AG19 IO219NB5F20 AK14 IO178PB4F16 AC23 IO199PB4F18 AG20 IO219PB5F20 AJ14 IO179PB4F16 AJ27 IO200NB4F18 AH19 IO222NB5F20 AB13 IO180NB4F16 AG23 IO200PB4F18 AH20 IO222PB5F20 AC14 IO180PB4F16 AG24 IO201NB4F18 AK19 IO223NB5F21 AJ12 IO181NB4F17 AK24 IO201PB4F18 AJ19 IO223PB5F21 AJ13 IO181PB4F17 AK25 IO202NB4F18 AC18 IO225NB5F21 AH11 IO182NB4F17 AD22 IO202PB4F18 AB18 IO225PB5F21 AH12 IO182PB4F17 AC22 IO206NB4F19 AE18 IO226NB5F21 AC13 IO183NB4F17 AF22 IO206PB4F19 AD18 IO226PB5F21 AD13 IO183PB4F17 AF23 IO207NB4F19 AJ17 IO227NB5F21 AE12 IO184NB4F17 AE21 IO207PB4F19 AJ18 IO227PB5F21 AE13 IO184PB4F17 AE22 IO208NB4F19 AE17 IO228NB5F21 AG11 IO185NB4F17 AJ23 IO208PB4F19 AD17 IO228PB5F21 AG12 IO185PB4F17 AJ24 IO209NB4F19 AK17 IO229NB5F21 AK11 IO187NB4F17 AH22 IO210NB4F19 AC17 IO229PB5F21 AK12 IO187PB4F17 AH23 IO210PB4F19 AB17 IO230NB5F21 AC12 IO188NB4F17 AD21 IO211NB4F19 AJ16 IO230PB5F21 AD12 IO188PB4F17 AC21 IO211PB4F19 AK16 IO232NB5F21 AE11 IO189PB4F17 AK22 IO212NB4F19/CLKEN AG18 IO232PB5F21 AF11 IO190NB4F17 AF20 IO212PB4F19/CLKEP AH18 IO233NB5F21 AJ10 IO190PB4F17 AF21 IO213NB4F19/CLKFN AG16 IO233PB5F21 AJ11 IO191NB4F17 AG21 IO213PB4F19/CLKFP AG17 IO234NB5F21 AC11 IO191PB4F17 AG22 IO234PB5F21 AD11 IO192NB4F17 AE19 IO214NB5F20/CLKGN AG14 IO236NB5F22 AK9 IO192PB4F17 AE20 IO214PB5F20/CLKGP AG15 IO236PB5F22 AK10 IO195NB4F18 AK21 IO215NB5F20/CLKHN AG13 IO237NB5F22 AG9 IO195PB4F18 AJ21 IO215PB5F20/CLKHP AH13 IO237PB5F22 AG10 IO196NB4F18 AD19 IO216NB5F20 AB14 IO238NB5F22 AF9 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Bank 5 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-61 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number IO238PB5F22 AF10 IO273PB6F25 AE2* IO239NB5F22 AH8 IO257NB6F24 AE4 IO274NB6F25 W8 IO239PB5F22 AH9 IO257PB6F24 AF4 IO274PB6F25 Y8 IO240NB5F22 AC10 IO258NB6F24 AB7 IO275NB6F25 Y5 IO240PB5F22 AD10 IO258PB6F24 AC7 IO275PB6F25 AA5 IO242NB5F22 AE9 IO259NB6F24 AD5 IO277NB6F25 AA2 IO242PB5F22 AE10 IO259PB6F24 AE5 IO277PB6F25 AA1 IO243NB5F22 AJ7 IO260NB6F24 AF1 IO278NB6F26 W6 IO243PB5F22 AJ8 IO260PB6F24 AF2 IO278PB6F26 W7 IO244NB5F22 AK6 IO261NB6F24 AF3 IO279NB6F26 Y3 IO244PB5F22 AK7 IO261PB6F24 AG3 IO279PB6F26 Y4 IO245NB5F23 AF8 IO262NB6F24 AC4 IO280NB6F26 V8 IO245PB5F23 AG8 IO262PB6F24 AD4 IO280PB6F26 V9 IO246NB5F23 AD8 IO263NB6F24 AD3 IO281NB6F26 Y1 IO246PB5F23 AD9 IO263PB6F24 AE3 IO281PB6F26 Y2 IO247NB5F23 AG7 IO264NB6F24 AB6 IO282NB6F26 V5 IO247PB5F23 AH7 IO264PB6F24 AC6 IO282PB6F26 W5 IO248NB5F23 AK5 IO265NB6F24 AD1 IO284NB6F26 V7 IO249NB5F23 AJ5 IO265PB6F24 AE1 IO284PB6F26 V6 IO249PB5F23 AJ6 IO266NB6F24 AA8 IO285NB6F26 W3 IO250NB5F23 AC8 IO266PB6F24 AB8 IO285PB6F26 W4 IO250PB5F23 AC9 IO267NB6F25 AB5 IO286NB6F26 U8 IO251NB5F23 AH6 IO267PB6F25 AC5 IO286PB6F26 U9 IO251PB5F23 AG6 IO268NB6F25 AB3 IO287NB6F26 W1 IO252NB5F23 AF6 IO268PB6F25 AC3 IO287PB6F26 W2 IO252PB5F23 AF7 IO269NB6F25 AC2 IO288NB6F26 U7 IO253NB5F23 AG2 IO269PB6F25 AD2 IO288PB6F26 U6 IO253PB5F23 AG1 IO270NB6F25 Y7 IO290NB6F27 U4 IO254NB5F23 AE7 IO270PB6F25 AA7 IO290PB6F27 V4 IO254PB5F23 AE8 IO271NB6F25 AA4 IO291NB6F27 U3 IO255NB5F23 AG5 IO271PB6F25 AB4 IO291PB6F27 V3 IO255PB5F23 AH5 IO272NB6F25 Y6 IO292NB6F27 T5 IO256NB5F23 AJ4 IO272PB6F25 AA6 IO292PB6F27 U5 IO256PB5F23 AK4 IO273NB6F25 AB1* IO293NB6F27 U2 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -6 2 AX2000 Function 896-Pin FBGA Pin Number Bank 6 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO293PB6F27 V2 IO315NB7F29 L2 IO334NB7F31 G4 IO294NB6F27 T8 IO315PB7F29 M2 IO334PB7F31 H4 IO294PB6F27 T9 IO316NB7F29 N7 IO335NB7F31 F2 IO296NB6F27 T1 IO316PB7F29 N6 IO335PB7F31 F1 IO296PB6F27 U1 IO317NB7F29 L3 IO336NB7F31 H5 IO298NB6F27 T7 IO317PB7F29 M3 IO336PB7F31 J5 IO298PB6F27 T6 IO318NB7F29 N8 IO337NB7F31 E2 IO299NB6F27 R2 IO318PB7F29 N9 IO337PB7F31 E1 IO299PB6F27 T2 IO320NB7F29 L6 IO338NB7F31 H7 IO320PB7F29 M6 IO338PB7F31 J7 Bank 7 IO300NB7F28 R8 IO321NB7F30 K4 IO339NB7F31 F4 IO300PB7F28 R9 IO321PB7F30 L4 IO339PB7F31 F3 IO302NB7F28 R4 IO322NB7F30 M8 IO340NB7F31 F5 IO302PB7F28 R5 IO322PB7F30 M7 IO340PB7F31 G5 IO303NB7F28 P1 IO323NB7F30 J1 IO341NB7F31 G6 IO303PB7F28 R1 IO323PB7F30 K1 IO341PB7F31 H6 IO304NB7F28 R7 IO324NB7F30 K5 IO304PB7F28 R6 IO324PB7F30 L5 GND A13 IO306NB7F28 N2 IO326NB7F30 G1* GND A18 IO306PB7F28 P2 IO326PB7F30 K2* GND A2 IO307NB7F28 N3 IO327NB7F30 J4 GND A23 IO307PB7F28 P3 IO327PB7F30 J3 GND A29 IO308NB7F28 P9 IO328NB7F30 L8 GND A8 IO308PB7F28 P8 IO328PB7F30 L7 GND AA10 IO309NB7F28 P4 IO329NB7F30 G2 GND AA21 IO309PB7F28 P5 IO329PB7F30 H2 GND AA28 IO310NB7F29 P7 IO330NB7F30 G3 GND AA3 IO310PB7F29 P6 IO330PB7F30 H3 GND AB2 IO311NB7F29 L1 IO331NB7F30 K8 GND AB22 IO311PB7F29 M1 IO331PB7F30 K7 GND AB29 IO312NB7F29 M5 IO332NB7F31 J6 GND AB9 IO312PB7F29 N5 IO332PB7F31 K6 GND AC1 IO313NB7F29 M4 IO333NB7F31 D1 GND AC30 IO313PB7F29 N4 IO333PB7F31 D2 GND AE25 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 Dedicated I/O * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-63 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND AE6 GND C3 GND N19 GND AF26 GND D27 GND N30 GND AF5 GND D28 GND P12 GND AG27 GND D4 GND P13 GND AG4 GND E26 GND P14 GND AH10 GND E5 GND P15 GND AH15 GND H1 GND P16 GND AH16 GND H30 GND P17 GND AH21 GND J2 GND P18 GND AH28 GND J22 GND P19 GND AH3 GND J29 GND R12 GND AJ1 GND J9 GND R13 GND AJ2 GND K10 GND R14 GND AJ22 GND K21 GND R15 GND AJ29 GND K28 GND R16 GND AJ30 GND K3 GND R17 GND AJ9 GND L11 GND R18 GND AK13 GND L20 GND R19 GND AK18 GND M12 GND R28 GND AK2 GND M13 GND R3 GND AK23 GND M14 GND T12 GND AK29 GND M15 GND T13 GND AK8 GND M16 GND T14 GND B1 GND M17 GND T15 GND B2 GND M18 GND T16 GND B22 GND M19 GND T17 GND B29 GND N1 GND T18 GND B30 GND N12 GND T19 GND B9 GND N13 GND T28 GND C10 GND N14 GND T3 GND C15 GND N15 GND U12 GND C16 GND N16 GND U13 GND C21 GND N17 GND U14 GND C28 GND N18 GND U15 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -6 4 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND U16 VCCA AD6 VCCA Y18 GND U17 VCCA AH26 VCCA Y19 GND U18 VCCA E28 VCCDA AD24 GND U19 VCCA E3 VCCDA AD7 GND V1 VCCA L12 VCCDA AE15 GND V12 VCCA L13 VCCDA AE16 GND V13 VCCA L14 VCCDA AF12 GND V14 VCCA L15 VCCDA AF13 GND V15 VCCA L16 VCCDA AF15 GND V16 VCCA L17 VCCDA AF18 GND V17 VCCA L18 VCCDA AF19 GND V18 VCCA L19 VCCDA AH27 GND V19 VCCA M11 VCCDA AH4 GND V30 VCCA M20 VCCDA C13 GND W12 VCCA N11 VCCDA C27 GND W13 VCCA N20 VCCDA C5 GND W14 VCCA P11 VCCDA D13 GND W15 VCCA P20 VCCDA D19 GND W16 VCCA R11 VCCDA D3 GND W17 VCCA R20 VCCDA E18 GND W18 VCCA T11 VCCDA F15 GND W19 VCCA T20 VCCDA F16 GND Y11 VCCA U11 VCCDA F26 GND Y20 VCCA U20 VCCDA G16 GND/LP E4 VCCA V11 VCCDA T25 PRA G15 VCCA V20 VCCDA T4 PRB D16 VCCA W11 VCCIB0 A3 PRC AB16 VCCA W20 VCCIB0 B3 PRD AF16 VCCA Y12 VCCIB0 J10 TCK G7 VCCA Y13 VCCIB0 J11 TDI D5 VCCA Y14 VCCIB0 J12 TDO J8 VCCA Y15 VCCIB0 K11 TMS F6 VCCA Y16 VCCIB0 K12 TRST C4 VCCA Y17 VCCIB0 K13 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-65 Axcelerator Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number VCCIB0 K14 VCCIB4 AA18 VCCIB7 M9 VCCIB0 K15 VCCIB4 AA19 VCCIB7 N10 VCCIB1 A28 VCCIB4 AA20 VCCIB7 P10 VCCIB1 B28 VCCIB4 AB19 VCCIB7 R10 VCCIB1 J19 VCCIB4 AB20 VCCPLA G14 VCCIB1 J20 VCCIB4 AB21 VCCPLB H15 VCCIB1 J21 VCCIB4 AJ28 VCCPLC G17 VCCIB1 K16 VCCIB4 AK28 VCCPLD J16 VCCIB1 K17 VCCIB5 AA11 VCCPLE AH17 VCCIB1 K18 VCCIB5 AA12 VCCPLF AC16 VCCIB1 K19 VCCIB5 AA13 VCCPLG AH14 VCCIB1 K20 VCCIB5 AA14 VCCPLH AD15 VCCIB2 C29 VCCIB5 AA15 VCOMPLA F14 VCCIB2 C30 VCCIB5 AB10 VCOMPLB J15 VCCIB2 K22 VCCIB5 AB11 VCOMPLC F17 VCCIB2 L21 VCCIB5 AB12 VCOMPLD H16 VCCIB2 L22 VCCIB5 AJ3 VCOMPLE AF17 VCCIB2 M21 VCCIB5 AK3 VCOMPLF AD16 VCCIB2 M22 VCCIB6 AA9 VCOMPLG AF14 VCCIB2 N21 VCCIB6 AH1 VCOMPLH AB15 VCCIB2 P21 VCCIB6 AH2 VPUMP G24 VCCIB2 R21 VCCIB6 T10 VCCIB3 AA22 VCCIB6 U10 VCCIB3 AH29 VCCIB6 V10 VCCIB3 AH30 VCCIB6 W10 VCCIB3 T21 VCCIB6 W9 VCCIB3 U21 VCCIB6 Y10 VCCIB3 V21 VCCIB6 Y9 VCCIB3 W21 VCCIB7 C1 VCCIB3 W22 VCCIB7 C2 VCCIB3 Y21 VCCIB7 K9 VCCIB3 Y22 VCCIB7 L10 VCCIB4 AA16 VCCIB7 L9 VCCIB4 AA17 VCCIB7 M10 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -6 6 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 1152-Pin FBGA A1 Ball Pad Corner 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Figure 3-8 * 1152-Pin FBGA (Bottom View) v2.3 3-67 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number Bank 0 3 -6 8 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number IO19NB0F1 F13 IO38PB0F3 C16 IO00NB0F0 D6 IO19PB0F1 G13 IO39NB0F3 K16 IO00PB0F0 C6 IO20NB0F1 A10 IO39PB0F3 L16 IO01NB0F0 H10 IO20PB0F1 A9 IO40NB0F3 D17 IO01PB0F0 H9 IO21NB0F1 K14 IO40PB0F3 C17 IO02NB0F0 F8 IO21PB0F1 K13 IO41NB0F3/HCLKAN E16 IO02PB0F0 G8 IO22NB0F2 B11 IO41PB0F3/HCLKAP F16 IO03NB0F0 A6 IO22PB0F2 B10 IO42NB0F3/HCLKBN G17 IO03PB0F0 B6 IO23NB0F2 C12 IO42PB0F3/HCLKBP F17 IO04NB0F0 C7 IO23PB0F2 C11 IO04PB0F0 D7 IO24NB0F2 A12 IO43NB1F4/HCLKCN G19 IO05NB0F0 K10 IO24PB0F2 A11 IO43PB1F4/HCLKCP G18 IO05PB0F0 J10 IO25NB0F2 H14 IO44NB1F4/HCLKDN E19 IO06NB0F0 F9 IO25PB0F2 J14 IO44PB1F4/HCLKDP F19 IO06PB0F0 G9 IO26NB0F2 D13 IO45NB1F4 C18 IO07NB0F0 F10 IO26PB0F2 D12 IO45PB1F4 D18 IO07PB0F0 G10 IO27NB0F2 F14 IO46NB1F4 A18 IO08NB0F0 E9 IO27PB0F2 G14 IO46PB1F4 B18 IO08PB0F0 E8 IO28NB0F2 E14 IO47NB1F4 K19 IO09NB0F0 J11 IO28PB0F2 E13 IO47PB1F4 L19 IO09PB0F0 K11 IO29NB0F2 B13 IO48NB1F4 C19 IO10NB0F0 C8 IO29PB0F2 B12 IO48PB1F4 D19 IO10PB0F0 D8 IO30NB0F2 C14 IO49NB1F4 K20 IO11NB0F0 K12 IO30PB0F2 C13 IO49PB1F4 L20 IO11PB0F0 J12 IO31NB0F2 H15 IO50NB1F4 A19 IO12NB0F1 G11 IO31PB0F2 J15 IO50PB1F4 B19 Bank 1 IO12PB0F1 H11 IO32NB0F2 A14 IO51NB1F4 H20 IO13NB0F1 G12 IO32PB0F2 B14 IO51PB1F4 J20 IO13PB0F1 H12 IO33NB0F2 K15 IO52NB1F4 B20 IO14NB0F1 A7 IO33PB0F2 L15 IO52PB1F4 A20 IO14PB0F1 B7 IO34NB0F3 D15 IO53NB1F4 F20 IO15NB0F1 H13 IO34PB0F3 D14 IO53PB1F4 E20 IO15PB0F1 J13 IO35NB0F3 A15 IO54NB1F5 B21 IO16NB0F1 C9 IO35PB0F3 B15 IO54PB1F5 A21 IO16PB0F1 D9 IO36NB0F3 B16 IO55NB1F5 K21 IO17NB0F1 F12 IO36PB0F3 A16 IO55PB1F5 J21 IO17PB0F1 F11 IO37NB0F3 G16 IO56NB1F5 D21 IO18NB0F1 E11 IO37PB0F3 G15 IO56PB1F5 C21 IO18PB0F1 E10 IO38NB0F3 D16 IO57NB1F5 G22 v2.3 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO57PB1F5 G21 IO77NB1F7 B29 IO96NB2F9 J32 IO58NB1F5 E22 IO77PB1F7 A29 IO96PB2F9 H32 IO58PB1F5 E21 IO78NB1F7 D28 IO97NB2F9 M27 IO59NB1F5 D22 IO78PB1F7 C28 IO97PB2F9 M26 IO59PB1F5 C22 IO79NB1F7 H25 IO98NB2F9 L30 IO60NB1F5 B23 IO79PB1F7 G25 IO98PB2F9 K30 IO60PB1F5 A23 IO80NB1F7 F27 IO99NB2F9 N25 IO61NB1F5 H22 IO80PB1F7 E27 IO99PB2F9 N26 IO61PB1F5 H21 IO81NB1F7 J25 IO100NB2F9 M29 IO62NB1F5 C24 IO81PB1F7 J24 IO100PB2F9 L29 IO62PB1F5 C23 IO82NB1F7 D29 IO101NB2F9 L33 IO63NB1F5 F23 IO82PB1F7 C29 IO101PB2F9 L32 IO63PB1F5 F22 IO83NB1F7 H26 IO102NB2F9 K34 IO64NB1F6 B24 IO83PB1F7 G26 IO102PB2F9 K33 IO64PB1F6 A24 IO84NB1F7 F28 IO103NB2F9 N28 IO65NB1F6 J22 IO84PB1F7 E28 IO103PB2F9 M28 IO65PB1F6 K22 IO85NB1F7 H27 IO104NB2F9 M34 IO66NB1F6 B25 IO85PB1F7 G27 IO104PB2F9 L34 IO66PB1F6 A25 IO105NB2F9 P27 IO67NB1F6 K23 IO86NB2F8 J28 IO105PB2F9 N27 IO67PB1F6 J23 IO86PB2F8 J27 IO106NB2F9 M32 IO68NB1F6 F24 IO87NB2F8 M25 IO106PB2F9 M31 IO68PB1F6 E24 IO87PB2F8 L25 IO107NB2F10 P25 IO69NB1F6 C27 IO88NB2F8 L26 IO107PB2F10 P26 IO69PB1F6 C26 IO88PB2F8 K26 IO108NB2F10 N33 IO70NB1F6 H24 IO89NB2F8 G31 IO108PB2F10 M33 Bank 2 IO70PB1F6 G24 IO89PB2F8 F31 IO109NB2F10 P29 IO71NB1F6 H23 IO90NB2F8 H29 IO109PB2F10 N29 IO71PB1F6 G23 IO90PB2F8 G29 IO110NB2F10 P30 IO72NB1F6 B28 IO91NB2F8 K28 IO110PB2F10 N30 IO72PB1F6 A28 IO91PB2F8 K27 IO111NB2F10 R24 IO73NB1F6 E26 IO92NB2F8 J30 IO111PB2F10 R25 IO73PB1F6 E25 IO92PB2F8 H30 IO112NB2F10 P31 IO74NB1F6 F26 IO93NB2F8 L28 IO112PB2F10 N31 IO74PB1F6 F25 IO93PB2F8 L27 IO113NB2F10 R28 IO75NB1F6 K25 IO94NB2F8 K29 IO113PB2F10 P28 IO75PB1F6 K24 IO94PB2F8 J29 IO114NB2F10 P32 IO76NB1F7 D27 IO95NB2F8 K31 IO114PB2F10 N32 IO76PB1F7 D26 IO95PB2F8 J31 IO115NB2F10 R30 v2.3 3-69 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO115PB2F10 R29 IO134PB3F12 V33 IO154NB3F14 AD32 IO116NB2F10 P34 IO135NB3F12 W25 IO154PB3F14 AC32 IO116PB2F10 P33 IO135PB3F12 W24 IO155NB3F14 AD29 IO117NB2F10 R27 IO136NB3F12 W31 IO155PB3F14 AC29 IO117PB2F10 R26 IO136PB3F12 W32 IO156NB3F14 AE30 IO118NB2F11 R34 IO137NB3F12 Y30 IO156PB3F14 AD30 IO118PB2F11 R33 IO137PB3F12 W30 IO157NB3F14 AC26 IO119NB2F11 T24 IO138NB3F12 Y29 IO157PB3F14 AB26 IO119PB2F11 T25 IO138PB3F12 W29 IO158NB3F14 AH33 IO120NB2F11 T33 IO139NB3F13 Y27 IO158PB3F14 AG33 IO120PB2F11 T34 IO139PB3F13 W27 IO159NB3F14 AD27 IO121NB2F11 T27 IO140NB3F13 AA33 IO159PB3F14 AC27 IO121PB2F11 T26 IO140PB3F13 Y33 IO160NB3F14 AG32 IO122NB2F11 T30 IO141NB3F13 Y25 IO160PB3F14 AF32 IO122PB2F11 T29 IO141PB3F13 Y24 IO161NB3F15 AG31 IO123NB2F11 U28 IO142NB3F13 AA31 IO161PB3F15 AF31 IO123PB2F11 T28 IO142PB3F13 Y31 IO162NB3F15 AF29 IO124NB2F11 T31 IO143NB3F13 AA28 IO162PB3F15 AE29 IO124PB2F11 T32 IO143PB3F13 Y28 IO163NB3F15 AE28 IO125NB2F11 U24 IO144NB3F13 AA34 IO163PB3F15 AD28 IO125PB2F11 U25 IO144PB3F13 Y34 IO164NB3F15 AG30 IO126NB2F11 U33 IO145NB3F13 AA26 IO164PB3F15 AF30 IO126PB2F11 U34 IO145PB3F13 Y26 IO165NB3F15 AE26 IO127NB2F11 U26 IO146NB3F13 AA29 IO165PB3F15 AD26 IO127PB2F11 U27 IO146PB3F13 AA30 IO166NB3F15 AJ30 IO128NB2F11 U31 IO147NB3F13 AB30 IO166PB3F15 AH30 IO128PB2F11 U32 Bank 3 3 -7 0 IO147PB3F13 AB29 IO167NB3F15 AG28 IO148NB3F13 AB32 IO167PB3F15 AF28 IO129NB3F12 V29 IO148PB3F13 AA32 IO168NB3F15 AF27 IO129PB3F12 U29 IO149NB3F13 AB27 IO168PB3F15 AE27 IO130NB3F12 V31 IO149PB3F13 AA27 IO169NB3F15 AH29 IO130PB3F12 V32 IO150NB3F14 AC31 IO169PB3F15 AG29 IO131NB3F12 V24 IO150PB3F14 AB31 IO170NB3F15 AD25 IO131PB3F12 V25 IO151NB3F14 AD33 IO170PB3F15 AC25 IO132NB3F12 W28 IO151PB3F14 AC33 IO132PB3F12 V28 IO152NB3F14 AC28 IO171NB4F16 AP29 IO133NB3F12 W26 IO152PB3F14 AB28 IO171PB4F16 AN29 IO133PB3F12 V26 IO153NB3F14 AB25 IO172NB4F16 AH26 IO134NB3F12 W33 IO153PB3F14 AA25 IO172PB4F16 AH27 v2.3 Bank 4 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO173NB4F16 AJ27 IO192PB4F17 AG22 IO212NB4F19/CLKEN AJ20 IO173PB4F16 AJ28 IO193NB4F18 AP23 IO212PB4F19/CLKEP AK20 IO174NB4F16 AL27 IO193PB4F18 AP24 IO213NB4F19/CLKFN AJ18 IO174PB4F16 AL28 IO194NB4F18 AN22 IO213PB4F19/CLKFP AJ19 IO175NB4F16 AM28 IO194PB4F18 AN23 IO175PB4F16 AM29 IO195NB4F18 AM23 IO176NB4F16 AG25 IO195PB4F18 AL23 IO214PB5F20/CLKGP AJ17 IO176PB4F16 AG26 IO196NB4F18 AF21 IO215NB5F20/CLKHN AJ15 IO177NB4F16 AK26 IO196PB4F18 AF22 IO215PB5F20/CLKHP AK15 IO177PB4F16 AK27 IO197NB4F18 AL22 IO216NB5F20 AD16 IO178NB4F16 AF25 IO197PB4F18 AM22 IO216PB5F20 AE17 IO178PB4F16 AE25 IO198NB4F18 AE21 IO217NB5F20 AM17 IO179NB4F16 AP28 IO198PB4F18 AE22 IO217PB5F20 AL17 IO179PB4F16 AN28 IO199NB4F18 AJ21 IO218NB5F20 AG16 IO180NB4F16 AJ25 IO199PB4F18 AJ22 IO218PB5F20 AF16 IO180PB4F16 AJ26 IO200NB4F18 AK21 IO219NB5F20 AM16 IO181NB4F17 AM26 IO200PB4F18 AK22 IO219PB5F20 AL16 IO181PB4F17 AM27 IO201NB4F18 AM21 IO220NB5F20 AP16 IO182NB4F17 AF24 IO201PB4F18 AL21 IO220PB5F20 AN16 IO182PB4F17 AE24 IO202NB4F18 AE20 IO221NB5F20 AN15 IO183NB4F17 AH24 IO202PB4F18 AD20 IO221PB5F20 AP15 IO183PB4F17 AH25 IO203NB4F19 AN21 IO222NB5F20 AD15 IO184NB4F17 AG23 IO203PB4F19 AP21 IO222PB5F20 AE16 IO184PB4F17 AG24 IO204NB4F19 AP20 IO223NB5F21 AL14 IO185NB4F17 AL25 IO204PB4F19 AN20 IO223PB5F21 AL15 IO185PB4F17 AL26 IO205NB4F19 AN19 IO224NB5F21 AN14 Bank 5 IO214NB5F20/CLKGN AJ16 IO186NB4F17 AP25 IO205PB4F19 AP19 IO224PB5F21 AP14 IO186PB4F17 AP26 IO206NB4F19 AG20 IO225NB5F21 AK13 IO187NB4F17 AK24 IO206PB4F19 AF20 IO225PB5F21 AK14 IO187PB4F17 AK25 IO207NB4F19 AL19 IO226NB5F21 AE15 IO188NB4F17 AF23 IO207PB4F19 AL20 IO226PB5F21 AF15 IO188PB4F17 AE23 IO208NB4F19 AG19 IO227NB5F21 AG14 IO189NB4F17 AN24 IO208PB4F19 AF19 IO227PB5F21 AG15 IO189PB4F17 AM24 IO209NB4F19 AN18 IO228NB5F21 AJ13 IO190NB4F17 AH22 IO209PB4F19 AP18 IO228PB5F21 AJ14 IO190PB4F17 AH23 IO210NB4F19 AE19 IO229NB5F21 AM13 IO191NB4F17 AJ23 IO210PB4F19 AD19 IO229PB5F21 AM14 IO191PB4F17 AJ24 IO211NB4F19 AL18 IO230NB5F21 AE14 IO192NB4F17 AG21 IO211PB4F19 AM18 IO230PB5F21 AF14 v2.3 3-71 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO231NB5F21 AN12 IO250PB5F23 AE11 IO269PB6F25 AF4 IO231PB5F21 AP12 IO251NB5F23 AK8 IO270NB6F25 AB9 IO232NB5F21 AG13 IO251PB5F23 AJ8 IO270PB6F25 AC9 IO232PB5F21 AH13 IO252NB5F23 AH8 IO271NB6F25 AC6 IO233NB5F21 AL12 IO252PB5F23 AH9 IO271PB6F25 AD6 IO233PB5F21 AL13 IO253NB5F23 AN6 IO272NB6F25 AB8 IO234NB5F21 AE13 IO253PB5F23 AP6 IO272PB6F25 AC8 IO234PB5F21 AF13 IO254NB5F23 AG9 IO273NB6F25 AE1 IO235NB5F22 AN11 IO254PB5F23 AG10 IO273PB6F25 AE2 IO235PB5F22 AP11 IO255NB5F23 AJ7 IO274NB6F25 AA10 IO236NB5F22 AM11 IO255PB5F23 AK7 IO274PB6F25 AB10 IO236PB5F22 AM12 IO256NB5F23 AL6 IO275NB6F25 AB7 IO237NB5F22 AJ11 IO256PB5F23 AM6 IO275PB6F25 AC7 IO237PB5F22 AJ12 IO276NB6F25 AD1 IO238NB5F22 AH11 IO257NB6F24 AG6 IO276PB6F25 AD2 IO238PB5F22 AH12 IO257PB6F24 AH6 IO277NB6F25 AC4 IO239NB5F22 AK10 IO258NB6F24 AD9 IO277PB6F25 AC3 IO239PB5F22 AK11 IO258PB6F24 AE9 IO278NB6F26 AA8 IO240NB5F22 AE12 IO259NB6F24 AF7 IO278PB6F26 AA9 IO240PB5F22 AF12 IO259PB6F24 AG7 IO279NB6F26 AB5 IO241NB5F22 AN10 IO260NB6F24 AH3 IO279PB6F26 AB6 IO241PB5F22 AP10 IO260PB6F24 AH4 IO280NB6F26 Y10 IO242NB5F22 AG11 IO261NB6F24 AH5 IO280PB6F26 Y11 IO242PB5F22 AG12 IO261PB6F24 AJ5 IO281NB6F26 AB3 IO243NB5F22 AL9 IO262NB6F24 AE6 IO281PB6F26 AB4 IO243PB5F22 AL10 IO262PB6F24 AF6 IO282NB6F26 Y7 IO244NB5F22 AM8 IO263NB6F24 AF5 IO282PB6F26 AA7 IO244PB5F22 AM9 IO263PB6F24 AG5 IO283NB6F26 AC2 IO245NB5F23 AH10 IO264NB6F24 AD8 IO283PB6F26 AC1 IO245PB5F23 AJ10 IO264PB6F24 AE8 IO284NB6F26 Y9 IO246NB5F23 AF10 IO265NB6F24 AF3 IO284PB6F26 Y8 IO246PB5F23 AF11 IO265PB6F24 AG3 IO285NB6F26 AA5 IO247NB5F23 AJ9 IO266NB6F24 AC10 IO285PB6F26 AA6 IO247PB5F23 AK9 IO266PB6F24 AD10 IO286NB6F26 W10 IO248NB5F23 AN7 IO267NB6F25 AD7 IO286PB6F26 W11 IO248PB5F23 AP7 IO267PB6F25 AE7 IO287NB6F26 AA3 IO249NB5F23 AL7 IO268NB6F25 AD5 IO287PB6F26 AA4 IO249PB5F23 AL8 IO268PB6F25 AE5 IO288NB6F26 W9 IO250NB5F23 AE10 IO269NB6F25 AE4 IO288PB6F26 W8 3 -7 2 Bank 6 v2.3 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO289NB6F27 AA1 IO308NB7F28 T11 IO327PB7F30 L5 IO289PB6F27 AA2 IO308PB7F28 T10 IO328NB7F30 N10 IO290NB6F27 W6 IO309NB7F28 T6 IO328PB7F30 N9 IO290PB6F27 Y6 IO309PB7F28 T7 IO329NB7F30 J4 IO291NB6F27 W5 IO310NB7F29 T9 IO329PB7F30 K4 IO291PB6F27 Y5 IO310PB7F29 T8 IO330NB7F30 J5 IO292NB6F27 V7 IO311NB7F29 N3 IO330PB7F30 K5 IO292PB6F27 W7 IO311PB7F29 P3 IO331NB7F30 M10 IO293NB6F27 W4 IO312NB7F29 P7 IO331PB7F30 M9 IO293PB6F27 Y4 IO312PB7F29 R7 IO332NB7F31 L8 IO294NB6F27 V10 IO313NB7F29 P6 IO332PB7F31 M8 IO294PB6F27 V11 IO313PB7F29 R6 IO333NB7F31 F2 IO295NB6F27 Y1 IO314NB7F29 M2 IO333PB7F31 F1 IO295PB6F27 Y2 IO314PB7F29 N2 IO334NB7F31 J6 IO296NB6F27 W1 IO315NB7F29 N4 IO334PB7F31 K6 IO296PB6F27 W2 IO315PB7F29 P4 IO335NB7F31 H4 IO297NB6F27 V1 IO316NB7F29 R9 IO335PB7F31 H3 IO297PB6F27 V2 IO316PB7F29 R8 IO336NB7F31 K7 IO298NB6F27 V9 IO317NB7F29 N5 IO336PB7F31 L7 IO298PB6F27 V8 IO317PB7F29 P5 IO337NB7F31 G4 IO299NB6F27 U4 IO318NB7F29 R10 IO337PB7F31 G3 IO299PB6F27 V4 IO318PB7F29 R11 IO338NB7F31 K9 IO319NB7F29 L2 IO338PB7F31 L9 Bank 7 IO300NB7F28 U10 IO319PB7F29 L1 IO339NB7F31 H6 IO300PB7F28 U11 IO320NB7F29 N8 IO339PB7F31 H5 IO301NB7F28 U2 IO320PB7F29 P8 IO340NB7F31 H7 IO301PB7F28 U1 IO321NB7F30 M6 IO340PB7F31 J7 IO302NB7F28 U6 IO321PB7F30 N6 IO341NB7F31 J8 IO302PB7F28 U7 IO322NB7F30 P10 IO341PB7F31 K8 IO303NB7F28 T3 IO322PB7F30 P9 IO303PB7F28 U3 IO323NB7F30 L3 GND A13 IO304NB7F28 U9 IO323PB7F30 M3 GND A2 IO304PB7F28 U8 IO324NB7F30 M7 GND A22 IO305NB7F28 R2 IO324PB7F30 N7 GND A27 IO305PB7F28 R1 IO325NB7F30 K2 GND A3 IO306NB7F28 R4 IO325PB7F30 K1 GND A31 IO306PB7F28 T4 IO326NB7F30 G2 GND A32 IO307NB7F28 R5 IO326PB7F30 H2 GND A33 IO307PB7F28 T5 IO327NB7F30 L6 GND A4 v2.3 Dedicated I/O 3-73 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND A8 GND AL1 GND AP33 GND AA14 GND AL11 GND AP4 GND AA15 GND AL2 GND AP8 GND AA16 GND AL24 GND B1 GND AA17 GND AL3 GND B2 GND AA18 GND AL31 GND B26 GND AA19 GND AL32 GND B3 GND AA20 GND AL33 GND B31 GND AA21 GND AL34 GND B32 GND AB1 GND AL4 GND B33 GND AB13 GND AM1 GND B34 GND AB22 GND AM10 GND B4 GND AB34 GND AM15 GND B9 GND AC12 GND AM2 GND C1 GND AC23 GND AM20 GND C10 GND AC30 GND AM25 GND C15 GND AC5 GND AM3 GND C2 GND AD11 GND AM31 GND C20 GND AD24 GND AM32 GND C25 GND AD31 GND AM33 GND C3 GND AD4 GND AM34 GND C31 GND AE3 GND AM4 GND C32 GND AE32 GND AN1 GND C33 GND AF2 GND AN2 GND C34 GND AF33 GND AN26 GND C4 GND AG1 GND AN3 GND D1 GND AG27 GND AN31 GND D11 GND AG34 GND AN32 GND D2 GND AG8 GND AN33 GND D24 GND AH28 GND AN34 GND D3 GND AH7 GND AN4 GND D31 GND AJ29 GND AN9 GND D32 GND AJ6 GND AP13 GND D33 GND AK12 GND AP2 GND D34 GND AK17 GND AP22 GND D4 GND AK18 GND AP27 GND E12 GND AK23 GND AP3 GND E17 GND AK30 GND AP31 GND E18 GND AK5 GND AP32 GND E23 3 -7 4 v2.3 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND E30 GND R20 GND W21 GND E5 GND R21 GND Y14 GND F29 GND R3 GND Y15 GND F30 GND R32 GND Y16 GND F6 GND T14 GND Y17 GND G28 GND T15 GND Y18 GND G7 GND T16 GND Y19 GND H1 GND T17 GND Y20 GND H34 GND T18 GND Y21 GND J2 GND T19 GND Y3 GND J33 GND T20 GND Y32 GND K3 GND T21 GND/LP G6 GND K32 GND U14 NC A17 GND L11 GND U15 NC A26 GND L24 GND U16 NC AB2 GND L31 GND U17 NC AB33 GND L4 GND U18 NC AC34 GND M12 GND U19 NC AD3 GND M23 GND U20 NC AD34 GND M30 GND U21 NC AE31 GND M5 GND U30 NC AE33 GND N1 GND U5 NC AE34 GND N13 GND V14 NC AF1 GND N22 GND V15 NC AF34 GND N34 GND V16 NC AG2 GND P14 GND V17 NC AG4 GND P15 GND V18 NC AH1 GND P16 GND V19 NC AH2 GND P17 GND V20 NC AH31 GND P18 GND V21 NC AH32 GND P19 GND V30 NC AH34 GND P20 GND V5 NC AJ1 GND P21 GND W14 NC AJ2 GND R14 GND W15 NC AJ3 GND R15 GND W16 NC AJ31 GND R16 GND W17 NC AJ32 GND R17 GND W18 NC AJ33 GND R18 GND W19 NC AJ34 GND R19 GND W20 NC AJ4 v2.3 3-75 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number NC AL29 NC V3 VCCA T13 NC AM19 NC V34 VCCA T22 NC AM7 NC W3 VCCA U13 NC AN13 NC W34 VCCA U22 NC AN17 PRA J17 VCCA V13 NC AN25 PRB F18 VCCA V22 NC AN27 PRC AD18 VCCA W13 NC AN8 PRD AH18 VCCA W22 NC AP17 TCK J9 VCCA Y13 NC AP9 TDI F7 VCCA Y22 NC B17 TDO L10 VCCDA AF26 NC B22 TMS H8 VCCDA AF9 NC B27 TRST E6 VCCDA AG17 NC B8 VCCA AA13 VCCDA AG18 NC D10 VCCA AA22 VCCDA AH14 NC D20 VCCA AB14 VCCDA AH15 NC D23 VCCA AB15 VCCDA AH17 NC D25 VCCA AB16 VCCDA AH20 NC F3 VCCA AB17 VCCDA AH21 NC F32 VCCA AB18 VCCDA AK29 NC F33 VCCA AB19 VCCDA AK6 NC F34 VCCA AB20 VCCDA E15 NC F4 VCCA AB21 VCCDA E29 NC G1 VCCA AF8 VCCDA E7 NC G32 VCCA AK28 VCCDA F15 NC G33 VCCA G30 VCCDA F21 NC G34 VCCA G5 VCCDA F5 NC H31 VCCA N14 VCCDA G20 NC H33 VCCA N15 VCCDA H17 NC J1 VCCA N16 VCCDA H18 NC J3 VCCA N17 VCCDA H28 NC J34 VCCA N18 VCCDA J18 NC M1 VCCA N19 VCCDA V27 NC M4 VCCA N20 VCCDA V6 NC P1 VCCA N21 VCCIB0 A5 NC P2 VCCA P13 VCCIB0 B5 NC R31 VCCA P22 VCCIB0 C5 NC T1 VCCA R13 VCCIB0 D5 NC T2 VCCA R22 VCCIB0 L12 3 -7 6 v2.3 Axcelerator Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number VCCIB0 L13 VCCIB3 AK34 VCCIB6 Y12 VCCIB0 L14 VCCIB3 V23 VCCIB7 E1 VCCIB0 M13 VCCIB3 W23 VCCIB7 E2 VCCIB0 M14 VCCIB3 Y23 VCCIB7 E3 VCCIB0 M15 VCCIB4 AC18 VCCIB7 E4 VCCIB0 M16 VCCIB4 AC19 VCCIB7 M11 VCCIB0 M17 VCCIB4 AC20 VCCIB7 N11 VCCIB1 A30 VCCIB4 AC21 VCCIB7 N12 VCCIB1 B30 VCCIB4 AC22 VCCIB7 P11 VCCIB1 C30 VCCIB4 AD21 VCCIB7 P12 VCCIB1 D30 VCCIB4 AD22 VCCIB7 R12 VCCIB1 L21 VCCIB4 AD23 VCCIB7 T12 VCCIB1 L22 VCCIB4 AL30 VCCIB7 U12 VCCIB1 L23 VCCIB4 AM30 VCCPLA J16 VCCIB1 M18 VCCIB4 AN30 VCCPLB K17 VCCIB1 M19 VCCIB4 AP30 VCCPLC J19 VCCIB1 M20 VCCIB5 AC13 VCCPLD L18 VCCIB1 M21 VCCIB5 AC14 VCCPLE AK19 VCCIB1 M22 VCCIB5 AC15 VCCPLF AE18 VCCIB2 E31 VCCIB5 AC16 VCCPLG AK16 VCCIB2 E32 VCCIB5 AC17 VCCPLH AF17 VCCIB2 E33 VCCIB5 AD12 VCOMPLA H16 VCCIB2 E34 VCCIB5 AD13 VCOMPLB L17 VCCIB2 M24 VCCIB5 AD14 VCOMPLC H19 VCCIB2 N23 VCCIB5 AL5 VCOMPLD K18 VCCIB2 N24 VCCIB5 AM5 VCOMPLE AH19 VCCIB2 P23 VCCIB5 AN5 VCOMPLF AF18 VCCIB2 P24 VCCIB5 AP5 VCOMPLG AH16 VCCIB2 R23 VCCIB6 AA11 VCOMPLH AD17 VCCIB2 T23 VCCIB6 AA12 VPUMP J26 VCCIB2 U23 VCCIB6 AB11 VCCIB3 AA23 VCCIB6 AB12 VCCIB3 AA24 VCCIB6 AC11 VCCIB3 AB23 VCCIB6 AK1 VCCIB3 AB24 VCCIB6 AK2 VCCIB3 AC24 VCCIB6 AK3 VCCIB3 AK31 VCCIB6 AK4 VCCIB3 AK32 VCCIB6 V12 VCCIB3 AK33 VCCIB6 W12 v2.3 3-77 Axcelerator Family FPGAs 208-Pin PQFP 208 1 208-Pin PQFP Figure 3-9 * 208-Pin PQFP 3 -7 8 v2.3 Axcelerator Family FPGAs 208-Pin PQFP 208-Pin PQFP AX250 Function Pin Number Bank 0 AX250 Function 208-Pin PQFP Pin Number AX250 Function Pin Number IO44NB2F2 131 IO77PB5F5/CLKHP 71 IO44PB2F2 133 IO78NB5F5 66 IO78PB5F5 67 IO02NB0F0 197 IO03NB0F0 198 IO03PB0F0 199 IO45NB3F3 127 IO86NB5F5 62 IO12NB0F0/HCLKAN 191 IO45PB3F3 129 IO87NB5F5 60 IO12PB0F0/HCLKAP 192 IO46NB3F3 126 IO87PB5F5 61 IO13NB0F0/HCLKBN 185 IO46PB3F3 128 IO88NB5F5 56 IO13PB0F0/HCLKBP 186 IO48NB3F3 122 IO88PB5F5 57 IO48PB3F3 123 IO89NB5F5 54 IO89PB5F5 55 Bank 1 Bank 3 IO14NB1F1/HCLKCN 180 IO50NB3F3 120 IO14PB1F1/HCLKCP 181 IO50PB3F3 121 IO15NB1F1/HCLKDN 174 IO55NB3F3 116 IO91NB6F6 47 IO15PB1F1/HCLKDP 175 IO55PB3F3 117 IO91PB6F6 49 IO16NB1F1 170 IO57NB3F3 114 IO92NB6F6 48 IO16PB1F1 171 IO57PB3F3 115 IO92PB6F6 50 IO24NB1F1 165 IO59NB3F3 110 IO93NB6F6 42 IO24PB1F1 166 IO59PB3F3 111 IO93PB6F6 43 IO26NB1F1 161 IO60NB3F3 108 IO94PB6F6 44 IO26PB1F1 162 IO60PB3F3 109 IO96NB6F6 40 IO27NB1F1 159 IO61NB3F3 106 IO96PB6F6 41 IO27PB1F1 160 IO61PB3F3 107 IO101NB6F6 35 IO101PB6F6 36 Bank 2 Bank 4 Bank 6 IO29NB2F2 151 IO62NB4F4 100 IO102PB6F6 37 IO29PB2F2 153 IO62PB4F4 103 IO103NB6F6 33 IO30NB2F2 152 IO63NB4F4 101 IO103PB6F6 34 IO30PB2F2 154 IO63PB4F4 102 IO105NB6F6 28 IO31PB2F2 148 IO64NB4F4 96 IO105PB6F6 30 IO32NB2F2 146 IO64PB4F4 97 IO106NB6F6 27 IO32PB2F2 147 IO72NB4F4 91 IO106PB6F6 29 IO34NB2F2 144 IO72PB4F4 92 IO34PB2F2 145 IO74NB4F4/CLKEN 87 IO107NB7F7 23 IO39NB2F2 139 IO74PB4F4/CLKEP 88 IO107PB7F7 25 IO39PB2F2 140 IO75NB4F4/CLKFN 81 IO108NB7F7 22 IO40PB2F2 141 IO75PB4F4/CLKFP 82 IO108PB7F7 24 IO41NB2F2 137 IO110NB7F7 18 IO41PB2F2 138 IO76NB5F5/CLKGN 76 IO110PB7F7 19 IO43NB2F2 132 IO76PB5F5/CLKGP 77 IO112NB7F7 16 IO43PB2F2 134 IO77NB5F5/CLKHN 70 IO112PB7F7 17 Bank 5 v2.3 Bank 7 3-79 Axcelerator Family FPGAs 208-Pin PQFP AX250 Function Pin Number AX250 Function Pin Number AX250 Function Pin Number IO117NB7F7 12 GND 125 VCCPLG 74 IO117PB7F7 13 GND 136 VCCPLH 72 IO119NB7F7 10 GND 143 VCCIB0 193 IO119PB7F7 11 GND 150 VCCIB0 200 IO121PB7F7 7 GND 155 VCCIB1 163 IO122NB7F7 5 GND 164 VCCIB1 172 IO122PB7F7 6 GND 169 VCCIB2 135 IO123NB7F7 3 GND 173 VCCIB2 149 IO123PB7F7 4 GND 194 VCCIB3 112 GND 196 VCCIB3 124 Dedicated I/O 3 -8 0 208-Pin PQFP 208-Pin PQFP VCCDA 1 GND 201 VCCIB4 89 VCCDA 26 GND/LP 208 VCCIB4 98 VCCDA 53 PRA 184 VCCIB5 58 VCCDA 63 PRB 183 VCCIB5 68 VCCDA 78 PRC 80 VCCIB6 31 VCCDA 95 PRD 79 VCCIB6 45 VCCDA 105 TCK 205 VCCIB7 8 VCCDA 130 TDI 204 VCCIB7 20 VCCDA 157 TDO 203 VCOMPLA 190 VCCDA 167 TMS 206 VCOMPLB 188 VCCDA 182 TRST 207 VCOMPLC 179 VCCDA 202 VCCA 2 VCOMPLD 177 GND 104 VCCA 52 VCOMPLE 86 GND 9 VCCA 156 VCOMPLF 84 GND 15 VCCA 14 VCOMPLG 75 GND 21 VCCA 38 VCOMPLH 73 GND 32 VCCA 64 VPUMP 158 GND 39 VCCA 93 GND 46 VCCA 118 GND 51 VCCA 142 GND 59 VCCA 168 GND 65 VCCA 195 GND 69 VCCPLA 189 GND 90 VCCPLB 187 GND 94 VCCPLC 178 GND 99 VCCPLD 176 GND 113 VCCPLE 85 GND 119 VCCPLF 83 v2.3 Axcelerator Family FPGAs 208-Pin PQFP 208-Pin PQFP AX500 Function Pin Number Bank 0 208-Pin PQFP AX500 Function Pin Number AX500 Function Pin Number IO62NB2F5 131 IO106PB5F10/CLKHP 71 IO62PB2F5 133 IO107NB5F10 66 IO107PB5F10 67 IO03NB0F0 198 IO03PB0F0 199 IO04NB0F0 197 IO63NB3F6 127 IO119NB5F11 62 IO19NB0F1/HCLKAN 191 IO63PB3F6 129 IO121NB5F11 60 IO19PB0F1/HCLKAP 192 IO64NB3F6 126 IO121PB5F11 61 IO20NB0F1/HCLKBN 185 IO64PB3F6 128 IO123NB5F11 56 IO20PB0F1/HCLKBP 186 IO66NB3F6 122 IO123PB5F11 57 IO66PB3F6 123 IO125NB5F11 54 IO125PB5F11 55 Bank 1 Bank 3 IO21NB1F2/HCLKCN 180 IO68NB3F6 120 IO21PB1F2/HCLKCP 181 IO68PB3F6 121 IO22NB1F2/HCLKDN 174 IO77NB3F7 116 IO127NB6F12 47 IO22PB1F2/HCLKDP 175 IO77PB3F7 117 IO127PB6F12 49 IO23NB1F2 170 IO79NB3F7 114 IO128NB6F12 48 IO23PB1F2 171 IO79PB3F7 115 IO128PB6F12 50 IO37NB1F3 165 IO81NB3F7 110 IO129NB6F12 42 IO37PB1F3 166 IO81PB3F7 111 IO129PB6F12 43 IO39NB1F3 161 IO82NB3F7 108 IO130PB6F12 44 IO39PB1F3 162 IO82PB3F7 109 IO132NB6F12 40 IO41NB1F3 159 IO83NB3F7 106 IO132PB6F12 41 IO41PB1F3 160 IO83PB3F7 107 IO141NB6F13 35 IO141PB6F13 36 Bank 2 Bank 4 Bank 6 IO43NB2F4 151 IO84PB4F8 103 IO142PB6F13 37 IO43PB2F4 153 IO85NB4F8 100 IO143NB6F13 33 IO44NB2F4 152 IO86NB4F8 101 IO143PB6F13 34 IO44PB2F4 154 IO86PB4F8 102 IO145NB6F13 28 IO45PB2F4 148 IO87NB4F8 96 IO145PB6F13 30 IO46NB2F4 146 IO87PB4F8 97 IO146NB6F13 27 IO46PB2F4 147 IO101NB4F9 91 IO146PB6F13 29 IO48NB2F4 144 IO101PB4F9 92 IO48PB2F4 145 IO103NB4F9/CLKEN 87 IO147NB7F14 23 IO57NB2F5 139 IO103PB4F9/CLKEP 88 IO147PB7F14 25 IO57PB2F5 140 IO104NB4F9/CLKFN 81 IO148NB7F14 22 IO58PB2F5 141 IO104PB4F9/CLKFP 82 IO148PB7F14 24 IO59NB2F5 137 IO150NB7F14 18 IO59PB2F5 138 IO105NB5F10/CLKGN 76 IO150PB7F14 19 IO61NB2F5 132 IO105PB5F10/CLKGP 77 IO152NB7F14 16 IO61PB2F5 134 IO106NB5F10/CLKHN 70 IO152PB7F14 17 Bank 5 v2.3 Bank 7 3-81 Axcelerator Family FPGAs 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO161NB7F15 12 GND 125 VCCPLG 74 IO161PB7F15 13 GND 143 VCCPLH 72 IO163NB7F15 10 GND 136 VCCIB0 200 IO163PB7F15 11 GND 150 VCCIB0 193 IO165PB7F15 7 GND 155 VCCIB1 172 IO166NB7F15 5 GND 164 VCCIB1 163 IO166PB7F15 6 GND 169 VCCIB2 149 IO167NB7F15 3 GND 173 VCCIB2 135 IO167PB7F15 4 GND 194 VCCIB3 124 GND 196 VCCIB3 112 Dedicated I/O 3 -8 2 VCCDA 1 GND 201 VCCIB4 98 VCCDA 26 GND/LP 208 VCCIB4 89 VCCDA 53 PRA 184 VCCIB5 68 VCCDA 63 PRB 183 VCCIB5 58 VCCDA 78 PRC 80 VCCIB6 45 VCCDA 95 PRD 79 VCCIB6 31 VCCDA 105 TCK 205 VCCIB7 20 VCCDA 130 TDI 204 VCCIB7 8 VCCDA 157 TDO 203 VCOMPLA 190 VCCDA 167 TMS 206 VCOMPLB 188 VCCDA 182 TRST 207 VCOMPLC 179 VCCDA 202 VCCA 2 VCOMPLD 177 GND 104 VCCA 14 VCOMPLE 86 GND 9 VCCA 38 VCOMPLF 84 GND 15 VCCA 52 VCOMPLG 75 GND 21 VCCA 64 VCOMPLH 73 GND 32 VCCA 93 VPUMP 158 GND 39 VCCA 118 GND 46 VCCA 142 GND 51 VCCA 156 GND 59 VCCA 168 GND 65 VCCA 195 GND 69 VCCPLA 189 GND 90 VCCPLB 187 GND 94 VCCPLC 178 GND 99 VCCPLD 176 GND 113 VCCPLE 85 GND 119 VCCPLF 83 v2.3 Axcelerator Family FPGAs 208-Pin CQFP 208 1 208-Pin PQFP Figure 3-10 * 208-Pin CQFP (Top View) v2.3 3-83 Axcelerator Family FPGAs 208-Pin CQFP 208-Pin CQFP AX250 Function Pin # Bank 0 AX250 Function Pin # AX250 Function Pin # IO43PB2F2 134 IO76PB5F5/CLKGP 77 IO02NB0F0 197 IO44NB2F2 131 IO77NB5F5/CLKHN 70 IO03NB0F0 198 IO44PB2F2 133 IO77PB5F5/CLKHP 71 IO03PB0F0 199 IO78NB5F5 66 IO12NB0F0/HCLKAN 191 IO45NB3F3 127 IO78PB5F5 67 IO12PB0F0/HCLKAP 192 IO45PB3F3 129 IO86NB5F5 62 IO13NB0F0/HCLKBN 185 IO46NB3F3 126 IO87NB5F5 60 IO13PB0F0/HCLKBP 186 IO46PB3F3 128 IO87PB5F5 61 IO48NB3F3 122 IO88NB5F5 56 Bank 1 Bank 3 IO14NB1F1/HCLKCN 180 IO48PB3F3 123 IO88PB5F5 57 IO14PB1F1/HCLKCP 181 IO50NB3F3 120 IO89NB5F5 54 IO15NB1F1/HCLKDN 174 IO50PB3F3 121 IO89PB5F5 55 IO15PB1F1/HCLKDP 175 IO55NB3F3 116 IO16NB1F1 170 IO55PB3F3 117 IO91NB6F6 47 IO16PB1F1 171 IO57NB3F3 114 IO91PB6F6 49 IO24NB1F1 165 IO57PB3F3 115 IO92NB6F6 48 IO24PB1F1 166 IO59NB3F3 110 IO92PB6F6 50 IO26NB1F1 161 IO59PB3F3 111 IO93NB6F6 42 IO26PB1F1 162 IO60NB3F3 108 IO93PB6F6 43 IO27NB1F1 159 IO60PB3F3 109 IO94PB6F6 44 IO27PB1F1 160 IO61NB3F3 106 IO96NB6F6 40 IO61PB3F3 107 IO96PB6F6 41 IO101NB6F6 35 Bank 2 3 -8 4 208-Pin CQFP Bank 6 IO29NB2F2 151 IO29PB2F2 153 IO62NB4F4 100 IO101PB6F6 36 IO30NB2F2 152 IO62PB4F4 103 IO102PB6F6 37 IO30PB2F2 154 IO63NB4F4 101 IO103NB6F6 33 IO31PB2F2 148 IO63PB4F4 102 IO103PB6F6 34 IO32NB2F2 146 IO64NB4F4 96 IO105NB6F6 28 IO32PB2F2 147 IO64PB4F4 97 IO105PB6F6 30 IO34NB2F2 144 IO72NB4F4 91 IO106NB6F6 27 IO34PB2F2 145 IO72PB4F4 92 IO106PB6F6 29 IO39NB2F2 139 IO74NB4F4/CLKEN 87 IO39PB2F2 140 IO74PB4F4/CLKEP 88 IO107NB7F7 23 IO40PB2F2 141 IO75NB4F4/CLKFN 81 IO107PB7F7 25 IO41NB2F2 137 IO75PB4F4/CLKFP 82 IO108NB7F7 22 IO41PB2F2 138 Bank 5 IO108PB7F7 24 IO43NB2F2 132 IO76NB5F5/CLKGN IO110NB7F7 18 Bank 4 v2.3 76 Bank 7 Axcelerator Family FPGAs 208-Pin CQFP 208-Pin CQFP 208-Pin CQFP AX250 Function Pin # AX250 Function Pin # AX250 Function Pin # IO110PB7F7 19 GND 194 VCCIB0 200 IO112NB7F7 16 GND 196 VCCIB1 163 IO112PB7F7 17 GND 201 VCCIB1 172 IO117NB7F7 12 GND/LP 208 VCCIB2 135 IO117PB7F7 13 PRA 184 VCCIB2 149 IO119NB7F7 10 PRB 183 VCCIB3 112 IO119PB7F7 11 PRC 80 VCCIB3 124 IO121PB7F7 7 PRD 79 VCCIB4 89 IO122NB7F7 5 TCK 205 VCCIB4 98 IO122PB7F7 6 TDI 204 VCCIB5 58 IO123NB7F7 3 TDO 203 VCCIB5 68 IO123PB7F7 4 TMS 206 VCCIB6 31 TRST 207 VCCIB6 45 Dedicated I/O GND 9 VCCA 2 VCCIB7 8 GND 15 VCCA 14 VCCIB7 20 GND 21 VCCA 38 VCCPLA 189 GND 32 VCCA 52 VCCPLB 187 GND 39 VCCA 64 VCCPLC 178 GND 46 VCCA 93 VCCPLD 176 GND 51 VCCA 118 VCCPLE 85 GND 59 VCCA 142 VCCPLF 83 GND 65 VCCA 156 VCCPLG 74 GND 69 VCCA 168 VCCPLH 72 GND 90 VCCA 195 VCOMPLA 190 GND 94 VCCDA 1 VCOMPLB 188 GND 99 VCCDA 26 VCOMPLC 179 GND 104 VCCDA 53 VCOMPLD 177 GND 113 VCCDA 63 VCOMPLE 86 GND 119 VCCDA 78 VCOMPLF 84 GND 125 VCCDA 95 VCOMPLG 75 GND 136 VCCDA 105 VCOMPLH 73 GND 143 VCCDA 130 VPUMP 158 GND 150 VCCDA 157 GND 155 VCCDA 167 GND 164 VCCDA 182 GND 169 VCCDA 202 GND 173 VCCIB0 193 v2.3 3-85 Axcelerator Family FPGAs 208 CQFP 208 CQFP AX500 Function Pin # Bank 0 AX500 Function Pin # AX500 Function Pin # IO61PB2F5 134 IO105PB5F10/CLKGP 77 IO03NB0F0 198 IO62NB2F5 131 IO106NB5F10/CLKHN 70 IO03PB0F0 199 IO62PB2F5 133 IO106PB5F10/CLKHP 71 IO04NB0F0 197 IO107NB5F10 66 IO19NB0F1/HCLKAN 191 IO63NB3F6 127 IO107PB5F10 67 IO19PB0F1/HCLKAP 192 IO63PB3F6 129 IO119NB5F11 62 IO20NB0F1/HCLKBN 185 IO64NB3F6 126 IO121NB5F11 60 IO20PB0F1/HCLKBP 186 IO64PB3F6 128 IO121PB5F11 61 IO66NB3F6 122 IO123NB5F11 56 Bank 1 Bank 3 IO21NB1F2/HCLKCN 180 IO66PB3F6 123 IO123PB5F11 57 IO21PB1F2/HCLKCP 181 IO68NB3F6 120 IO125NB5F11 54 IO22NB1F2/HCLKDN 174 IO68PB3F6 121 IO125PB5F11 55 IO22PB1F2/HCLKDP 175 IO77NB3F7 116 IO23NB1F2 170 IO77PB3F7 117 IO127NB6F12 47 IO23PB1F2 171 IO79NB3F7 114 IO127PB6F12 49 IO37NB1F3 165 IO79PB3F7 115 IO128NB6F12 48 IO37PB1F3 166 IO81NB3F7 110 IO128PB6F12 50 IO39NB1F3 161 IO81PB3F7 111 IO129NB6F12 42 IO39PB1F3 162 IO82NB3F7 108 IO129PB6F12 43 IO41NB1F3 159 IO82PB3F7 109 IO130PB6F12 44 IO41PB1F3 160 IO83NB3F7 106 IO132NB6F12 40 IO83PB3F7 107 IO132PB6F12 41 IO141NB6F13 35 Bank 2 3 -8 6 208 CQFP Bank 6 IO43NB2F4 151 IO43PB2F4 153 IO84PB4F8 103 IO141PB6F13 36 IO44NB2F4 152 IO85NB4F8 100 IO142PB6F13 37 IO44PB2F4 154 IO86NB4F8 101 IO143NB6F13 33 IO45PB2F4 148 IO86PB4F8 102 IO143PB6F13 34 IO46NB2F4 146 IO87NB4F8 96 IO145NB6F13 28 IO46PB2F4 147 IO87PB4F8 97 IO145PB6F13 30 IO48NB2F4 144 IO101NB4F9 91 IO146NB6F13 27 IO48PB2F4 145 IO101PB4F9 92 IO146PB6F13 29 IO57NB2F5 139 IO103NB4F9/CLKEN 87 IO57PB2F5 140 IO103PB4F9/CLKEP 88 IO147NB7F14 23 IO58PB2F5 141 IO104NB4F9/CLKFN 81 IO147PB7F14 25 IO59NB2F5 137 IO104PB4F9/CLKFP 82 IO148NB7F14 22 IO59PB2F5 138 Bank 5 IO148PB7F14 24 IO61NB2F5 132 IO150NB7F14 18 Bank 4 IO105NB5F10/CLKGN v2.3 76 Bank 7 Axcelerator Family FPGAs 208 CQFP 208 CQFP 208 CQFP AX500 Function Pin # AX500 Function Pin # AX500 Function Pin # IO150PB7F14 19 GND 173 VCCIB0 200 IO152NB7F14 16 GND 194 VCCIB1 163 IO152PB7F14 17 GND 196 VCCIB1 172 IO161NB7F15 12 GND 201 VCCIB2 135 IO161PB7F15 13 GND/LP 208 VCCIB2 149 IO163NB7F15 10 PRA 184 VCCIB3 112 IO163PB7F15 11 PRB 183 VCCIB3 124 IO165PB7F15 7 PRC 80 VCCIB4 89 IO166NB7F15 5 PRD 79 VCCIB4 98 IO166PB7F15 6 TCK 205 VCCIB5 58 IO167NB7F15 3 TDI 204 VCCIB5 68 IO167PB7F15 4 TDO 203 VCCIB6 31 TMS 206 VCCIB6 45 Dedicated I/O VCCDA 1 TRST 207 VCCIB7 8 GND 9 VCCA 2 VCCIB7 20 GND 15 VCCA 14 VCCPLA 189 GND 21 VCCA 38 VCCPLB 187 GND 32 VCCA 52 VCCPLC 178 GND 39 VCCA 64 VCCPLD 176 GND 46 VCCA 93 VCCPLE 85 GND 51 VCCA 118 VCCPLF 83 GND 59 VCCA 142 VCCPLG 74 GND 65 VCCA 156 VCCPLH 72 GND 69 VCCA 168 VCOMPLA 190 GND 90 VCCA 195 VCOMPLB 188 GND 94 VCCDA 26 VCOMPLC 179 GND 99 VCCDA 53 VCOMPLD 177 GND 104 VCCDA 63 VCOMPLE 86 GND 113 VCCDA 78 VCOMPLF 84 GND 119 VCCDA 95 VCOMPLG 75 GND 125 VCCDA 105 VCOMPLH 73 GND 136 VCCDA 130 VPUMP 158 GND 143 VCCDA 157 GND 150 VCCDA 167 GND 155 VCCDA 182 GND 164 VCCDA 202 GND 169 VCCIB0 193 v2.3 3-87 Axcelerator Family FPGAs 268 267 266 265 339 338 337 336 335 334 333 332 331 352 351 350 349 352-Pin CQFP Pin 1 1 2 3 4 264 263 262 261 Ceramic Tie Bar 41 42 43 44 45 46 47 48 49 223 222 221 220 219 218 217 216 215 352-Pin CQFP 180 179 178 177 Figure 3-11 * 352-Pin CQFP (Bottom View) 3 -8 8 v2.3 173 174 175 176 127 128 129 130 131 132 133 134 135 89 90 91 92 85 86 87 88 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP AX250 Function Pin # Bank 0 352-Pin CQFP AX250 Function Pin # AX250 Function Pin # IO25NB1F1 271 IO46PB3F3 220 IO00NB0F0 341 IO25PB1F1 272 IO47NB3F3 213 IO00PB0F0 342 IO27NB1F1 269 IO47PB3F3 214 IO01NB0F0 343 IO27PB1F1 270 IO48NB3F3 211 IO02NB0F0 337 IO48PB3F3 212 IO02PB0F0 338 IO29NB2F2 261 IO49NB3F3 207 IO04NB0F0 335 IO29PB2F2 262 IO49PB3F3 208 IO04PB0F0 336 IO30NB2F2 259 IO51NB3F3 205 IO06NB0F0 331 IO30PB2F2 260 IO51PB3F3 206 IO06PB0F0 332 IO31NB2F2 255 IO52NB3F3 201 IO08NB0F0 325 IO31PB2F2 256 IO52PB3F3 202 IO08PB0F0 326 IO33NB2F2 249 IO53NB3F3 199 IO10NB0F0 323 IO33PB2F2 250 IO53PB3F3 200 IO10PB0F0 324 IO34NB2F2 253 IO54NB3F3 195 IO12NB0F0/HCLKAN 319 IO34PB2F2 254 IO54PB3F3 196 IO12PB0F0/HCLKAP 320 IO35NB2F2 247 IO55NB3F3 193 IO13NB0F0/HCLKBN 313 IO35PB2F2 248 IO55PB3F3 194 IO13PB0F0/HCLKBP 314 IO36NB2F2 243 IO56NB3F3 187 IO36PB2F2 244 IO56PB3F3 188 Bank 1 Bank 2 IO14NB1F1/HCLKCN 305 IO37NB2F2 241 IO57NB3F3 189 IO14PB1F1/HCLKCP 306 IO37PB2F2 242 IO57PB3F3 190 IO15NB1F1/HCLKDN 299 IO38NB2F2 237 IO59NB3F3 183 IO15PB1F1/HCLKDP 300 IO38PB2F2 238 IO59PB3F3 184 IO16NB1F1 289 IO39NB2F2 235 IO60NB3F3 181 IO16PB1F1 290 IO39PB2F2 236 IO60PB3F3 182 IO17NB1F1 295 IO41NB2F2 231 IO61NB3F3 179 IO17PB1F1 296 IO41PB2F2 232 IO61PB3F3 180 IO18NB1F1 287 IO42NB2F2 229 IO18PB1F1 288 IO42PB2F2 230 IO62NB4F4 172 IO20NB1F1 283 IO43NB2F2 225 IO62PB4F4 173 IO20PB1F1 284 IO43PB2F2 226 IO64NB4F4 166 IO22NB1F1 277 IO44NB2F2 223 IO64PB4F4 167 IO22PB1F1 278 IO44PB2F2 224 IO65NB4F4 170 IO23NB1F1 281 IO65PB4F4 171 IO23PB1F1 282 IO45NB3F3 217 IO66NB4F4 164 IO24NB1F1 275 IO45PB3F3 218 IO66PB4F4 165 IO24PB1F1 276 IO46NB3F3 219 IO67NB4F4 160 Bank 3 v2.3 Bank 4 3-89 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP AX250 Function Pin # AX250 Function Pin # AX250 Function Pin # IO67PB4F4 161 IO90PB6F6 86 IO110PB7F7 35 IO68NB4F4 158 IO91NB6F6 84 IO111NB7F7 30 IO68PB4F4 159 IO91PB6F6 85 IO111PB7F7 31 IO70NB4F4 154 IO92NB6F6 78 IO113NB7F7 28 IO70PB4F4 155 IO92PB6F6 79 IO113PB7F7 29 IO72NB4F4 152 IO93NB6F6 82 IO114NB7F7 24 IO72PB4F4 153 IO93PB6F6 83 IO114PB7F7 25 IO73NB4F4 146 IO95NB6F6 76 IO115NB7F7 22 IO73PB4F4 147 IO95PB6F6 77 IO115PB7F7 23 IO74NB4F4/CLKEN 142 IO96NB6F6 72 IO116NB7F7 18 IO74PB4F4/CLKEP 143 IO96PB6F6 73 IO116PB7F7 19 IO75NB4F4/CLKFN 136 IO97NB6F6 70 IO117NB7F7 16 IO75PB4F4/CLKFP 137 IO97PB6F6 71 IO117PB7F7 17 IO98NB6F6 66 IO118NB7F7 12 Bank 5 IO76NB5F5/CLKGN 128 IO98PB6F6 67 IO118PB7F7 13 IO76PB5F5/CLKGP 129 IO99NB6F6 64 IO119NB7F7 10 IO77NB5F5/CLKHN 122 IO99PB6F6 65 IO119PB7F7 11 IO77PB5F5/CLKHP 123 IO100NB6F6 60 IO121NB7F7 6 IO78NB5F5 112 IO100PB6F6 61 IO121PB7F7 7 IO78PB5F5 113 IO101NB6F6 58 IO123NB7F7 4 IO79NB5F5 118 IO101PB6F6 59 IO123PB7F7 5 IO79PB5F5 119 IO103NB6F6 54 Dedicated I/O IO80NB5F5 110 IO103PB6F6 55 GND 1 IO80PB5F5 111 IO104NB6F6 52 GND 9 IO82NB5F5 106 IO104PB6F6 53 GND 15 IO82PB5F5 107 IO105NB6F6 48 GND 21 IO84NB5F5 100 IO105PB6F6 49 GND 27 IO84PB5F5 101 IO106NB6F6 46 GND 33 IO85NB5F5 104 IO106PB6F6 47 GND 39 IO85PB5F5 105 Bank 7 GND 45 IO86NB5F5 98 IO107NB7F7 40 GND 51 IO86PB5F5 99 IO107PB7F7 41 GND 57 IO87NB5F5 94 IO108NB7F7 42 GND 63 IO87PB5F5 95 IO108PB7F7 43 GND 69 IO89NB5F5 92 IO109NB7F7 36 GND 75 IO89PB5F5 93 IO109PB7F7 37 GND 81 IO110NB7F7 34 GND 88 Bank 6 3 -9 0 352-Pin CQFP v2.3 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP AX250 Function Pin # AX250 Function Pin # AX250 Function Pin # GND 89 GND 334 VCCA 209 GND 97 GND 340 VCCA 233 GND 103 GND 345 VCCA 251 GND 109 GND 352 VCCA 263 GND 115 NC 91 VCCA 279 GND 121 NC 117 VCCA 291 GND 133 NC 130 VCCA 329 GND 145 NC 131 VCCA 339 GND 151 NC 148 VCCDA 2 GND 157 NC 174 VCCDA 44 GND 163 NC 268 VCCDA 90 GND 169 NC 294 VCCDA 116 GND 176 NC 307 VCCDA 132 GND 177 NC 308 VCCDA 149 GND 186 NC 327 VCCDA 178 GND 192 NC 328 VCCDA 221 GND 198 PRA 312 VCCDA 266 GND 204 PRB 311 VCCDA 293 GND 210 PRC 135 VCCDA 309 GND 216 PRD 134 VCCDA 346 GND 222 TCK 349 VCCIB0 321 GND 228 TDI 348 VCCIB0 333 GND 234 TDO 347 VCCIB0 344 GND 240 TMS 350 VCCIB1 273 GND 246 TRST 351 VCCIB1 285 GND 252 VCCA 3 VCCIB1 297 GND 258 VCCA 14 VCCIB2 227 GND 264 VCCA 32 VCCIB2 239 GND 265 VCCA 56 VCCIB2 245 GND 274 VCCA 74 VCCIB2 257 GND 280 VCCA 87 VCCIB3 185 GND 286 VCCA 102 VCCIB3 197 GND 292 VCCA 114 VCCIB3 203 GND 298 VCCA 150 VCCIB3 215 GND 310 VCCA 162 VCCIB4 144 GND 322 VCCA 175 VCCIB4 156 GND 330 VCCA 191 VCCIB4 168 v2.3 3-91 Axcelerator Family FPGAs 352-Pin CQFP 3 -9 2 352-Pin CQFP 352-Pin CQFP AX500 Function Pin # IO37NB1F3 271 343 IO37PB1F3 272 IO03NB0F0 341 IO41NB1F3 269 50 IO03PB0F0 342 IO41PB1F3 270 VCCIB6 62 IO05NB0F0 337 VCCIB6 68 IO05PB0F0 338 IO43NB2F4 261 VCCIB6 80 IO07NB0F0 335 IO43PB2F4 262 VCCIB7 8 IO07PB0F0 336 IO45NB2F4 259 VCCIB7 20 IO09NB0F0 331 IO45PB2F4 260 VCCIB7 26 IO09PB0F0 332 IO47NB2F4 255 VCCIB7 38 IO15NB0F1 325 IO47PB2F4 256 VCCPLA 317 IO15PB0F1 326 IO49NB2F4 253 VCCPLB 315 IO17NB0F1 323 IO49PB2F4 254 VCCPLC 303 IO17PB0F1 324 IO50NB2F4 247 VCCPLD 301 IO19NB0F1/HCLKAN 319 IO50PB2F4 248 VCCPLE 140 IO19PB0F1/HCLKAP 320 IO51NB2F4 249 VCCPLF 138 IO20NB0F1/HCLKBN 313 IO51PB2F4 250 VCCPLG 126 IO20PB0F1/HCLKBP 314 IO53NB2F5 243 VCCPLH 124 Bank 1 IO53PB2F5 244 VCOMPLA 318 IO21NB1F2/HCLKCN 305 IO54NB2F5 241 VCOMPLB 316 IO21PB1F2/HCLKCP 306 IO54PB2F5 242 VCOMPLC 304 IO22NB1F2/HCLKDN 299 IO55NB2F5 237 VCOMPLD 302 IO22PB1F2/HCLKDP 300 IO55PB2F5 238 VCOMPLE 141 IO23NB1F2 289 IO57NB2F5 235 VCOMPLF 139 IO23PB1F2 290 IO57PB2F5 236 VCOMPLG 127 IO24NB1F2 295 IO58NB2F5 231 VCOMPLH 125 IO24PB1F2 296 IO58PB2F5 232 VPUMP 267 IO25NB1F2 287 IO59NB2F5 229 IO25PB1F2 288 IO59PB2F5 230 IO27NB1F2 283 IO61NB2F5 225 IO27PB1F2 284 IO61PB2F5 226 IO29NB1F2 281 IO62NB2F5 223 IO29PB1F2 282 IO62PB2F5 224 IO31NB1F2 277 IO31PB1F2 278 IO63NB3F6 217 IO35NB1F3 275 IO63PB3F6 218 IO35PB1F3 276 IO64NB3F6 219 AX250 Function Pin # VCCIB5 96 VCCIB5 108 IO00PB0F0 VCCIB5 120 VCCIB6 AX500 Function Pin # Bank 0 v2.3 Bank 2 Bank 3 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP AX500 Function Pin # AX500 Function Pin # AX500 Function Pin # IO64PB3F6 220 IO95PB4F9 161 IO126PB6F12 86 IO65NB3F6 213 IO97NB4F9 158 IO127NB6F12 84 IO65PB3F6 214 IO97PB4F9 159 IO127PB6F12 85 IO67NB3F6 207 IO99NB4F9 154 IO129NB6F12 82 IO67PB3F6 208 IO99PB4F9 155 IO129PB6F12 83 IO68NB3F6 211 IO100NB4F9 146 IO131NB6F12 78 IO68PB3F6 212 IO100PB4F9 147 IO131PB6F12 79 IO69NB3F6 205 IO101NB4F9 152 IO133NB6F12 76 IO69PB3F6 206 IO101PB4F9 153 IO133PB6F12 77 IO71NB3F6 201 IO103NB4F9/CLKEN 142 IO134NB6F12 72 IO71PB3F6 202 IO103PB4F9/CLKEP 143 IO134PB6F12 73 IO73NB3F6 199 IO104NB4F9/CLKFN 136 IO135NB6F12 70 IO73PB3F6 200 IO104PB4F9/CLKFP 137 IO135PB6F12 71 IO75NB3F7 193 Bank 5 IO137NB6F13 66 IO75PB3F7 194 IO105NB5F10/CLKGN 128 IO137PB6F13 67 IO76NB3F7 195 IO105PB5F10/CLKGP 129 IO138NB6F13 64 IO76PB3F7 196 IO106NB5F10/CLKHN 122 IO138PB6F13 65 IO77NB3F7 189 IO106PB5F10/CLKHP 123 IO139NB6F13 60 IO77PB3F7 190 IO107NB5F10 118 IO139PB6F13 61 IO79NB3F7 187 IO107PB5F10 119 IO141NB6F13 54 IO79PB3F7 188 IO114NB5F11 112 IO141PB6F13 55 IO80NB3F7 183 IO114PB5F11 113 IO142NB6F13 58 IO80PB3F7 184 IO115NB5F11 110 IO142PB6F13 59 IO81NB3F7 181 IO115PB5F11 111 IO143NB6F13 52 IO81PB3F7 182 IO116NB5F11 106 IO143PB6F13 53 IO83NB3F7 179 IO116PB5F11 107 IO145NB6F13 48 IO83PB3F7 180 IO117NB5F11 104 IO145PB6F13 49 IO117PB5F11 105 IO146NB6F13 46 IO146PB6F13 47 Bank 4 IO85NB4F8 172 IO119NB5F11 100 IO85PB4F8 173 IO119PB5F11 101 IO87NB4F8 170 IO121NB5F11 98 IO147NB7F14 40 IO87PB4F8 171 IO121PB5F11 99 IO147PB7F14 41 IO89NB4F8 166 IO123NB5F11 94 IO148NB7F14 42 IO89PB4F8 167 IO123PB5F11 95 IO148PB7F14 43 IO94NB4F9 164 IO125NB5F11 92 IO149NB7F14 36 IO94PB4F9 165 IO125PB5F11 93 IO149PB7F14 37 IO95NB4F9 160 IO151NB7F14 30 Bank 6 v2.3 Bank 7 3-93 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP AX500 Function Pin # AX500 Function Pin # AX500 Function Pin # IO151PB7F14 31 GND 89 GND 334 IO152NB7F14 34 GND 97 GND 340 IO152PB7F14 35 GND 103 GND 345 IO153NB7F14 28 GND 109 GND/LP 352 IO153PB7F14 29 GND 115 NC 91 IO155NB7F14 24 GND 121 NC 117 IO155PB7F14 25 GND 133 NC 130 IO157NB7F14 22 GND 145 NC 131 IO157PB7F14 23 GND 151 NC 148 IO159NB7F15 16 GND 157 NC 174 IO159PB7F15 17 GND 163 NC 268 IO160NB7F15 18 GND 169 NC 294 IO160PB7F15 19 GND 176 NC 307 IO161NB7F15 12 GND 177 NC 308 IO161PB7F15 13 GND 186 NC 327 IO163NB7F15 10 GND 192 NC 328 IO163PB7F15 11 GND 198 PRA 312 IO165NB7F15 6 GND 204 PRB 311 IO165PB7F15 7 GND 210 PRC 135 IO167NB7F15 4 GND 216 PRD 134 IO167PB7F15 5 GND 222 TCK 349 GND 228 TDI 348 Dedicated I/O 3 -9 4 352-Pin CQFP GND 1 GND 234 TDO 347 GND 9 GND 240 TMS 350 GND 15 GND 246 TRST 351 GND 21 GND 252 VCCA 3 GND 27 GND 258 VCCA 14 GND 33 GND 264 VCCA 32 GND 39 GND 265 VCCA 56 GND 45 GND 274 VCCA 74 GND 51 GND 280 VCCA 87 GND 57 GND 286 VCCA 102 GND 63 GND 292 VCCA 114 GND 69 GND 298 VCCA 150 GND 75 GND 310 VCCA 162 GND 81 GND 322 VCCA 175 GND 88 GND 330 VCCA 191 v2.3 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP AX500 Function Pin # AX500 Function Pin # VCCA 209 VCCIB5 96 VCCA 233 VCCIB5 108 IO02NB0F0 341 VCCA 251 VCCIB5 120 IO02PB0F0 342 VCCA 263 VCCIB6 50 IO03PB0F0 343 VCCA 279 VCCIB6 62 IO04NB0F0 337 VCCA 291 VCCIB6 68 IO04PB0F0 338 VCCA 329 VCCIB6 80 IO08NB0F0 331 VCCA 339 VCCIB7 8 IO08PB0F0 332 VCCDA 2 VCCIB7 20 IO09NB0F0 335 VCCDA 44 VCCIB7 26 IO09PB0F0 336 VCCDA 90 VCCIB7 38 IO24NB0F2 325 VCCDA 116 VCCPLA 317 IO24PB0F2 326 VCCDA 132 VCCPLB 315 IO25NB0F2 323 VCCDA 149 VCCPLC 303 IO25PB0F2 324 VCCDA 178 VCCPLD 301 IO30NB0F2/HCLKAN 319 VCCDA 221 VCCPLE 140 IO30PB0F2/HCLKAP 320 VCCDA 266 VCCPLF 138 IO31NB0F2/HCLKBN 313 VCCDA 293 VCCPLG 126 IO31PB0F2/HCLKBP 314 VCCDA 309 VCCPLH 124 Bank 1 VCCDA 346 VCOMPLA 318 IO32NB1F3/HCLKCN 305 VCCIB0 321 VCOMPLB 316 IO32PB1F3/HCLKCP 306 VCCIB0 333 VCOMPLC 304 IO33NB1F3/HCLKDN 299 VCCIB0 344 VCOMPLD 302 IO33PB1F3/HCLKDP 300 VCCIB1 273 VCOMPLE 141 IO38NB1F3 295 VCCIB1 285 VCOMPLF 139 IO38PB1F3 296 VCCIB1 297 VCOMPLG 127 IO54NB1F5 287 VCCIB2 227 VCOMPLH 125 IO54PB1F5 288 VCCIB2 239 VPUMP 267 IO55NB1F5 289 VCCIB2 245 IO55PB1F5 290 VCCIB2 257 IO56NB1F5 281 VCCIB3 185 IO56PB1F5 282 VCCIB3 197 IO57NB1F5 283 VCCIB3 203 IO57PB1F5 284 VCCIB3 215 IO59NB1F5 277 VCCIB4 144 IO59PB1F5 278 VCCIB4 156 IO60NB1F5 275 VCCIB4 168 IO60PB1F5 276 v2.3 AX1000 Function Pin # Bank 0 3-95 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP AX1000 Function Pin # AX1000 Function Pin # AX1000 Function Pin # IO61NB1F5 271 IO97PB3F9 220 IO134PB4F12 161 IO61PB1F5 272 IO99NB3F9 213 IO136NB4F12 158 IO63NB1F5 269 IO99PB3F9 214 IO136PB4F12 159 IO63PB1F5 270 IO108NB3F10 211 IO137NB4F12 154 IO108PB3F10 212 IO137PB4F12 155 Bank 2 IO64NB2F6 259 IO109NB3F10 207 IO138NB4F12 152 IO64PB2F6 260 IO109PB3F10 208 IO138PB4F12 153 IO67NB2F6 261 IO111NB3F10 205 IO153NB4F14 146 IO67PB2F6 262 IO111PB3F10 206 IO153PB4F14 147 IO68NB2F6 255 IO112NB3F10 199 IO159NB4F14/CLKEN 142 IO68PB2F6 256 IO112PB3F10 200 IO159PB4F14/CLKEP 143 IO69NB2F6 253 IO113NB3F10 201 IO160NB4F14/CLKFN 136 IO69PB2F6 254 IO113PB3F10 202 IO160PB4F14/CLKFP 137 IO74NB2F7 249 IO115NB3F10 195 Bank 5 IO74PB2F7 250 IO115PB3F10 196 IO161NB5F15/CLKGN 128 IO75NB2F7 247 IO116NB3F10 193 IO161PB5F15/CLKGP 129 IO75PB2F7 248 IO116PB3F10 194 IO162NB5F15/CLKHN 122 IO76NB2F7 243 IO117NB3F10 189 IO162PB5F15/CLKHP 123 IO76PB2F7 244 IO117PB3F10 190 IO167NB5F15 118 IO77NB2F7 241 IO124NB3F11 183 IO167PB5F15 119 IO77PB2F7 242 IO124PB3F11 184 IO183NB5F17 110 IO78NB2F7 237 IO125NB3F11 187 IO183PB5F17 111 IO78PB2F7 238 IO125PB3F11 188 IO184NB5F17 112 IO79NB2F7 235 IO127NB3F11 181 IO184PB5F17 113 IO79PB2F7 236 IO127PB3F11 182 IO185NB5F17 104 IO82NB2F7 231 IO128NB3F11 179 IO185PB5F17 105 IO82PB2F7 232 IO128PB3F11 180 IO186NB5F17 106 IO83NB2F7 229 IO186PB5F17 107 IO83PB2F7 230 IO130NB4F12 172 IO187NB5F17 98 IO94NB2F8 225 IO130PB4F12 173 IO187PB5F17 99 IO94PB2F8 226 IO131NB4F12 170 IO188NB5F17 100 IO95NB2F8 223 IO131PB4F12 171 IO188PB5F17 101 IO95PB2F8 224 IO132NB4F12 166 IO190NB5F17 94 IO132PB4F12 167 IO190PB5F17 95 Bank 3 3 -9 6 352-Pin CQFP Bank 4 IO96NB3F9 217 IO133NB4F12 164 IO192NB5F17 92 IO96PB3F9 218 IO133PB4F12 165 IO192PB5F17 93 IO97NB3F9 219 IO134NB4F12 160 v2.3 Bank 6 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP AX1000 Function Pin # AX1000 Function Pin # AX1000 Function Pin # IO193PB6F18 86 IO238PB7F22 37 GND 89 IO194NB6F18 84 IO240NB7F22 30 GND 97 IO194PB6F18 85 IO240PB7F22 31 GND 103 IO196NB6F18 78 IO241NB7F22 28 GND 109 IO196PB6F18 79 IO241PB7F22 29 GND 115 IO197NB6F18 82 IO242NB7F22 24 GND 121 IO197PB6F18 83 IO242PB7F22 25 GND 133 IO198NB6F18 76 IO244NB7F22 22 GND 145 IO198PB6F18 77 IO244PB7F22 23 GND 151 IO203NB6F19 72 IO245NB7F22 18 GND 157 IO203PB6F19 73 IO245PB7F22 19 GND 163 IO204NB6F19 70 IO246NB7F22 16 GND 169 IO204PB6F19 71 IO246PB7F22 17 GND 176 IO205NB6F19 66 IO249NB7F23 12 GND 177 IO205PB6F19 67 IO249PB7F23 13 GND 186 IO206NB6F19 64 IO250NB7F23 10 GND 192 IO206PB6F19 65 IO250PB7F23 11 GND 198 IO207NB6F19 60 IO256NB7F23 4 GND 204 IO207PB6F19 61 IO256PB7F23 5 GND 210 IO208NB6F19 58 IO257NB7F23 6 GND 216 IO208PB6F19 59 IO257PB7F23 7 GND 222 IO211NB6F19 54 Dedicated I/O GND 228 IO211PB6F19 55 GND 1 GND 234 IO212NB6F19 52 GND 9 GND 240 IO212PB6F19 53 GND 15 GND 246 IO223NB6F20 48 GND 21 GND 252 IO223PB6F20 49 GND 27 GND 258 IO224NB6F20 46 GND 33 GND 264 IO224PB6F20 47 GND 39 GND 265 GND 45 GND 274 Bank 7 IO225NB7F21 40 GND 51 GND 280 IO225PB7F21 41 GND 57 GND 286 IO226NB7F21 42 GND 63 GND 292 IO226PB7F21 43 GND 69 GND 298 IO237NB7F22 34 GND 75 GND 310 IO237PB7F22 35 GND 81 GND 322 IO238NB7F22 36 GND 88 GND 330 v2.3 3-97 Axcelerator Family FPGAs 352-Pin CQFP 3 -9 8 352-Pin CQFP 352-Pin CQFP AX1000 Function Pin # AX1000 Function Pin # AX1000 Function Pin # GND 334 VCCA 291 VCCIB5 96 GND 340 VCCA 329 VCCIB5 108 GND 345 VCCA 339 VCCIB5 120 GND 352 VCCDA 2 VCCIB6 50 NC 91 VCCDA 44 VCCIB6 62 NC 130 VCCDA 90 VCCIB6 68 NC 131 VCCDA 116 VCCIB6 80 NC 174 VCCDA 117 VCCIB7 8 NC 268 VCCDA 132 VCCIB7 20 NC 307 VCCDA 148 VCCIB7 26 NC 308 VCCDA 149 VCCIB7 38 PRA 312 VCCDA 178 VCCPLA 317 PRB 311 VCCDA 221 VCCPLB 315 PRC 135 VCCDA 266 VCCPLC 303 PRD 134 VCCDA 293 VCCPLD 301 TCK 349 VCCDA 294 VCCPLE 140 TDI 348 VCCDA 309 VCCPLF 138 TDO 347 VCCDA 327 VCCPLG 126 TMS 350 VCCDA 328 VCCPLH 124 TRST 351 VCCDA 346 VCOMPLA 318 VCCA 3 VCCIB0 321 VCOMPLB 316 VCCA 14 VCCIB0 333 VCOMPLC 304 VCCA 32 VCCIB0 344 VCOMPLD 302 VCCA 56 VCCIB1 273 VCOMPLE 141 VCCA 74 VCCIB1 285 VCOMPLF 139 VCCA 87 VCCIB1 297 VCOMPLG 127 VCCA 102 VCCIB2 227 VCOMPLH 125 VCCA 114 VCCIB2 239 VPUMP 267 VCCA 150 VCCIB2 245 VCCA 162 VCCIB2 257 VCCA 175 VCCIB3 185 VCCA 191 VCCIB3 197 VCCA 209 VCCIB3 203 VCCA 233 VCCIB3 215 VCCA 251 VCCIB4 144 VCCA 263 VCCIB4 156 VCCA 279 VCCIB4 168 v2.3 Axcelerator Family FPGAs 352-Pin CQFP AX2000 Function 352-Pin CQFP Pin Number AX2000 Function 352-Pin CQFP Pin Number Bank 2 Bank 0 AX2000 Function Pin Number IO142PB3F13 208 IO01NB0F0 341 IO87NB2F8 261 IO145NB3F13 199 IO01PB0F0 342 IO87PB2F8 262 IO145PB3F13 200 IO02PB0F0 343 IO88NB2F8 255 IO146NB3F13 201 IO04NB0F0 337 IO88PB2F8 256 IO146PB3F13 202 IO04PB0F0 338 IO89NB2F8 259 IO147NB3F13 193 IO05NB0F0 335 IO89PB2F8 260 IO147PB3F13 194 IO05PB0F0 336 IO91NB2F8 253 IO148NB3F13 195 IO08NB0F0 331 IO91PB2F8 254 IO148PB3F13 196 IO08PB0F0 332 IO99NB2F9 249 IO149NB3F13 189 IO37NB0F3 325 IO99PB2F9 250 IO149PB3F13 190 IO37PB0F3 326 IO100NB2F9 247 IO161NB3F15 183 IO38NB0F3 323 IO100PB2F9 248 IO161PB3F15 184 IO38PB0F3 324 IO107NB2F10 243 IO163NB3F15 187 IO41NB0F3/HCLKAN 319 IO107PB2F10 244 IO163PB3F15 188 IO41PB0F3/HCLKAP 320 IO110NB2F10 241 IO165NB3F15 181 IO42NB0F3/HCLKBN 313 IO110PB2F10 242 IO165PB3F15 182 IO42PB0F3/HCLKBP 314 IO111NB2F10 237 IO167NB3F15 179 IO111PB2F10 238 IO167PB3F15 180 Bank 1 IO43NB1F4/HCLKCN 305 IO112NB2F10 235 IO43PB1F4/HCLKCP 306 IO112PB2F10 236 IO181NB4F17 172 IO44NB1F4/HCLKDN 299 IO113NB2F10 231 IO181PB4F17 173 IO44PB1F4/HCLKDP 300 IO113PB2F10 232 IO182NB4F17 170 IO48NB1F4 295 IO114NB2F10 229 IO182PB4F17 171 IO48PB1F4 296 IO114PB2F10 230 IO183NB4F17 166 IO65NB1F6 283 IO115NB2F10 225 IO183PB4F17 167 IO65PB1F6 284 IO115PB2F10 226 IO184NB4F17 164 IO66NB1F6 289 IO117NB2F10 223 IO184PB4F17 165 IO66PB1F6 290 IO117PB2F10 224 IO185NB4F17 160 IO68NB1F6 287 IO185PB4F17 161 IO68PB1F6 288 IO190NB4F17 158 Bank 3 IO129NB3F12 219 Bank 4 IO69NB1F6 275 IO129PB3F12 220 IO190PB4F17 159 IO69PB1F6 276 IO132NB3F12 217 IO191NB4F17 154 IO70NB1F6 281 IO132PB3F12 218 IO191PB4F17 155 IO70PB1F6 282 IO137NB3F12 213 IO192NB4F17 152 IO71NB1F6 277 IO137PB3F12 214 IO192PB4F17 153 IO71PB1F6 278 IO139NB3F13 211 IO207NB4F19 146 IO73NB1F6 269 IO139PB3F13 212 IO207PB4F19 147 IO73PB1F6 270 IO141NB3F13 205 IO212NB4F19/CLKEN 142 IO74NB1F6 271 IO141PB3F13 206 IO212PB4F19/CLKEP 143 IO74PB1F6 272 IO142NB3F13 207 IO213NB4F19/CLKFN 136 v2.3 3-99 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO213PB4F19/CLKFP 137 IO282PB6F26 65 IO341PB7F31 5 IO284NB6F26 60 Bank 5 Dedicated I/O IO214NB5F20/CLKGN 128 IO284PB6F26 61 GND 1 IO214PB5F20/CLKGP 129 IO285NB6F26 58 GND 9 IO215NB5F20/CLKHN 122 IO285PB6F26 59 GND 15 IO215PB5F20/CLKHP 123 IO286NB6F26 54 GND 21 IO217NB5F20 118 IO286PB6F26 55 GND 27 IO217PB5F20 119 IO287NB6F26 52 GND 33 IO236NB5F22 110 IO287PB6F26 53 GND 39 IO236PB5F22 111 IO294NB6F27 48 GND 45 IO237NB5F22 112 IO294PB6F27 49 GND 51 IO237PB5F22 113 IO296NB6F27 46 GND 57 IO238NB5F22 104 IO296PB6F27 47 GND 63 IO238PB5F22 105 GND 69 IO239NB5F22 106 42 GND 75 IO300NB7F28 IO239PB5F22 107 IO300PB7F28 43 GND 81 IO240NB5F22 100 IO303NB7F28 40 GND 88 IO240PB5F22 101 IO303PB7F28 41 GND 89 IO242NB5F22 94 IO310NB7F29 34 GND 97 IO242PB5F22 95 IO310PB7F29 35 GND 103 IO243NB5F22 98 IO311NB7F29 36 GND 109 IO243PB5F22 99 IO311PB7F29 37 GND 115 IO244NB5F22 92 IO312NB7F29 28 GND 121 IO244PB5F22 93 Bank 6 3 -1 0 0 Bank 7 IO312PB7F29 29 GND 133 IO315NB7F29 30 GND 145 IO257PB6F24 86 IO315PB7F29 31 GND 151 IO258NB6F24 84 IO316NB7F29 22 GND 157 IO258PB6F24 85 IO316PB7F29 23 GND 163 IO261NB6F24 82 IO317NB7F29 24 GND 169 IO261PB6F24 83 IO317PB7F29 25 GND 176 IO262NB6F24 78 IO318NB7F29 18 GND 177 IO262PB6F24 79 IO318PB7F29 19 GND 186 IO265NB6F24 76 IO320NB7F29 16 GND 192 IO265PB6F24 77 IO320PB7F29 17 GND 198 IO279NB6F26 72 IO334NB7F31 10 GND 204 IO279PB6F26 73 IO334PB7F31 11 GND 210 IO280NB6F26 70 IO335NB7F31 12 GND 216 IO280PB6F26 71 IO335PB7F31 13 GND 222 IO281NB6F26 66 IO338NB7F31 6 GND 228 IO281PB6F26 67 IO338PB7F31 7 GND 234 IO282NB6F26 64 IO341NB7F31 4 GND 240 v2.3 Axcelerator Family FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND 246 VCCA 263 VCCIB3 203 GND 252 VCCA 279 VCCIB3 215 GND 258 VCCA 291 VCCIB4 144 GND 264 VCCA 329 VCCIB4 156 GND 265 VCCA 339 VCCIB4 168 GND 274 VCCDA 2 VCCIB5 96 GND 280 VCCDA 44 VCCIB5 108 GND 286 VCCDA 90 VCCIB5 120 GND 292 VCCDA 91 VCCIB6 50 GND 298 VCCDA 116 VCCIB6 62 GND 310 VCCDA 117 VCCIB6 68 GND 322 VCCDA 130 VCCIB6 80 GND 330 VCCDA 131 VCCIB7 8 GND 334 VCCDA 132 VCCIB7 20 GND 340 VCCDA 148 VCCIB7 26 GND 345 VCCDA 149 VCCIB7 38 GND 352 VCCDA 174 VCCPLA 317 PRA 312 VCCDA 178 VCCPLB 315 PRB 311 VCCDA 221 VCCPLC 303 PRC 135 VCCDA 266 VCCPLD 301 PRD 134 VCCDA 268 VCCPLE 140 TCK 349 VCCDA 293 VCCPLF 138 TDI 348 VCCDA 294 VCCPLG 126 TDO 347 VCCDA 307 VCCPLH 124 TMS 350 VCCDA 308 VCOMPLA 318 TRST 351 VCCDA 309 VCOMPLB 316 VCCA 3 VCCDA 327 VCOMPLC 304 VCCA 14 VCCDA 328 VCOMPLD 302 VCCA 32 VCCDA 346 VCOMPLE 141 VCCA 56 VCCIB0 321 VCOMPLF 139 VCCA 74 VCCIB0 333 VCOMPLG 127 VCCA 87 VCCIB0 344 VCOMPLH 125 VCCA 102 VCCIB1 273 VPUMP 267 VCCA 114 VCCIB1 285 VCCA 150 VCCIB1 297 VCCA 162 VCCIB2 227 VCCA 175 VCCIB2 239 VCCA 191 VCCIB2 245 VCCA 209 VCCIB2 257 VCCA 233 VCCIB3 185 VCCA 251 VCCIB3 197 v2.3 3-101 Axcelerator Family FPGAs 624-Pin CCGA 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Figure 3-12 * 624-Pin CCGA (Bottom View) 3 -1 0 2 v2.3 Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA AX1000 Function Pin Number Bank 0 624-Pin CCGA AX1000 Function Pin Number AX1000 Function Pin Number IO22PB0F2 H9 IO40PB1F3 D15 IO00NB0F0 F8 IO23NB0F2 E11 IO41NB1F4 F16 IO00PB0F0 F7 IO23PB0F2 F11 IO42NB1F4 G21 IO02NB0F0 G7 IO24NB0F2 D7 IO42PB1F4 G20 IO02PB0F0 G6 IO24PB0F2 E7 IO43NB1F4 A16 IO04NB0F0 E9 IO25PB0F2 B12 IO43PB1F4 A15 IO04PB0F0 D8 IO26NB0F2 H11 IO44NB1F4 A20 IO06NB0F0 G9 IO26PB0F2 G11 IO44PB1F4 A19 IO06PB0F0 G8 IO27NB0F2 C11* IO45NB1F4 B17 IO07PB0F0 B6 IO27PB0F2 B8 IO45PB1F4 B16 IO08NB0F0 F10 IO28NB0F2 J13 IO46NB1F4 G17 IO08PB0F0 F9 IO28PB0F2 K13 IO46PB1F4 H17 IO09PB0F0 C7 IO29NB0F2 J8 IO47NB1F4 A17 IO10NB0F0 H8 IO29PB0F2 J7 IO48NB1F4 C19 IO10PB0F0 H7 IO30NB0F2/HCLKAN G13 IO48PB1F4 C18 IO11NB0F0 D10 IO30PB0F2/HCLKAP G12 IO49NB1F4 B20 IO11PB0F0 D9 IO31NB0F2/HCLKBN C13 IO49PB1F4 B19 IO12NB0F1 B5 IO31PB0F2/HCLKBP C12 IO50NB1F4 H20 IO12PB0F1 B4 IO50PB1F4 H19 IO13NB0F1 A7 IO32NB1F3/HCLKCN G15 IO51NB1F4 A22 IO13PB0F1 A6 IO32PB1F3/HCLKCP G14 IO51PB1F4 A21 IO14NB0F1 C9 IO33NB1F3/HCLKDN B14 IO52NB1F4 C21 IO14PB0F1 C8 IO33PB1F3/HCLKDP B13 IO52PB1F4 C20 IO15PB0F1 B7 IO34NB1F3 G16 IO53NB1F4 B22 IO16NB0F1 A5 IO34PB1F3 H16 IO53PB1F4 B21 IO16PB0F1 A4 IO35NB1F3 C17 IO54NB1F5 J18 IO17NB0F1 A9 IO35PB1F3 B18 IO54PB1F5 J19 IO17PB0F1 B9 IO36NB1F3 H18 IO55NB1F5 D18 IO18NB0F1 D12 IO36PB1F3 H15 IO55PB1F5 D17 IO18PB0F1 D11 IO37NB1F3 H13 IO56NB1F5 F20 IO20NB0F1 B11 IO38NB1F3 E15 IO56PB1F5 F19 IO20PB0F1 B10 IO38PB1F3 F15 IO58NB1F5 E17 IO21NB0F1 A11 IO39NB1F3 D14 IO58PB1F5 F17 IO21PB0F1 A10 IO39PB1F3 C14 IO60NB1F5 D20 IO22NB0F2 H10 IO40NB1F3 D16 IO60PB1F5 D19 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Bank 1 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-103 Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA 624-Pin CCGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO62NB1F5 E18 IO82NB2F7 P18 IO101PB3F9 P22 IO62PB1F5 F18 IO82PB2F7 P17 IO102NB3F9 U19 IO63NB1F5 G19 IO83NB2F7 N22 IO102PB3F9 T19 IO63PB1F5 G18 IO83PB2F7 M22 IO104NB3F9 V20 IO84NB2F7 M20 IO104PB3F9 U20 Bank 2 IO64NB2F6 M17* IO84PB2F7 M21 IO105NB3F9 R23 IO64PB2F6 G22* IO86NB2F8 E25 IO105PB3F9 P23 IO65NB2F6 J21 IO86PB2F8 D25 IO106NB3F9 R19 IO65PB2F6 J20 IO87NB2F8 L24 IO106PB3F9 R20 IO66NB2F6 L23* IO87PB2F8 K24 IO107NB3F10 AB24 IO66PB2F6 K20* IO88NB2F8 G24 IO108NB3F10 R25 IO67NB2F6 F23 IO88PB2F8 F24 IO108PB3F10 P25 IO67PB2F6 E23 IO89NB2F8 J25 IO109NB3F10 U25 IO68NB2F6 L18 IO90NB2F8 G25 IO109PB3F10 T25 IO68PB2F6 K18 IO90PB2F8 F25 IO110NB3F10 U24 IO70NB2F6 E24 IO91NB2F8 L25 IO110PB3F10 U23 IO70PB2F6 D24 IO91PB2F8 K25 IO112NB3F10 T24 IO71NB2F6 H23 IO92NB2F8 J24 IO112PB3F10 R24 IO71PB2F6 G23 IO92PB2F8 H24 IO113NB3F10 Y25 IO72NB2F6 L19 IO93PB2F8 J23 IO113PB3F10 W25 IO72PB2F6 K19 IO94NB2F8 N24 IO114NB3F10 V23 IO74NB2F7 J22 IO94PB2F8 M24 IO114PB3F10 V24 IO74PB2F7 H22 IO95NB2F8 N25 IO116NB3F10 AA24 IO75NB2F7 N23 IO95PB2F8 M25 IO116PB3F10 Y24 IO75PB2F7 M23 IO117NB3F10 AB25 IO76NB2F7 N17* IO96NB3F9 T18 IO117PB3F10 AA25 IO76PB2F7 N16* IO96PB3F9 R18 IO118NB3F11 T20 IO77NB2F7 L22 IO97NB3F9 N20 IO118PB3F11 R21 IO77PB2F7 K22 IO97PB3F9 P24 IO120NB3F11 W22 IO78NB2F7 M19 IO98NB3F9 P20 IO120PB3F11 W23 IO78PB2F7 M18 IO98PB3F9 P19 IO122NB3F11 V22 IO79NB2F7 N19 IO99NB3F9 P21 IO122PB3F11 U22 IO79PB2F7 N18 IO100NB3F9 T22 IO124NB3F11 Y23 IO80NB2F7 L21 IO100PB3F9 W24 IO124PB3F11 AA23 IO80PB2F7 L20 IO101NB3F9 R22 IO126NB3F11 V21 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -1 0 4 Bank 3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA 624-Pin CCGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO126PB3F11 U21 IO149PB4F13 AC14 IO168PB5F15 AA6 IO128NB3F11 Y22 IO150NB4F13 AE19 IO169NB5F15 V8 IO128PB3F11 Y21 IO150PB4F13 AE20 IO169PB5F15 V7 IO151NB4F13 V17 IO171NB5F16 W8 Bank 4 IO129NB4F12 W20 IO151PB4F13 W17 IO171PB5F16 W9 IO129PB4F12 Y20 IO152NB4F14 AB16 IO172NB5F16 AB8 IO131NB4F12 V19 IO152PB4F14 W16 IO172PB5F16 AC8 IO131PB4F12 W19 IO153NB4F14 Y15 IO173NB5F16 AA11 IO133NB4F12 Y18 IO153PB4F14 Y16 IO173PB5F16 Y11 IO133PB4F12 Y19 IO155NB4F14 V15 IO174NB5F16 AB10 IO135NB4F12 W18 IO155PB4F14 V16 IO174PB5F16 AB11 IO135PB4F12 V18 IO156NB4F14 AB14 IO175NB5F16 AC9 IO137NB4F12 Y17 IO156PB4F14 AB15 IO175PB5F16 AE9 IO137PB4F12 AA17 IO157NB4F14 AE14 IO177NB5F16 AA8 IO138NB4F12 AB19 IO157PB4F14 AC18 IO177PB5F16 Y8 IO138PB4F12 AB18 IO158NB4F14 AC15 IO178NB5F16 Y6 IO139NB4F13 AA19 IO158PB4F14 AC19 IO178PB5F16 W6 IO139PB4F13 U18 IO159NB4F14/CLKEN W14 IO179NB5F16 Y10 IO140NB4F13 AC20 IO159PB4F14/CLKEP W15 IO179PB5F16 W10 IO140PB4F13 AC21 IO160NB4F14/CLKFN AC13 IO180NB5F16 Y7 IO141NB4F13 AD17 IO160PB4F14/CLKFP AD13 IO180PB5F16 W7 IO141PB4F13 AD18 IO181NB5F17 AD9 IO142NB4F13 AD21 IO161NB5F15/CLKGN W13 IO181PB5F17 AD10 IO142PB4F13 AD22 IO161PB5F15/CLKGP Y13 IO182NB5F17 AE10 IO143NB4F13 AB17 IO162NB5F15/CLKHN AC12 IO182PB5F17 AE11 IO143PB4F13 AC17 IO162PB5F15/CLKHP AD12 IO183NB5F17 AD7 IO144PB4F13 AE22 IO163NB5F15 V9 IO183PB5F17 AD8 IO145NB4F13 AE15 IO163PB5F15 V10 IO184NB5F17 AB9 IO145PB4F13 AE16 IO164NB5F15 V11 IO185NB5F17 AE6 IO146NB4F13 AD19 IO164PB5F15 T13 IO185PB5F17 AE7 IO146PB4F13 AD20 IO165NB5F15 U13 IO186NB5F17 AE4 IO147NB4F13 AD15 IO165PB5F15 V13 IO186PB5F17 AE5 IO147PB4F13 AD16 IO167NB5F15 W11 IO187NB5F17 AA9 IO148PB4F13 AE21 IO167PB5F15 W12 IO187PB5F17 Y9 IO149NB4F13 AD14 IO168NB5F15 AB6 IO188NB5F17 U8 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Bank 5 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-105 Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA 624-Pin CCGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO189NB5F17 AD5 IO209NB6F19 AA2 IO231NB7F21 E2 IO189PB5F17 AD6 IO209PB6F19 AB2 IO231PB7F21 F2 IO191NB5F17 AC5 IO210NB6F19 P5 IO232NB7F21 F1 IO191PB5F17 AC6 IO211NB6F19 M1 IO232PB7F21 G1 IO192NB5F17 AB7 IO211PB6F19 N1 IO233NB7F21 L3 IO192PB5F17 AC7 IO212NB6F19 P1 IO233PB7F21 M3 IO212PB6F19 R1 IO234NB7F21 D1 Bank 6 IO193NB6F18 U6 IO213NB6F19 R8 IO234PB7F21 E1 IO193PB6F18 U5 IO213PB6F19 T8 IO235NB7F21 K4 IO194NB6F18 Y3 IO215NB6F20 U4 IO235PB7F21 L4 IO194PB6F18 AA3 IO215PB6F20 V4 IO236NB7F22 M6 IO195NB6F18 V6* IO216NB6F20 P8 IO237NB7F22 N8 IO195PB6F18 W4* IO216PB6F20 R3 IO237PB7F22 N7 IO197NB6F18 R5 IO217NB6F20 P7 IO238NB7F22 M5 IO197PB6F18 U3 IO217PB6F20 R7 IO239NB7F22 L6 IO198NB6F18 P6 IO219NB6F20 R4 IO239PB7F22 L5 IO199NB6F18 Y5 IO219PB6F20 T4 IO240NB7F22 M4 IO199PB6F18 W5 IO220NB6F20 P2 IO241NB7F22 L7 IO200NB6F18 V3 IO220PB6F20 R2 IO241PB7F22 M7 IO200PB6F18 W3 IO221NB6F20 N4 IO242NB7F22 J3 IO201NB6F18 T7 IO221PB6F20 P4 IO243NB7F22 M9 IO201PB6F18 U7 IO223NB6F20 M2 IO243PB7F22 M8 IO202NB6F18 V2 IO223PB6F20 N2 IO244NB7F22 P9* IO203NB6F19 W2 IO224NB6F20 N3 IO244PB7F22 N6* IO203PB6F19 Y2 IO224PB6F20 P3 IO245NB7F22 K8 IO204NB6F19 AA1 IO245PB7F22 L8 IO204PB6F19 AB1 IO225NB7F21 J2 IO246NB7F22 F3 IO205NB6F19 R6 IO225PB7F21 J1 IO246PB7F22 E3 IO205PB6F19 T6 IO226PB7F21 G2 IO247NB7F23 K7 IO206NB6F19 W1 IO227NB7F21 H3 IO247PB7F23 K6 IO206PB6F19 Y1 IO227PB7F21 H2 IO248NB7F23 D2 IO207NB6F19 T2 IO229NB7F21 K2 IO249NB7F23 G4 IO207PB6F19 U2 IO229PB7F21 L2 IO249PB7F23 G3 IO208NB6F19 T1 IO230NB7F21 K1 IO251NB7F23 N10 IO208PB6F19 U1 IO230PB7F21 L1 IO251PB7F23 N9 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -1 0 6 Bank 7 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA 624-Pin CCGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO253NB7F23 H4 GND B25 GND P14 IO253PB7F23 J4 GND C10 GND P15 IO255NB7F23 J6 GND C16 GND R11 IO255PB7F23 J5 GND C23 GND R12 IO257NB7F23 H5 GND C3 GND R13 IO257PB7F23 H6 GND D22 GND R14 GND D4 GND R15 Dedicated I/O GND A18 GND E10 GND T21 GND A2 GND E16 GND T23 GND A24 GND E21 GND T3 GND A25 GND E5 GND T5 GND A8 GND H1 GND V1 GND AA10 GND H21 GND V25 GND AA16 GND H25 GND V5 GND AA18 GND K21 GND/LP E8 GND AA21 GND K23 NC A14 GND AA5 GND K3 NC AA20 GND AB22 GND K5 NC AB13 GND AB4 GND L11 NC AD4 GND AC10 GND L12 NC AE12 GND AC16 GND L13 NC F21 GND AC23 GND L14 NC G10 GND AC3 GND L15 PRA F13 GND AD1 GND M11 PRB A13 GND AD2 GND M12 PRC AB12 GND AD24 GND M13 PRD AE13 GND AD25 GND M14 TCK F5 GND AE1 GND M15 TDI C5 GND AE18 GND N11 TDO F6 GND AE2 GND N12 TMS D6 GND AE24 GND N13 TRST E6 GND AE25 GND N14 VCCA AB20 GND AE8 GND N15 VCCA F22 GND B1 GND P11 VCCA F4 GND B2 GND P12 VCCA J17 GND B24 GND P13 VCCA J9 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-107 Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA 624-Pin CCGA AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number VCCA K10 VCCIB0 D5 VCCIB5 AE3 VCCA K11 VCCIB0 J10 VCCIB5 T12 VCCA K15 VCCIB0 J11 VCCIB5 U10 VCCA K16 VCCIB0 K12 VCCIB5 U11 VCCA L10 VCCIB1 A23 VCCIB6 AA4 VCCA L16 VCCIB1 B23 VCCIB6 AB3 VCCA R10 VCCIB1 C22 VCCIB6 AC1 VCCA R16 VCCIB1 D21 VCCIB6 AC2 VCCA T10 VCCIB1 J15 VCCIB6 P10 VCCA T11 VCCIB1 J16 VCCIB6 R9 VCCA T15 VCCIB1 K14 VCCIB6 T9 VCCA T16 VCCIB2 C24 VCCIB7 C1 VCCA U17 VCCIB2 C25 VCCIB7 C2 VCCA U9 VCCIB2 D23 VCCIB7 D3 VCCA Y4 VCCIB2 E22 VCCIB7 E4 VCCDA A12 VCCIB2 K17 VCCIB7 K9 VCCDA AA13 VCCIB2 L17 VCCIB7 L9 VCCDA AA15 VCCIB2 M16 VCCIB7 M10 VCCDA AA7 VCCIB3 AA22 VCCPLA J12 VCCDA AC11 VCCIB3 AB23 VCCPLB E14 VCCDA AD11 VCCIB3 AC24 VCCPLC H14 VCCDA AE17 VCCIB3 AC25 VCCPLD Y14 VCCDA B15 VCCIB3 P16 VCCPLE U14 VCCDA C15 VCCIB3 R17 VCCPLF Y12 VCCDA C6 VCCIB3 T17 VCCPLG U12 VCCDA D13 VCCIB4 AB21 VCCPLH F12 VCCDA E13 VCCIB4 AC22 VCOMPLA H12 VCCDA E19 VCCIB4 AD23 VCOMPLB F14 VCCDA G5 VCCIB4 AE23 VCOMPLC J14 VCCDA N21 VCCIB4 T14 VCOMPLD AA14 VCCDA N5 VCCIB4 U15 VCOMPLE V14 VCCDA W21 VCCIB4 U16 VCOMPLF AA12 VCCIB0 A3 VCCIB5 AB5 VCOMPLG V12 VCCIB0 B3 VCCIB5 AC4 VCOMPLH J12 VCCIB0 C4 VCCIB5 AD3 VPUMP E20 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -1 0 8 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 624-Pin CCGA 624-Pin CCGA AX2000 Function Pin Number Bank 0 AX2000 Function 624-Pin CCGA Pin Number AX2000 Function Pin Number IO30NB0F2 B11 IO57PB1F5 D15 IO00NB0F0 D7* IO30PB0F2 B10 IO58NB1F5 A22 IO00PB0F0 E7* IO31NB0F2 E11 IO58PB1F5 A21 IO01NB0F0 G7 IO31PB0F2 F11 IO59NB1F5 F16 IO01PB0F0 G6 IO33NB0F2 D12 IO61NB1F5 G17 IO02NB0F0 B5 IO33PB0F2 D11 IO61PB1F5 H17 IO02PB0F0 B4 IO34NB0F3 A11 IO62NB1F5 B17 IO04PB0F0 C7 IO34PB0F3 A10 IO62PB1F5 B16 IO05NB0F0 F8 IO37NB0F3 J13 IO63NB1F5 H18 IO05PB0F0 F7 IO37PB0F3 K13 IO65NB1F6 C17 IO06NB0F0 H8 IO38NB0F3 H11 IO66PB1F6 B18 IO06PB0F0 H7 IO38PB0F3 G11 IO67NB1F6 J18 IO11NB0F0 J8 IO40PB0F3 B12 IO67PB1F6 J19 IO11PB0F0 J7 IO41NB0F3/HCLKAN G13 IO68NB1F6 B20 IO12PB0F1 B6 IO41PB0F3/HCLKAP G12 IO68PB1F6 B19 IO13NB0F1 E9* IO42NB0F3/HCLKBN C13 IO69NB1F6 E17 IO13PB0F1 D8* IO42PB0F3/HCLKBP C12 IO69PB1F6 F17 IO15NB0F1 C9 IO70NB1F6 B22 IO15PB0F1 C8 IO43NB1F4/HCLKCN G15 IO70PB1F6 B21 IO16NB0F1 A5 IO43PB1F4/HCLKCP G14 IO71PB1F6 G18 IO16PB0F1 A4 IO44NB1F4/HCLKDN B14 IO73NB1F6 G19 IO17NB0F1 D10 IO44PB1F4/HCLKDP B13 IO74NB1F6 C19 IO17PB0F1 D9 IO45NB1F4 H13 IO74PB1F6 C18 IO18NB0F1 A7 IO47NB1F4 D14 IO75NB1F6 D18 IO18PB0F1 A6 IO47PB1F4 C14 IO75PB1F6 D17 IO19NB0F1 G9 IO48NB1F4 A16 IO76NB1F7 C21 IO19PB0F1 G8 IO48PB1F4 A15 IO76PB1F7 C20 IO20PB0F1 B7 IO49PB1F4 H15 IO79NB1F7 H20 IO23NB0F2 F10 IO51NB1F4 E15 IO79PB1F7 H19 IO23PB0F2 F9 IO51PB1F4 F15 IO80NB1F7 E18 IO26NB0F2 C11* IO52NB1F4 A17 IO80PB1F7 F18 IO26PB0F2 B8* IO55NB1F5 G16 IO81NB1F7 G21 IO27NB0F2 H10 IO55PB1F5 H16 IO81PB1F7 G20 IO27PB0F2 H9 IO56NB1F5 A20 IO82NB1F7 F20 IO28NB0F2 A9 IO56PB1F5 A19 IO82PB1F7 F19 IO28PB0F2 B9 IO57NB1F5 D16 IO85NB1F7 D20* * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Bank 1 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-109 Axcelerator Family FPGAs 624-Pin CCGA AX2000 Function IO85PB1F7 624-Pin CCGA Pin Number D19* Bank 2 Pin Number AX2000 Function Pin Number IO112NB2F10 L24 IO146NB3F13 T24 IO112PB2F10 K24 IO146PB3F13 R24 IO86NB2F8 F23 IO113NB2F10 N17 IO147NB3F13 T20 IO86PB2F8 E23 IO115NB2F10 M20 IO147PB3F13 R20 IO87NB2F8 H23 IO115PB2F10 M21 IO148NB3F13 U25 IO87PB2F8 G23 IO117NB2F10 N19 IO148PB3F13 T25 IO88NB2F8 E24 IO117PB2F10 N18 IO149NB3F13 T22 IO88PB2F8 D24 IO118NB2F11 J25 IO153NB3F14 U19 IO89NB2F8 M17* IO121NB2F11 N24 IO153PB3F14 T19 IO89PB2F8 G22* IO121PB2F11 M24 IO154NB3F14 Y25 IO91NB2F8 J22 IO122NB2F11 L25 IO154PB3F14 W25 IO91PB2F8 H22 IO122PB2F11 K25 IO157NB3F14 V20 IO92NB2F8 L18 IO123NB2F11 N22 IO157PB3F14 U20 IO92PB2F8 K18 IO123PB2F11 M22 IO158NB3F14 AB25 IO96NB2F9 G24 IO124NB2F11 N23 IO158PB3F14 AA25 IO96PB2F9 F24 IO124PB2F11 M23 IO160PB3F14 W24 IO97NB2F9 J21 IO127NB2F11 P18 IO161NB3F15 U24 IO97PB2F9 J20 IO127PB2F11 P17 IO161PB3F15 U23 IO98PB2F9 J23 IO128NB2F11 N25 IO162NB3F15 AA24 IO99NB2F9 L19 IO128PB2F11 M25 IO162PB3F15 Y24 IO99PB2F9 K19 IO163NB3F15 V22 IO100NB2F9 E25 IO129NB3F12 N20 IO163PB3F15 U22 IO100PB2F9 D25 IO130PB3F12 P24 IO164NB3F15 V23 IO103PB2F9 K20 IO131NB3F12 P21 IO164PB3F15 V24 IO105NB2F9 M19 IO133NB3F12 P20 IO166NB3F15 AB24 IO105PB2F9 M18 IO133PB3F12 P19 IO167NB3F15 V21 IO106NB2F9 J24 IO138NB3F12 R23 IO167PB3F15 U21 IO106PB2F9 H24 IO138PB3F12 P23 IO168NB3F15 Y23 IO107NB2F10 L23* IO139NB3F13 R22 IO168PB3F15 AA23 IO107PB2F10 N16* IO139PB3F13 P22 IO169NB3F15 W22* IO109NB2F10 L22 IO141NB3F13 R19 IO169PB3F15 W23* IO109PB2F10 K22 IO142NB3F13 R25 IO170NB3F15 Y22 IO110NB2F10 G25 IO142PB3F13 P25 IO170PB3F15 Y21 IO110PB2F10 F25 IO143PB3F13 R21 IO111NB2F10 L21 IO145NB3F13 T18 IO171NB4F16 AC20* IO111PB2F10 L20 IO145PB3F13 R18 IO171PB4F16 AC21* * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -1 1 0 AX2000 Function 624-Pin CCGA Bank 3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 Bank 4 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 624-Pin CCGA AX2000 Function 624-Pin CCGA Pin Number AX2000 Function 624-Pin CCGA Pin Number AX2000 Function Pin Number IO172NB4F16 W20 IO206NB4F19 AB14 IO229PB5F21 AD10 IO172PB4F16 Y20 IO206PB4F19 AB15 IO230NB5F21 V11 IO173NB4F16 AD21 IO207NB4F19 AE15 IO233NB5F21 AD7 IO173PB4F16 AD22 IO207PB4F19 AE16 IO233PB5F21 AD8 IO174NB4F16 AA19 IO208PB4F19 W16 IO234NB5F21 V9 IO176NB4F16 Y18 IO209NB4F19 AE14 IO234PB5F21 V10 IO176PB4F16 Y19 IO210NB4F19 V15 IO236NB5F22 AC9 IO177NB4F16 AB19 IO210PB4F19 V16 IO238NB5F22 W8 IO177PB4F16 AB18 IO211NB4F19 AD14 IO238PB5F22 W9 IO182NB4F17 V19 IO211PB4F19 AC14 IO239NB5F22 AE4 IO182PB4F17 W19 IO212NB4F19/CLKEN W14 IO239PB5F22 AE5 IO183PB4F17 AC19 IO212PB4F19/CLKEP W15 IO240NB5F22 AB9 IO184NB4F17 AB17 IO213NB4F19/CLKFN AC13 IO242NB5F22 AA9 IO184PB4F17 AC17 IO213PB4F19/CLKFP AD13 IO242PB5F22 Y9 IO185NB4F17 AD19 IO243NB5F22 AD5 IO185PB4F17 AD20 IO214NB5F20/CLKGN W13 IO243PB5F22 AD6 IO187PB4F17 AC18 IO214PB5F20/CLKGP Y13 IO244NB5F22 U8 IO188NB4F17 Y17 IO215NB5F20/CLKHN AC12 IO246NB5F23 AB8 IO188PB4F17 AA17 IO215PB5F20/CLKHP AD12 IO246PB5F23 AC8 IO189PB4F17 AE22 IO216NB5F20 U13 IO247NB5F23 AB7 IO191NB4F17 W18 IO216PB5F20 V13 IO247PB5F23 AC7 IO191PB4F17 V18 IO217NB5F20 AE10 IO250NB5F23 AA8 IO192PB4F17 U18 IO217PB5F20 AE11 IO250PB5F23 Y8 IO195PB4F18 AE21 IO218NB5F20 W11 IO251NB5F23 V8 IO196NB4F18 AB16 IO218PB5F20 W12 IO251PB5F23 V7 IO197NB4F18 AD17 IO222NB5F20 AA11 IO252NB5F23 Y7 Bank 5 IO197PB4F18 AD18 IO222PB5F20 Y11 IO252PB5F23 W7 IO198NB4F18 V17 IO223PB5F21 AE9 IO253NB5F23 AC5 IO198PB4F18 W17 IO225NB5F21 AE6 IO253PB5F23 AC6 IO199NB4F18 AE19 IO225PB5F21 AE7 IO254NB5F23 Y6 IO199PB4F18 AE20 IO226NB5F21 Y10 IO254PB5F23 W6 IO200NB4F18 AC15 IO226PB5F21 W10 IO256NB5F23 AB6* IO201NB4F18 AD15 IO227PB5F21 T13 IO256PB5F23 AA6* IO201PB4F18 AD16 IO228NB5F21 AB10 IO202NB4F18 Y15 IO228PB5F21 AB11 IO257NB6F24 Y3 IO202PB4F18 Y16 IO229NB5F21 AD9 IO257PB6F24 AA3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 Bank 6 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-111 Axcelerator Family FPGAs 624-Pin CCGA AX2000 Function 624-Pin CCGA Pin Number Pin Number AX2000 Function Pin Number IO258NB6F24 V3 IO288NB6F26 P5 IO321NB7F30 J2 IO258PB6F24 W3 IO290NB6F27 P6 IO321PB7F30 J1 IO259NB6F24 AA2 IO291NB6F27 P1 IO323NB7F30 L7 IO259PB6F24 AB2 IO291PB6F27 R1 IO323PB7F30 M7 IO260NB6F24 V6* IO292NB6F27 P7 IO324NB7F30 M9 IO260PB6F24 W4* IO292PB6F27 R7 IO324PB7F30 M8 IO262NB6F24 U4 IO293NB6F27 M1 IO327NB7F30 F1 IO262PB6F24 V4 IO293PB6F27 N1 IO327PB7F30 G1 IO263NB6F24 Y5 IO294NB6F27 P8 IO328NB7F30 K7 IO263PB6F24 W5 IO296NB6F27 N3 IO328PB7F30 K6 IO268NB6F25 U6 IO296PB6F27 P3 IO329NB7F30 D1 IO268PB6F25 U5 IO298NB6F27 N4 IO329PB7F30 E1 IO269PB6F25 U3 IO298PB6F27 P4 IO331PB7F30 G2 IO272NB6F25 T2 IO299NB6F27 M2 IO332NB7F31 H3 IO272PB6F25 U2 IO299PB6F27 N2 IO332PB7F31 H2 IO273NB6F25 W2 IO333NB7F31 E2 IO273PB6F25 Y2 IO300NB7F28 P9* IO333PB7F31 F2 IO274NB6F25 R6 IO300PB7F28 N6* IO334NB7F31 H4 IO274PB6F25 T6 IO302NB7F28 M6 IO334PB7F31 J4 IO275NB6F25 T7 IO304NB7F28 N8 IO335NB7F31 H5 IO275PB6F25 U7 IO304PB7F28 N7 IO335PB7F31 H6 IO277NB6F25 V2 IO308NB7F28 M4 IO337NB7F31 D2 IO278NB6F26 R4 IO309NB7F28 L3 IO338NB7F31 J6 IO278PB6F26 T4 IO309PB7F28 M3 IO338PB7F31 J5 IO279PB6F26 R3 IO310NB7F29 N10 IO339NB7F31 F3 IO280NB6F26 R5 IO310PB7F29 N9 IO339PB7F31 E3 IO281NB6F26 AA1 IO311NB7F29 K1 IO340NB7F31 G4* IO281PB6F26 AB1 IO311PB7F29 L1 IO340PB7F31 G3* IO284NB6F26 R8 IO313NB7F29 M5 IO341NB7F31 K8 IO284PB6F26 T8 IO316NB7F29 L6 IO341PB7F31 L8 IO285NB6F26 W1 IO316PB7F29 L5 IO285PB6F26 Y1 IO317NB7F29 K2 GND K5 IO286NB6F26 P2 IO317PB7F29 L2 GND A18 IO286PB6F26 R2 IO318NB7F29 K4 GND A2 IO287NB6F26 T1 IO318PB7F29 L4 GND A24 IO287PB6F26 U1 IO320NB7F29 J3 GND A25 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -1 1 2 AX2000 Function 624-Pin CCGA Bank 7 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 Dedicated I/O * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs 624-Pin CCGA AX2000 Function 624-Pin CCGA Pin Number AX2000 Function 624-Pin CCGA Pin Number AX2000 Function Pin Number GND A8 GND E8 GND V1 GND AA10 GND H1 GND V25 GND AA16 GND H21 GND V5 GND AA18 GND H25 PRA F13 GND AA21 GND K21 PRB A13 GND AA5 GND K23 PRC AB12 GND AB22 GND K3 PRD AE13 GND AB4 GND L11 TCK F5 GND AC10 GND L12 TDI C5 GND AC16 GND L13 TDO F6 GND AC23 GND L14 TMS D6 GND AC3 GND L15 TRST E6 GND AD1 GND M11 VCCA AB20 GND AD2 GND M12 VCCA F22 GND AD24 GND M13 VCCA F4 GND AD25 GND M14 VCCA J17 GND AE1 GND M15 VCCA J9 GND AE18 GND N11 VCCA K10 GND AE2 GND N12 VCCA K11 GND AE24 GND N13 VCCA K15 GND AE25 GND N14 VCCA K16 GND AE8 GND N15 VCCA L10 GND B1 GND P11 VCCA L16 GND B2 GND P12 VCCA R10 GND B24 GND P13 VCCA R16 GND B25 GND P14 VCCA T10 GND C10 GND P15 VCCA T11 GND C16 GND R11 VCCA T15 GND C23 GND R12 VCCA T16 GND C3 GND R13 VCCA U17 GND D22 GND R14 VCCA U9 GND D4 GND R15 VCCA Y4 GND E10 GND T21 VCCDA A12 GND E16 GND T23 VCCDA A14 GND E21 GND T3 VCCDA AA13 GND E5 GND T5 VCCDA AA15 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3-113 Axcelerator Family FPGAs 624-Pin CCGA AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number VCCDA AA20 VCCIB2 D23 VCCIB7 E4 VCCDA AA7 VCCIB2 E22 VCCIB7 K9 VCCDA AB13 VCCIB2 K17 VCCIB7 L9 VCCDA AC11 VCCIB2 L17 VCCIB7 M10 VCCDA AD11 VCCIB2 M16 VCCPLA E12 VCCDA AD4 VCCIB3 AA22 VCCPLB J12 VCCDA AE12 VCCIB3 AB23 VCCPLC E14 VCCDA AE17 VCCIB3 AC24 VCCPLD H14 VCCDA B15 VCCIB3 AC25 VCCPLE Y14 VCCDA C15 VCCIB3 P16 VCCPLF U14 VCCDA C6 VCCIB3 R17 VCCPLG Y12 VCCDA D13 VCCIB3 T17 VCCPLH U12 VCCDA E13 VCCIB4 AB21 VCOMPLA F12 VCCDA E19 VCCIB4 AC22 VCOMPLB H12 VCCDA F21 VCCIB4 AD23 VCOMPLC F14 VCCDA G10 VCCIB4 AE23 VCOMPLD J14 VCCDA G5 VCCIB4 T14 VCOMPLE AA14 VCCDA N21 VCCIB4 U15 VCOMPLF V14 VCCDA N5 VCCIB4 U16 VCOMPLG AA12 VCCDA W21 VCCIB5 AB5 VCOMPLH V12 VCCIB0 A3 VCCIB5 AC4 VPUMP E20 VCCIB0 B3 VCCIB5 AD3 VCCIB0 C4 VCCIB5 AE3 VCCIB0 D5 VCCIB5 T12 VCCIB0 J10 VCCIB5 U10 VCCIB0 J11 VCCIB5 U11 VCCIB0 AA4 K12 VCCIB6 VCCIB1 A23 VCCIB6 AB3 VCCIB1 B23 VCCIB6 AC1 VCCIB1 C22 VCCIB6 AC2 VCCIB1 D21 VCCIB6 P10 VCCIB1 J15 VCCIB6 R9 VCCIB1 J16 VCCIB6 T9 VCCIB1 K14 VCCIB7 C1 VCCIB2 C24 VCCIB7 C2 VCCIB2 C25 VCCIB7 D3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3 -1 1 4 624-Pin CCGA 624-Pin CCGA * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. v2.3 * Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version v2.2 v2.1 Changes in current version (v2.3) Page The "Packaging Data" section is new. iii Table 2-2 was updated. 2-1 "VCCDA Supply Voltage" was updated. 2-9 "PRA/B/C/D Probe A/B/C/D" was updated. 2-9 The "User I/Os" was updated. 2-10 Figure 1-3 was updated. 1-3 Table 2-2 was updated. 2-1 The "Power-Up/Down Sequence" section was updated. 2-1 Table 2-4 was updated. 2-2 Table 2-5 was updated. 2-3 The "Timing Characteristics" section was added. 2-7 Table 2-7 was updated. 2-7 Figure 2-1 was updated. 2-8 The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired Clock - Using LVTTL 24mA High Slew Clock I/O" section were updated. 2-8 The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock - Using LVTTL 24mA High Slew Clock I/O" section were updated. 2-8 The "Global Pins" section was updated. 2-9 The "User I/Os" section was updated. 2-10 Table 2-17 was updated. 2-17 Figure 2-8 was updated. 2-18 Figure 2-13 and Figure 2-14 were updated. The following timing parameters were renamed in I/O timing characteristic tables from Table 2-21 to Table 2-59: 2-21 2-22 to 2-41 tIOCLKQ > tICLKQ tIOCLKY > tOCLKQ Timing numbers were updated from Table 2-21 to Table 2-77. 2-22 to 2-58 The "R-Cell" section was updated. 2-47 Figure 2-59 was updated. 2-74 Figure 2-60 was updated. 2-75 Figure 2-67 was updated. 2-85 Figure 2-68 was updated. 2-86 Table 2-88 to Table 2-92 were updated. 2-75 to 2-79 Table 2-97 to Table 2-101 were updated. 2-86 to 2-88 The "TRST" section was updated. 2-90 The "Global Set Fuse" section was added. 2-91 v2.3 4-1 Axcelerator Family FPGAs Previous version Changes in current version (v2.3) Page A footnote was added to "896-Pin FBGA" for the AX2000 regarding pins AB1, AE2, G1, and K2. v2.0 Advanced v1.6 Pinouts for the AX250, AX500 and AX1000 were added for "352-Pin CQFP". 3-88 Pinout for the AX1000 was added for "624-Pin CCGA". 3-102 Table 2-78 was updated. 2-58 The "Low Power Mode" section was updated. 2-90 Table 1 has been updated. i "Ordering Information" section has been updated. ii The "Device Resources" section has been updated. ii The "Temperature Grade Offerings" section is new. iii The "Speed Grade and Temperature Grade Matrix" section has been updated. iii Table 2-9 has been updated. 2-11 Table 2-10 has been updated. 2-11 Table 2-1 has been updated. 2-1 Table 2-2 has been updated. 2-1 Table 2-3 has been updated. 2-2 Table 2-4 has been updated. 2-2 Table 2-5 has been updated. 2-3 The "Power Estimation Example" section has been updated. 2-5 The "Thermal Characteristics" section has been updated. 2-6 The "Package Thermal Characteristics" section has been updated. 2-6 The "Timing Characteristics" section has been updated. 2-7 The "Pin Descriptions" section has been updated. Timing numbers have been updated from the "3.3V LVTTL" section to the "Timing Characteristics" section. Many AC Loads were updated as well. Timing characteristics for the "Hardwired Clocks" section were updated. Timing characteristics for the "Routed Clocks" section were updated. 2-9 2-22 to 2-48 2-55 2-57 Table 2-88 to Table 2-91 were updated. 2-75 to 2-78 Table 2-97 to Table 2-98were updated. 2-86 to 2-87 The "Low Power Mode" section was updated. 4 -2 3-49 2-90 The "Interface" section was updated. 2-90 The "Data Registers (DRs)" section was updated. 2-91 The "Security" section was updated. 2-91 The "Silicon Explorer II Probe Interface" section was updated. 2-92 The "Programming" section was updated. 2-92 In the "208-Pin PQFP" (AX500) section, pins 2, 52, and 156 changed from VCCDA to VCCA. For pins 170 and 171, the I/O names refer to pair 23 instead of 24. 3-78 The following changes were made in the "676-Pin FBGA"(AX500) section: AE2, AE25 Change from NC to GND. AF2, AF25 Changed from GND to NC AB4, AF24, C1, C26 Changed from VCCDA to VCCA AD15 Change from VCCDA to VCOMPLE AD17 Changed from VCOMPLE to VCCDA 3-36 In the "896-Pin FBGA" (AX2000) section, the AK28 changed from VCCIB5 to VCCIB4. 3-49 The "352-Pin CQFP" section is new. 3-88 The "624-Pin CCGA" section is new. 3-102 v2.3 Axcelerator Family FPGAs Previous version Advanced v1.5 Changes in current version (v2.3) Page All I/O FIFO capability was removed. n/a Table 1 was updated. i Figure 1-9 and was updated. Advanced v1.4 Advanced v1.3 1-7 Figure 2-5 was updated. 2-14 The "Using an I/O Register" section was updated. 2-14 The AX250 and AX1000 descriptions were added to the "484-Pin FBGA"section. 3-22 Table 2-3 was updated. 2-2 Figure 2-1 was updated. 2-8 Figure 2-48 was updated. 2-63 Figure 2-52 was updated. 2-68 In the "208-Pin PQFP" table, pin 196 was missing, but it has been added in this version with a function of GND. 3-78 The following pins in the "484-Pin FBGA" table for AX500 were changed: 3-22 Pin G7 is GND/LP Pins AB8, C10, C11, C14, AB16 are NC. The "676-Pin FBGA" table was updated. Advanced v1.2 3-36 The "Device Resources" section was updated for the CS180. The "Programmable Interconnect Element" and Figure 1-2 was new. Advanced v1.1 ii 1-1 and 1-2 The "180-Pin CSP" table is new. 3-1 The "208-Pin PQFP" tables for the AX500 were updated. The following pins were not defined in the previous version: GND 21 IO106PB5F10/CLKHP 71 GND 136 3-78 Table 1 was updated. i "Ordering Information", "Device Resources" and the Product Plan table were updated. ii Figure 1-3 was updated. 1-3 The "Design Environment" section was updated. 1-6 Figure 1-8 was new. 1-6 Table 2-3 was updated. 2-2 "Package Thermal Characteristics" was updated. 2-6 Figure 2-2 was updated. 2-9 Table 2-8 was updated. 2-11 Figure 2-11 was updated. 2-20 The timing characteristics tables from pages 2-22 to 2-49 were updated. The "Global Resources" section was updated. The timing characteristics tables from pages 2-86 to 2-87 were updated. 2-22 to 2-49 2-55 2-86 to 2-87 The "208-Pin PQFP" tables are new. 3-78 The "256-Pin FBGA" tables are new. 3-12 The "324-Pin FBGA" tables are new. 3-18 v2.3 4-3 Axcelerator Family FPGAs Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. Unmarked (production) This datasheet version contains information that is considered to be final. 4 -4 v2.3 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation Actel Europe Ltd. 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