JFET Input Operational
Amplifiers
These low–cost JFET input operational amplifiers combine two state–of–
the–art linear technologies on a single monolithic integrated circuit. Each
internally compensated operational amplifier has well matched high voltage
JFET input devices for low input offset voltage. The BIFET technology
provides wide bandwidths and fast slew rates with low input bias currents,
input offset currents, and supply currents.
These devices are available in single, dual and quad operational
amplifiers which are pin–compatible with the industry standard MC1741,
MC1458, and the MC3403/LM324 bipolar products.
•Input Offset Voltage Options of 6.0 mV and 15 mV Max
•Low Input Bias Current: 30 pA
•Low Input Offset Current: 5.0 pA
•Wide Gain Bandwidth: 4.0 MHz
•High Slew Rate: 13 V/µs
•Low Supply Current: 1.4 mA per Amplifier
•High Input Impedance: 1012 Ω
ORDERING INFORMATION
Op Amp
Function Device Operating
Temperature Range Package
Single
TL081CD
T 0°to +70°C
SO–8
Single TL081ACP TA = 0° to +70°CPlastic DIP
Dual
TL082CD
T 0°to +70°C
SO–8
Dual TL082ACP TA = 0° to +70°CPlastic DIP
Quad TL084CN, ACN TA = 0° to +70°CPlastic DIP
ON Semiconductor
Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 2 1Publication Order Number:
TL081C/D
TL081C,AC
TL082C,AC
TL084C,AC
SEMICONDUCTOR
TECHNICAL DATA
JFET INPUT
OPERATIONAL AMPLIFIERS
TL081 (Top View)
TL082 (Top View)
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
11
88
PIN CONNECTIONS
+
Offset Null
Noninvt Input
VEE
Inv + Input
VEE
Inputs A
Output A
NC
VCC
Output
Offset Null
Inputs B
Output B
VCC
–
–
+
+
18
7
6
5
2
3
4
18
7
6
5
2
3
4
TL084 (Top View)
N SUFFIX
PLASTIC PACKAGE
CASE 646
PIN CONNECTIONS
4
23
1
14 1
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
––
––
++
++
114
13
12
11
10
9
8
2
3
4
5
6
7
Representative Circuit Schematic (Each Amplifier)
-
+
Inputs
Q3 Q4 Q5 Q2
Q1
VCC
Q6
J1 J2
Q17
Q20
Q23
24
J3
2.0 k
Q14
Q15 10 pF Q19
Q21 Q22 Q24
Q9 Q8 Q7 Q25
Q12
Q10
Q13
Q11
Q16
Q18
1.5k
VEE
Bias Circuitry
Common to All
Amplifiers
Offset
Null
(TL081
only)
Output
1.5k
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
2
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC 18 V
VEE –18
Differential Input Voltage VID ±30 V
Input Voltage Range (Note 1) VIDR ±15 V
Output Short Circuit Duration (Note 2) tSC Continuous
Power Dissipation
Plastic Package (N, P) PD680 mW
Derate above TA = +47°C 1/θJA 10 mW/°C
Operating Ambient Temperature Range TA0 to +70 °C
Storage Temperature Range Tstg –65 to +150 °C
NOTES: 1.The magnitude of the input voltage must not exceed the magnitude of the supply voltage or
15 V, whichever is less.
2.The output may be shorted to ground or either supply. Temperature and/or supply voltages
must be limited to ensure that power dissipation ratings are not exceeded.
3.ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = Tlow to Thigh [Note 1].)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k, VCM = 0) VIO mV
TL081C, TL082C – – 20
TL084C – – 20
TL08_AC – – 7.5
Input Offset Current (VCM = 0) (Note 2) IIO nA
TL08_C – – 5.0
TL08_AC – – 3.0
Input Bias Current (VCM = 0) (Note 2) IIB nA
TL08_C – – 10
TL08_AC – – 7.0
Large–Signal Voltage Gain (VO= ±10 V,RL ≥ 2.0 k) AVOL V/mV
TL08_C 15 – –
TL08_AC 25 – –
Output Voltage Swing (Peak–to–Peak) VOV
(RL ≥ 10 k) 24 – –
(RL ≥ 2.0 k) 20 – –
NOTES: 1. Tlow =0°C for TL081AC,C Thigh =70°C for TL081AC
0°C for TL082AC,C +70°C for TL082AC,C
0°C for TL084AC,C +70°C for TL084AC,C
2.Input Bias currents of JFET input op amps approximately double for every 10°C rise in Junction Temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.
Figure 1. Unity Gain Voltage Follower Figure 2. Inverting Gain of 10 Amplifier
-
+
Vin
RL = 2.0 k
VO
CL = 100 pF
-
+
Vin
RL
VO
CL = 100 pF
10 k
1.0 k
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤10 k, VCM = 0) VIO mV
TL081C, TL082C – 5.0 15
TL084C – 5.0 15
TL08_AC – 3.0 6.0
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 10 – µV/°C
RS = 50 Ω, TA = Tlow to Thigh (Note 1)
Input Offset Current (VCM = 0) (Note 2) IIO pA
TL08_C – 5.0 200
TL08_AC – 5.0 100
Input Bias Current (VCM = 0) (Note 2) IIB pA
TL08_C – 30 400
TL08_AC – 30 200
Input Resistance ri– 1012 –Ω
Common Mode Input Voltage Range VICR V
TL08_C ±10 15, –12 –
TL08_AC ±11 15, –12 –
Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL V/mV
TL08_C 25 150 –
TL08_AC 50 150 –
Output Voltage Swing (Peak–to–Peak) VO24 28 – V
(RL = 10 k)
Common Mode Rejection Ratio (RS ≤ 10 k) CMRR dB
TL08_C 70 100 –
TL08_AC 80 100 –
Supply Voltage Rejection Ratio (RS ≤ 10 k) PSRR dB
TL08_C 70 100 –
TL08_AC 80 100 –
Supply Current (Each Amplifier) ID– 1.4 2.8 mA
Unity Gain Bandwidth BW – 4.0 – MHz
Slew Rate (See Figure 1) SR – 13 – V/µs
Vin = 10 V, RL = 2.0 k, CL = 100 pF
Rise Time (See Figure 1) tr– 0.1 – µs
Overshoot (Vin = 20 mV, RL = 2.0 k, CL = 100 pF) OS – 10 – %
Equivalent Input Noise Voltage en– 25 – nV/ Hz√
RS = 100 Ω, f = 1000 Hz
Channel Separation CS – 120 – dB
AV = 100
NOTES: 1.Tlow =0°C for TL081AC,C Thigh =70°C for TL081AC
0°C for TL082AC,C +70°C for TL082AC,C
0°C for TL084AC,C +70°C for TL084AC,C
2.Input Bias currents of JFET input op amps approximately double for every 10°C rise in Junction Temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
4
VO, OUTPUT VOLTAGE SWING (Vpp)
VO, OUTPUT VOLTAGE SWING (Vpp)
VO, OUTPUT VOLTAGE SWING (Vpp)
VO, OUTPUT VOLTAGE SWING (Vpp)
VCC/VEE = ±15 V
(See Figure 2)
RL = 10 k
RL = 2.0 k
Figure 3. Input Bias Current
versus Temperature Figure 4. Output Voltage Swing
versus Frequency
Figure 5. Output Voltage Swing
versus Load Resistance Figure 6. Output Voltage Swing
versus Supply Voltage
Figure 7. Output Voltage Swing
versus Temperature Figure 8. Supply Current per Amplifier
versus Temperature
TA, AMBIENT TEMPERATURE (°C)
IB
-75 -50 -25 0 25 50 75 100 125
VCC/VEE = ±15 V
100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
RL, LOAD RESISTANCE (kΩ)
0.1 0.2 0.4 0.7 1.0 2.0 104.0 7.0
VCC, |VEE| , SUPPLY VOLTAGE (±V)
0 5.0 10 15 20
RL = 2.0 k
TA = 25°C
TA, AMBIENT TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
ID
VCC/VEE = ±15 V
TA = 25°C
(See Figure 2)
0.6
100
10
1.0
0.1
0.01
30
25
20
15
10
5.0
0
30
20
10
5.0
0
40
30
20
10
0
35
30
25
20
15
10
5.0
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.4
0.2
0
VCC/VEE = ±15 V
±10 V
±5.0 V
RL = 2.0 k
TA = 25°C
(See Figure 2)
VCC/VEE = ±15 V
I , INPUT BIAS CURRENT (nA)
, SUPPLY DRAIN CURRENT (mA)
-100 150
35
40
40
-75 -75
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
5
, OPEN-LOOP GAIN (V/m/v)
VOL
A
, EQUIVALENT INPUT NOISE VOLTAGE (
Figure 9. Large Signal Voltage Gain and
Phase Shift versus Frequency Figure 10. Large Signal Voltage Gain
versus Temperature
Figure 11. Normalized Slew Rate
versus Temperature Figure 12. Equivalent Input Noise Voltage
versus Frequency
Figure 13. Total Harmonic Distortion
versus Frequency
f, FREQUENCY (Hz)
PHASE SHIFT (DEGREES)
106
105
104
103
101
102
1.01.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
, OPEN-LOOP GAIN (V/m/v)
VOL
Gain
Phase Shift
VCC/VEE = ±15 V
RL = 2.0 k
TA = 25°C
VCC/VEE = ±15 V
VO = ±10 V
RL = 2.0 k
TA, AMBIENT TEMPERATURE (°C)
1000
100
10
1.0 -50 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
NORMALIZED SLEW RATE
1.15
1.10
1.05
1.0
0.95
0.90
0.85
-50 -25 0 25 50 75 100 125
f, FREQUENCY (Hz)
60
50
40
30
20
10
0
0.01 0.05 0.1 0.5 1.0 5.0 10 50 100
VCC/VEE = ±15 V
AV = 10
RS = 100 Ω
TA = 25°C
VCC/VEE = ±15 V
AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
f, FREQUENCY (Hz)
THD, TOTAL HARMONIC DISTORTION (%)
1.0
0.5
0.1
0.05
0.01
0.005
0.0010.1 0.5 1.0 5.0 10 50 100
0°
45°
90°
135°
180°
A
enV/ Hz√
n)
107
108
100 M -75-100 150
1.20
0.80
-75
70
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
6
-
+
-
+
Reset
Vin
1/2
TL082 1N914 1.0 µF
*
*Polycarbonate or
Polystyrene Capacitor
VO
Figure 14. Positive Peak Detector
VR
Run
R4
R1 V1 R3
TL081 6
R6
Clear C*
R5
-
+
*Polycarbonate or
Polystyrene Capacitor
Time (t) = R4 Cn (VR/VR-VI), R3 = R4, R5 = 0.1 R6
If R1 = R2: t = 0.693 R4C
Design Example: 100 Second Timer
VR = 10 V C = l.0 mF R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k R1 = R2 = 1.0 k
R2
Figure 15. Voltage Controlled Current Source
Figure 16. Long Interval RC Timer
R2 5.1 k VO
R1 5.1 k
TL081
RL 5.1 k CL 0.5 µF
CC 20 pF
R3 10
2.0 V
0
V/µs = 0.04 V/µs (with CL shown)
•Overshoot 10%
•ts = 10 µs
•When driving large CL, the VO slew rate is determined by CL
•and IO(max):
-2.0 V
IO
Figure 17. Isolating Large Capacitive Loads
If R1 through R4 > > R5 then Iout =
+
Vin
R1
R5
R2
TL081
R4
IO
-
1/2
TL082
-
+
Vin
R5
VO
tIO
CL
0.02
0.5
R3
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
7
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE S
SEATING
PLANE
1
4
58
A0.25 MCBSS
0.25 MBM
h
C
X 45
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.18 0.25
D4.80 5.00
E
1.27 BSCe
3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
0.25 0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
TL081C,AC TL082C,AC TL084C,AC
http://onsemi.com
8
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
ON Semiconductor i s a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right
to make changes without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indem nify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
TL081C/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver , Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
