24C02CT/SN - Microchip - Datasheet.Directory

24C02C

Features:

• Single-supply with operation from 4.5 to 5.5V

• Low-power CMOS technology:

- 1 mA active current, typical

-10 μA standby current, typical at 5.5V

• Organiz ed as a s ingle bl ock of 256 bytes (256 x 8)

• Hardware write protection for upper half of array

• 2-wire serial interface bus, I2C compatible

• 100 kHz and 400 kHz compatibility

• Page write buffer for up to 16 bytes

• Self-timed write cycle (including auto-erase)

• Fast 1 ms write cycle time for Byte or Page mode

• Address lines allow up to eight devices on bus

• 1,000,000 erase/write cycles

• ESD protection > 4,000V

• Data retention > 200 years

• 8-pin PDIP, SOIC, DFN, MSOP or TSSOP

packages

• Available for extended temperature ranges:

Description:

The Microchip Technology Inc. 24C02C is a 2K bit

Serial El ectricall y Erasabl e PROM with a volt age rang e

of 4.5V to 5.5V. The device is organized as a single

block of 256 x 8-bit memory with a 2-wire serial

interface. Low-current design permits operation with

typica l st andb y and ac tive cu rrent s of only 10 μA and 1

mA, respec tiv el y. The device has a p a ge w rite capabil-

ity for up to 16 bytes of data and has fast write cycle

times of only 1 ms for both byte and page writes.

Functional address lines allow the connection of up to

eight 24C02C devices on the same bus for up to 16K

bits of contiguous EEPROM memory. The device is

available in the standard 8-pin PDIP, 8-pin SOIC (150

mil), 8-pin 2x3 DFN, 8-pin MSOP and TSSOP

packages.

Package Types

Block Diagram

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°C to +85°C

- Automotive (E ): -40°C to +125°C

VSS

VCC

SCL

SDA

PDIP, MSOP SOIC, TSSOP

VSS

VCC

SCL

SDA

DFN

VSS

SCL

SDA

VCC

I/O

Control

Logic

Memory

Control

Logic XDEC

HV Generator

EEPROM

Array

Write-Protect

Circuitry

YDEC

Vcc

Vss

Sense Amp.

R/W Control

SDA SCL

A0 A1 A2 WP

2K 5.0V I2C™ Serial EEPROM

I2C is a trademark of Philips Corporation.

24C02C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins...................................................................................................................................... ≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal ope ration of the device at thos e or any other co nditio ns abov e those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply across the

specified operating ranges unless

otherwise noted.

VCC = +4.5V to +5.5V

Commercial (C): TA = 0°C to +70°C

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High-level input voltage VIH 0.7 VCC —V

Low-level input voltage VIL — 0.3 VCC V

Hysteresis of Schmitt Trigger inputs VHYS 0.05 VCC —V(Note)

Low-level output vo lt ag e VOL —0.40VIOL = 3.0 mA, VCC = 4.5V

Input leakage current ILI —±1μAVIN = VSS or VCC, WP = V ss

Output lea kage curre nt ILO —±1μAVOUT = VSS or VCC

Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)

TA = 25°C, f = 1 MHz

Operati ng current ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz

ICC Write — 3 mA VCC = 5.5V

Standby current ICCS —50μAVCC = 5.5V, SDA = SCL = VCC

WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

24C02C

TABLE 1-2: AC CHARACTERISTICS

FIGURE 1-1: BUS TIMING DATA

All parameters apply across the

specified operating ranges unless

otherwise noted.

VCC = +4.5V to +5.5V

Commercial (C): TA = 0°C to +70°C

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Parameter Symbol TA > +85°C -40°C ≤ TA ≤ +85°C Units Remarks

Min. Max. Min. Max.

Clock frequency FCLK —100 — 400kHz

Clock high time THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 — 300 ns (Note 1)

SDA and SCL fall time TF— 300 — 300 ns (Note 1)

Start condition hold time THD:STA 4000 — 600 — ns After this period the first

clock pulse is generated

Start condition setup time TSU:STA 4700 — 600 — ns Only releva nt for repeated

Start condition

Data input hold time THD:DAT 0— 0 —ns(Note 2)

Data input setup time TSU:DAT 250 — 100 — ns

Stop condition setup time TSU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns (Note 2)

Bus free time TBUF 4700 — 1300 — ns Tim e the bu s must be fre e

before a new transmission

can start

Output fall time from VIH

minimum to VIL maxim um TOF — 250 20 + 0.1 CB250 ns (Note 1), CB ≤ 100 pF

Input fil ter sp ik e s upp res si on

(SDA and SCL pins) TSP — 50 — 50 ns (Note 3)

Write cycle time TWR — 1.5 — 1 ms Byte or Page mode

Endurance 1M — 1M — cycles 25°C, VCC = 5.0V, Block

mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not test ed but ensured by characterization. For endur ance esti mates in a s pecific

applic ation, ple ase con sult the Total Endura nce™ Model w hich ca n be obt ained from Microchi p’ s web sit e

at www.microchip.com.

SCL

SDA

TSU:STA

SDA

OUT

THD:STA

TLOW

THIGH TR

TBUF

TAA

THD:DAT TSU:DAT TSU:STO

TSP

24C02C

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 SDA Serial Data

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).

For norma l data trans fer SDA is all owed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.2 SCL Serial Clock

This i nput is u sed t o sy nchron ize the d ata trans fer fro m

and to the device.

2.3 A0, A1, A2

The levels on these inputs are compared with the

corresponding bits in the slave address. The chip is

selected if the compare is true.

Up to eight 24C02C devices may be connected to the

same bus by using different Chip Select bit combina-

tions. T hese i nput s mu st be c onnec ted to e ither VCC or

VSS.

2.4 WP

This is the hardware write-p rotect pin. It must be tie d to

VCC or VSS. If tied to Vcc, the ha rdware write protectio n

is enabled. If the WP pin is tied to Vss the hardware

write protection is disabled.

2.5 Noise Protection

The 24C02C employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 3.8 volts at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

3.0 FUNCTIONAL DESCRIPTIONS

The 24C02C supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receivi ng data as receiver . The bus has t o be controlle d

by a master device which generates the Serial Clock

(SCL), controls the bus access, and generates the S tart

and S t op conditi ons, while the 24C02C works as slave.

Both master and slave can operate as transmitter or

receive r but th e mas ter devic e det ermine s whic h mod e

is activated.

Name Function

Vss Ground

SDA Serial Data

SCL Serial Clock

VCC +4.5V to 5.5V Power Supply

A0, A1, A2 Chip Selects

WP Hardware Write-Protect

24C02C

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Fig ure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All opera-

tions must be ended with a Stop condition.

4.4 Dat a Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of th e clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last sixteen

will be stored when doing a write operation. When an

overwri te does occur it will replace da ta in a firs t-in first-

out fashion.

4.5 Acknowledge

Each receiving device, when addressed, is required to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line du ring the Acknow ledge cl ock pulse in s uch a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by no t g ene rati ng an Acknow led ge bi t o n th e las t

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the maste r to gen erat e the Stop conditi on (Fi gure 4-2).

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24C02C does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

(A) (B) (C) (D) (A)(C)

SCL

SDA

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL 987654321 123

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Data from transmitter Data from transmitter

SDA

Acknowledge

Bit

24C02C

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a four bit control code; for

the 24C02C this is set as ‘1010’ binary for read and

write op erat ion s. Th e ne xt three bits of th e control byte

are t he C hip Sele ct b its (A 2, A1 , A0) . Th e C hip S ele ct

bits allo w th e us e of up to eigh t 24C 02C d evice s on the

same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

corresp ond to the logic lev els on the corresp onding A2,

A1 and A0 pins for the device to respond. These bits

are in effect the three Most Significant bits of the word

address.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’ a read operation is

selected, and when set to a ‘0’ a write operation is

selected. Following the Start condition, the 24C02C

monitors the SDA bus checking the control byte being

transmitted. Upon receiving a ‘1010’ code and appro-

priate Chip Select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24C02C will select a read or

write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across

Multiple Devices

The Chip Select bits A2, A1, A0 can be used to expand

the contiguous address space for up to 16K bits by

adding up to eight 24C02C devices on the same bus.

In this case, software can use A0 of the control byte

as address bit A8, A1 as address bit A9, and A2 as

address bit A10. It is not possible to write or read

across device boundaries.

1 0 1 0 A2 A1 A0SACKR/W

Control Code Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

24C02C

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start signal from the master, the device

code (4 bits), the Chip Select bits (3 bits) and the R/W

bit, which i s a logi c low, is pl aced ont o the bu s by the

master transmitter. The device will acknowledge this

control by te during the ninth clock pulse. The ne xt byte

tran smit ted by the ma ster is the word add res s and wi ll

be written into the Address Pointer of the 24C02C.

After receiving another Acknowledge signal from the

24C02C the master device will transmit the data word

to be written into the addressed memory location. The

24C02C acknowledges again and the master gener-

ates a Stop condition. This initiates the internal write

cycle, and during this time the 24C02C will not gener-

ate Acknowledge signals (Figure 6-1). If an attempt is

made to write to the protected portion of the array when

the hardware write protection has been enabled, the

device will acknowledge the command but no data will

be written. The write cycle time must be observed even

if the write protection is enabled.

6.2 Page Write

The write control byte, word address and the first data

byte are tr ansmitted to the 24 C02C in the same way a s

in a byte write. But instead of generating a Stop

conditi on, th e mas ter tran smit s u p to 15 addi tional dat a

bytes to the 24C02C which are temporarily stored in

the on-chip page buffer and will be written into the

memory after the master has transmitted a Stop

conditi on. After th e recei pt of each word , the four lo wer

order Address Pointer bits are internally incremented

by o ne. T h e hi g her o r der f o ur bi ts of t he w o rd a d dr e ss

remains constant. If the master should transmit more

than 1 6 bytes p rior to gen erating the S top cond ition, the

address counter will roll over and the previously

received data will be overwritten.

As with the byte write operation, once the Stop

condition is received an internal write cycle will begin

(Figure 6-2). If an attempt is made to write to the

protected portion of the array when the hardware write

protection has been enabled, the device will acknowl-

edge the command, but no data will be written. The

write cycle time must be observed even if the write

protection is enabled.

6.3 Write Protection

The WP pin must be tied to VCC or VSS. If tied to VCC,

the upper half of the array (080-0FF) will be write-

protected. If the WP pin is tied to VSS, then write

operations t o all addr ess locations a re allowed.

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’ ) an d end at address es that a re

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritte n to th e nex t page as mi ght be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

S P

Bus Acti vity

Master

SDA Line

Bus Acti vity

Control

Byte Word

Address Data

S P

Bus Activit y

Master

SDA Line

Bus Activity

Control

Byte Word

Address (n) Data n Data n + 15

Data n +1

24C02C

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no AC K is retu rned, then the S t art bit and cont rol byte

must be re-sent. If the cycle is complete, then the

device will return the ACK and the master can then

proceed with the next Read or Write command. See

Figure 7-1 for flow diagram.

FIGURE 7-1: ACKNOWLEDGE

POLLING FLOW

8.0 READ OPERATIONS

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There a re three basic types

of read operation s: curren t address re ad, ra ndom rea d,

and sequential read.

8.1 Current Address Read

The 24C02C contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access was to address n, the next current address read

operat ion woul d acc ess da ta f rom add ress n + 1. Upo n

receipt o f the slave a ddress with the R/W bit s et to one,

the 24C02C issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer , but does generate a S top condition and the

24C02C discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad o peration, fi rst the word address m us t

be set. This is done b y sending the word address to the

24C02C as part of a write operation. After the word

address is sent, the master generat es a Start condi tion

following the acknowledge. This terminates the write

operatio n, but not before the internal Address Pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24C02C will then

issue an acknowledge and transmits the eight bit data

word. The m aster wil l not a cknowledg e the tra nsfer b ut

does generate a Stop condition and the 24C02C

discontinues transmission (Figure 8-2). After this

command, the interna l address counte r will po int to the

address location following the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24C02C transmits

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

directs the 24C02C to transmit the next sequentially

addressed 8-bit word (Figure 8-3).

To provide sequential reads, the 24C02C contains an

internal Address Pointer which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation. The internal Address

Pointer will automatically roll over from address FF to

address 00.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24C02C

FIGURE 8-1: CURRENT READ ADDRESS

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

Bus Acti vity

Master

SDA line

Bus Acti vity

Control

Byte

TData

S P

Control

Byte

Word

Address (n) Control

Byte

TData (n)

Bus Activity

Master

SDA line

Bus Activity

Control

Byte Data n Data n + 1 D ata n + 2 Data n + X

Bus Acti vity

Master

SDA line

Bus Acti vity

24C02C

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXT

XXXXYYWW

NNN

8-Lead TSSOP Example:

24C02C

I/P 13F

0527

24C02CI

SN 0527

13F

8-Lead MSOP Example:

XXXX

TYWW

NNN

4C2C

I527

13F

XXXXT

YWWNNN

8-Lead 2x3 DFN

XXX

YWW

2P7

527

Example:

4C2CI

52713F

24C02C

Part Number

1st Line Marking Codes

TSSOP MSOP DFN

I Temp. E Temp.

24C02C 4C2C 4C2CT 2P7 2P8

Note: T = Temperature grade (I, E)

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the even t the fu ll Microc hip p art numb er ca nnot be mark ed on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

24C02C

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Sh oulder Width E . 300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24C02C

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot Angle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thi ckne ss

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Number of P ins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

24C02C

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thi ckne ss

0.700.600.50.028.024.020LFoot Len gth 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1Molded Package Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff § 0.950.900.85.037.035.033A2Molded Package Thickness 1.10.043AOverall Height 0.65.026

Pitch 88

Number of P ins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERS*INCHES

Units

Foot Angle φ048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per si de.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

24C02C

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REFFFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

24C02C

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

Exposed Pad Width

Exposed Pad Length

Contact Length

*Controlling Parameter

Contact Width

Drawing No. C04-123

Notes:

Exposed pad dimensions vary with paddle size.

Overall Width

.016

.012

.008

.047

.055

.010

.118 BSC

Number of Pins

Standoff

Contact Thickness

Overall Length

Overall Height

Pitch p

Units

Dimension Limits

.000 .001

.008 REF.

.079 BSC

.031

.020 BSC

MIN

INCHES

NOM

0.40

0.25

3.00 BSC

0.30

.020

.071

.012

.064

0.20

1.20

1.39

0.50

0.30

1.80

1.62

0.02

0.80

2.00 BSC

0.20 REF.

0.50 BSC

MILLIMETERS*

.002

.039

0.00

MINMAX NOM

0.05

1.00

MAX

Package may have one or more exposed tie bars at ends.1.

Pin 1 visual index feature may vary, but must be located within the hatched area.2.

0.90.035

(Note 3)

4. JEDEC equivalent: MO-229

A3 A1

TOP VIEW

EXPOSED

PAD

METAL

BOTTOM VIEW

(NOTE 1)

EXPOSED

TIE BAR

PIN 1

(NOTE 2)

ID INDEX

AREA

Revised 05/24/04

-- --

24C02C

APPENDIX A: REVISION HISTORY

Revision D

Corrections to Section 1.0, Electrical Characteristics.

Revision E

Added DFN package.

24C02C

NOTES:

24C02C

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

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SERVICE

Microchip’s customer notification service helps keep

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changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

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Notification and follow the registration instructions.

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Users of Microchip products can receive assistance

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Customers should contact their distributor,

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This line also provides information on how customers

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The Development Systems Information Line

numbers are:

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24C02C

READER RESPONSE

It is ou r intentio n to pro vi de you w it h th e best do cu me nt a t ion po ss ib le to e ns ure succes sfu l u se of y ou r Mic r oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

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Device: Literature Number:

Questions:

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DS21202E24C02C

1. What are the best features of thi s document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24C02C

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured

before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).

Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational diff erences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

PART NO. X/XX X

Lead FinishPackageTemperature

Range

Device

Device: 24C02C 2K I2C™ Serial EEPROM

24C02CT 2K I2C™ Serial EEPROM (Tape and Reel)

Temperature

Range: Blank = 0°C to +70°C

I= -40°C to +85°C

E= -40°C to +125°C

Package: P = Plastic DIP (300 mil Bod y), 8-le ad

SN = Plastic SOIC, (150 mil Body), 8-lead

ST = TSSOP (4.4 mm Body), 8-lead

MS = Plastic Micro Small Outline (MSOP), 8-lead

MC = 2x3 DFN, 8-lead

Lead Finish: Blank = Pb-free – Matte Tin (see Note 1)

G = Pb-free – Matte Tin only

24C02C

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

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RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

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Microchip disclaims all liability arising from this information and

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The Microchip name and logo, the Microchip logo, Accuron,

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PRO MATE, PowerSmart, rfPIC, and SmartShunt are

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in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Prog ra mming , IC SP, IC E P I C , MPASM, MPLI B, M PL I N K,

MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,

PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance and WiperLock are trademarks of Microchip

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SQTP is a service mark of Microchip Technology Incorporated

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

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• Microchip believes that its family of products is one of t he most secure famili es of its kind on t he market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

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Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving t he c ode protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

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devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

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03/01/05