IS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT MAY 2012 FEATURES DESCRIPTION * High-speed access times: 8, 10, 12 ns * High-performance, low-power CMOS process * Multiple center power and ground pins for greater noise immunity * Easy memory expansion with CE and OE options * CE power-down * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 3.3V power supply * Packages available: - 32-pin 300-mil SOJ - 32-pin 400-mil SOJ - 32-pin TSOP (Type II) - 32-pin STSOP (Type I) - 36-pin BGA (8mmx10mm) * Lead-free Available The ISSI IS63LV1024/IS63LV1024L is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The IS63LV1024/IS63LV1024L is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 W (typical) with CMOS input levels. The IS63LV1024/IS63LV1024L operates from a single 3.3V power supply and all inputs are TTL-compatible. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K X 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE CONTROL CIRCUIT WE Copyright (c) 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 1 IS63LV1024 IS63LV1024L PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type II) (T) 32-Pin STSOP (Type I) (H) A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE I/O0 6 27 I/O7 I/O1 7 26 I/O6 VDD 8 25 GND GND 9 24 VDD I/O2 10 23 I/O5 I/O3 11 22 I/O4 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 PIN DESCRIPTIONS 2 A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 PIN CONFIGURATION 36-mini BGA (B) (8 mm x 10 mm) A0-A16 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Data Inputs/Outputs VDD Power A GND Ground B I/O4 C I/O5 D GND E VDD F I/O6 G I/O7 H A9 1 2 3 4 5 6 A0 A1 NC A3 A6 A8 A2 WE A4 A7 I/O0 NC A5 I/O1 VDD GND NC NC OE CE A16 A15 I/O3 A10 A11 A12 A13 A14 I/O2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 IS63LV1024 IS63LV1024L TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE CE OE I/O Operation VDD Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.5 to VDD + 0.5 -65 to +150 1.0 Unit V C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 0.3V 3.3V 0.15V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = -4.0 mA 2.4 -- V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA -- 0.4 V VIH Input HIGH Voltage 2.2 VDD + 0.3 V VIL Input LOW Voltage(1) -0.3 0.8 V ILI Input Leakage GND VIN VDD Com. Ind. -1 -5 1 5 A ILO Output Leakage GND VOUT VDD, Outputs Disabled Com. Ind. -1 -5 1 5 A Note: 1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width under Vss < 5ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width over VDD < 5ns). Not 100% tested. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 3 IS63LV1024 IS63LV1024L IS63LV1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions ICC1 VDD Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = Max. ISB TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE VIH, f = Max ISB1 TTL Standby Current (TTL Inputs) ISB2 -8 ns Min. Max. Com. Ind. typ.(2) Ind. (@15 ns) -10 ns Min. Max. -12 ns Min. Max. Unit -- -- -- 160 170 105 -- -- -- 150 160 95 -- -- -- -- 130 140 75 90 mA Com. Ind. -- -- 55 55 -- -- 45 45 -- -- 40 40 mA VDD = Max., VIN = VIH or VIL CE VIH, f = 0 Com. Ind. -- -- 25 30 -- -- 25 30 -- -- 25 30 mA CMOS Standby Current VDD = Max., CE VDD - 0.2V, Com. Ind. typ.(2) -- -- -- 5 10 0.5 -- -- -- 5 10 0.5 -- -- -- 5 10 0.5 mA (CMOS Inputs) VIN VDD - 0.2V, or VIN 0.2V, f = 0 Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested. IS63LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. Symbol Parameter Test Conditions Unit ICC1 VDD Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = Max. Com. Ind. typ.(2) -- -- -- 100 110 75 -- -- -- 95 105 70 -- -- -- 90 100 65 mA ISB TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE VIH, f = Max Com. Ind. -- -- 35 40 -- -- 30 35 -- -- 25 30 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE VIH, f = 0 Com. Ind. -- -- 15 20 -- -- 15 20 -- -- 15 20 mA ISB2 CMOS Standby Current VDD = Max., CE VDD - 0.2V, Com. Ind. typ.(2) -- -- -- 1 1.5 0.05 -- -- -- 1 1.5 0.05 -- -- -- 1 1.5 0.05 mA (CMOS Inputs) VIN VDD - 0.2V, or VIN 0.2V, f = 0 Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested. CAPACITANCE(1,2) Symbol Parameter CIN CI/O Input Capacitance Input/Output Capacitance Conditions Max. Unit VIN = 0V VOUT = 0V 6 8 pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 IS63LV1024 IS63LV1024L READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -8 ns Min. Max. Parameter -10 ns Min. Max. -12 ns Min. Max. Unit tRC Read Cycle Time 8 -- 10 -- 12 -- ns tAA Address Access Time -- 8 -- 10 -- 12 ns tOHA Output Hold Time 2 -- 2 -- 2 -- ns tACE CE Access Time -- 8 -- 10 -- 12 ns tDOE OE Access Time -- 4 -- 5 -- 6 ns tLZOE(2) OE to Low-Z Output 0 -- 0 -- 0 -- ns tHZOE(2) OE to High-Z Output 0 4 0 5 0 6 ns tLZCE CE to Low-Z Output 3 -- 3 -- 3 -- ns tHZCE CE to High-Z Output 0 4 0 5 0 6 ns tPU CE to Power Up Time 0 -- 0 -- 0 -- ns tPD CE to Power Down Time -- 8 -- 10 -- 12 ns (2) (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V loading specified in Figure 1. 2. Tested with the loading specified in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 3.3V ZOUT = 50 OUTPUT OUTPUT 50 5 pF Including jig and scope VT = 1.5V Figure 1 Figure 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 351 5 IS63LV1024 IS63LV1024L AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE CE t LZOE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 IS63LV1024 IS63LV1024L WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -8 ns Min. Max. Parameter -10 ns Min. Max. -12 ns Min. Max. Unit tWC Write Cycle Time 8 -- 10 -- 12 -- ns tSCE CE to Write End 7 -- 7 -- 8 -- ns tAW Address Setup Time to Write End 8 -- 8 -- 8 -- ns tHA Address Hold from Write End 0 -- 0 -- 0 -- ns tSA Address Setup Time 0 -- 0 -- 0 -- ns (1) WE Pulse Width (OE High) 7 -- 7 -- 8 -- ns tPWE2(2) WE Pulse Width (OE Low) 8 -- 10 -- 12 -- ns tSD Data Setup to Write End 5 -- 5 -- 6 -- ns tPWE1 tHD Data Hold from Write End 0 -- 0 -- 0 -- ns (2) WE LOW to High-Z Output -- 4 -- 5 -- 6 ns tLZWE(2) WE HIGH to Low-Z Output 3 -- 3 -- 3 -- ns tHZWE Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. AC WAVEFORMS WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 7 IS63LV1024 IS63LV1024L AC WAVEFORMS WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS OE CE VALID ADDRESS t HA LOW LOW t AW t PWE2 WE tSA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 IS63LV1024 IS63LV1024L DATA RETENTION SWITCHING CHARACTERISTICS Min. Typ.(1) Max. Unit 2.0 -- 3.6 V -- -- 0.5 0.05 10 1.5 mA See Data Retention Waveform 0 -- -- ns See Data Retention Waveform tRC -- -- ns Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE VDD - 0.2V tSDR tRDR Data Retention Setup Time Recovery Time IS63LV1024 IS63LV1024L Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. O DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND CE VDD - 0.2V Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 9 IS63LV1024 IS63LV1024L IS63LV1024 ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. Package 8 IS63LV1024-8K IS63LV1024-8KL 400-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free 10 IS63LV1024-10T IS63LV1024-10J IS63LV1024-10K TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 12 IS63LV1024-12T IS63LV1024-12J IS63LV1024-12JL IS63LV1024-12KL TSOP (Type II) 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free 400-mil Plastic SOJ, Lead-free Industrial Range: -40C to +85C Speed (ns) Order Part No. Package 8 IS63LV1024-8KI 400-mil Plastic SOJ 10 IS63LV1024-10KI 400-mil Plastic SOJ 12 IS63LV1024-12TI TSOP (Type II) 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 IS63LV1024 IS63LV1024L IS63LV1024L ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. Package 8 IS63LV1024L-8T IS63LV1024L-8TL IS63LV1024L-8B TSOP (Type II) TSOP (Type II), Lead-free mBGA (8mmx10mm) 10 IS63LV1024L-10T IS63LV1024L-10TL IS63LV1024L-10HL TSOP (Type II) TSOP (Type II), Lead-free sTSOP (Type I) (8mm x13.4mm), Lead-free 12 IS63LV1024L-12T IS63LV1024L-12TL IS63LV1024L-12H IS63LV1024L-12JL IS63LV1024L-12B TSOP (Type II) TSOP (Type II), Lead-free sTSOP (Type I) (8mm x13.4mm) 300-mil Plastic SOJ, Lead-free mBGA (8mmx10mm) Industrial Range: -40C to +85C Speed (ns) Order Part No. Package 8 IS63LV1024L-8TI IS63LV1024L-8KI IS63LV1024L-8BI TSOP (Type II) 400-mil Plastic SOJ mBGA (8mmx10mm) 10 IS63LV1024L-10HI IS63LV1024L-10JLI IS63LV1024L-10KLI IS63LV1024L-10TLI sTSOP (Type I) (8mm x13.4mm) 300-mil Plastic SOJ, Lead-free 400-mil Plastic SOJ, Lead-free TSOP (Type II), Lead-free 12 IS63LV1024L-12BI IS63LV1024L-12BLI IS63LV1024L-12TI IS63LV1024L-12TLI mBGA (8mmx10mm) mBGA (8mmx10mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Special Part Numbers Industrial Range: -40C to +85C Speed (ns) 8 Top Mark Order Part No. Package IS63LV1024L-10KLI IS63LV1024L-10TLI U788B-8KLI U788A-8TLI 400-mil Plastic SOJ, Lead-free TSOP (Type II), Lead-free Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 11 IS63LV1024 IS63LV1024L 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 SEATING PLANE 3. Dimension b2 does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS-027. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : 12/19/2007 IS63LV1024 IS63LV1024L 13 IS63LV1024 IS63LV1024L 14 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 IS63LV1024 IS63LV1024L Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012 15 16 08/12/2008 Package Outline 1. Controlling dimension : mm 2. Reference document : JEDEC MO-207 NOTE : IS63LV1024 IS63LV1024L Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. P 05/09/2012