1/8August 2002
NEW DATASHEET ACCORDING TO PCN DSG/CT/1C02 MARKING: IRF530 @ .
IRF530
N-CHA NNE L 100 V - 0.115 - 14A TO-220
LOW GATE CHARGE STripFET™ II POWER MOSF ET
TYPICAL RDS(on) = 0.115
AVALANCHE RUGGED TECHNOLOGY
100% AVALANCHE TESTED
LOW GATE CHARGE
HIGH CURRENT CAPABILITY
175 oC OPERATING TEMPERATURE
DESCRIPTION
This MOSFET series realized with STMicroelectronics
unique STripFET™ process has specifically been
designed to minimize input capacitance and gate charge.
It is therefore suitable as primary switch in advanced
high-efficiency, high-frequency isolated DC-DC
converters for Telecom and Computer applications. It is
also intended for any applications with low gate drive
requirements.
APPLICATIONS
HIGH CURRENT, HIGH SWITCHING SPEED
SOLENOID AND RELAY DRI VERS
REGULATOR
DC-DC & DC-AC CONVERTERS
MOTOR CONTROL, AUDIO AMPLIFIERS
AUTOM OT IVE ENVIRONMENT (INJECTION,
ABS, AIR-BAG, LAMPDRIVERS, etc.)
TYPE VDSS RDS(on) ID
IRF530 100 V <0.16 14 A
123
TO-220
ABSOLUTE MAXIMUM RATINGS
(•) P ul se width li mited by safe operating area. (1) ISD 14A, di/dt 30 0A/ µ s , V DD V(BR)DSS, Tj TJMAX
(2) Starting Tj = 25 oC, ID = 14A, VDD = 50V
Symbol Parameter Value Unit
VDS Drain-so urce Voltag e (VGS = 0) 100 V
VDGR Drain-gate Voltage (RGS = 20 k)100 V
VGS Gate- source Voltage ± 20 V
IDDrain Current (continuous) at TC = 25°C 14 A
IDDrain Current (continuous) at TC = 100°C 10 A
IDM(•) Drain Current (pulsed) 56 A
Ptot Total Dissipation at TC = 25°C 60 W
Derating Factor 0.4 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 20 V/ns
EAS (2) Single Pulse Avalanche Energy 70 mJ
Tstg Storage Temperature -55 to 175 °C
TjOperating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
IRF530
2/8
THE RMAL DA TA
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise spe cified)
OFF
ON (*)
DYNAMIC
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max 2.5
62.5
300
°C/W
°C/W
°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source
Breakdown Voltage ID = 250 µA, VGS = 0 100 V
IDSS Zero Gate Voltage
Drain Current (VGS = 0) VDS = Max Rating
VDS = Max Rating TC = 100°C 1
10 µA
µA
IGSS Gate-body Leakage
Current (VDS = 0) VGS = ± 20 V ±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS = VGS I
D
= 250 µA 234V
R
DS(on) Static Drain-source On
Resistance VGS = 10 V ID = 7 A 0.115 0.16
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (*) Forward Transconductance VDS = 15 V ID=7 A 7S
C
iss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0 458
68
29
pF
pF
pF
3/8
IRF530
SWITCHIN G ON
SWITCHIN G OFF
SOURCE DRAIN DIODE
(*)P ulsed: P ul se durat i on = 3 00 µs, duty cycle 1.5 %.
(•)Puls e width l imi t ed by saf e operating area.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on)
trTurn-on Delay Time
Rise Time VDD = 50 V ID = 7 A
RG= 4.7 V
GS = 10 V
(Resistive Load, Figure 3)
16
25 ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 80V ID = 14A VGS= 10V 16
3.7
4.7
21 nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(off)
tfTurn-off Delay Time
Fall Time VDD = 50 V ID = 7 A
RG= 4.7Ω, V
GS = 10 V
(Resistive Load, Figure 3)
32
8ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD
ISDM ()Source-drain Current
Source-drain Current (pulsed) 14
56 A
A
VSD (*) Forward On Voltage ISD = 14 A VGS = 0 1.6 V
trr
Qrr
IRRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 14 A di/dt = 100A/µs
VDD = 10V Tj = 150°C
(see test circuit, Figure 5)
92
230
5
ns
nC
A
ELECTRICAL CHARACTERISTICS (continued)
Safe Operating Area Thermal Impedance
IRF530
4/8
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage Capacitance Variations
5/8
IRF530
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature
. .
IRF530
6/8
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Induc tive Wav eform
Fig. 3: Switching Times Test Circuits For Resistive
Load Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switchin g
And Diode Recovery Ti m es
7/8
IRF530
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
IRF530
8/8
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes n o responsibility for the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No lic ense is granted
by i m pl i cation or oth erwise unde r any pat ent or paten t rights of STMi croelectronics. Specifications ment i oned in this p ublicat i on are subject
to change without notice. This publication supersedes and repl aces all information previously supplied. STMicroel ectronics products are not
authorized for use as c ri tical com pone nt s i n l i f e support d evices or systems wi t hout express wri t ten approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
2002 ST M icroe le ctronics - All Ri ghts Reserv ed
All other names are the p roperty of their respective owner s.
STMicroelectronics GROUP OF C OMPANIES
Australia - Braz i l - Canada - Chi na - Finland - Fra n ce - Germ any - Hong Kong - India - Israel - It al y - Japan - Malaysia - M al ta - Morocco -
Singap ore - Spain - Sweden - Swit zerla nd - United Kingdom - United States.
http://www.st.com