1PS8306C 11/13/08
Product Pin Configuration
Functional Table
Logic Block Diagram
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PI6C2510A
Phase-Lock Loop Clock Driver
with 10-Clock Outputs
Description
The PI6C2510A family is a low-skew, low-jitter, phase-lock loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing one clock input to one bank of ten outputs,
with an output enable.
The PI6C2510A is designed to meet PC100 SDRAM Registered
DIMM Specification, for heavy load applications. For test pur-
poses, the PLL can be bypassed by strapping AVCC to ground.
The PI6C2510A family has the same pinouts as TI’s CDC2510A/
2510B, with enhanced rise/fall times, and allowing a Spread Spec-
trum clock input.
Features
•High-Performance Phase-Lock Loop Clock Distribution that
meets 100/134 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
•Allows Clock Input to have Spread Spectrum modulation for
EMI reduction
•Zero Input-to-Output delay: Distribute One Clock Input
to one bank of ten outputs, with an output enable.
•Same pinout as TI CDC2510/2510A
•Low jitter: Cycle-to-Cycle jitter ±100ps max.
•On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
•Operates at 3.3V VCC
•Wide Clock Frequency Range:
•Packaging
-24-pin TSSOP (L)
stupnIstuptuO
GNI_KLC]9:0[Y1TUO_BF
XL L L
LH L H
HH H H
G
10
CLK_IN
FB_IN
PLL
AVCC
FB_OUT
1Y[0:9]
CLK_IN
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FB_IN
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24-Pin
L