M38062M3-XXXFP - Renesas Electronics - Datasheet.Directory

To our custo mers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corpor ation took over all the business of both

companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid

Renesas Electronics document. W e appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights

of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas

Electronics products or the technology described in this document for any purpose relating to military applications or use by

the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and

technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Ren esas E lectronics assumes no liability whatsoever for any da mages

incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified acco rding to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior

written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way

liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an

application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written

consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise

expressly specified in a Renesas Electronics data sheets or data books, et c.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electro nic app liances; machine tool s; p ersonal electron ic equipment; and indu strial robots .

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equ i pment; submersible repeaters; nu clear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

interven tion (e.g. excision, et c.), and any oth er applications or purposes that pose a direct th reat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,

Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for det ai ls as to enviro nmental matters such as the en vi ronmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS

Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with

applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this

document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

Regarding the change of names mentioned in the document, such as Mitsubishi

Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

3806 Group

User’s Manual

8

User’s Manual

Rev.1.0 2003.04

RENESAS 8-BIT SINGLE-CHIP

MICROCOMPUTER

740 FAMILY / 38000 SERIES

Notes regarding these materials

These materials are intended as a reference to assist our customers in the

selection of the Mitsubishi semiconductor product best suited to the

customer’s application; they do not convey any license under any

intellectual property rights, or any other rights, belonging to Mitsubishi

Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage,

or infringement of any third-party’s rights, originating in the use of any

product data, diagrams, charts or circuit application examples contained in

these materials.

All information contained in these materials, including product data,

diagrams and charts, represent information on products at the time of

publication of these materials, and are subject to change by Mitsubishi

Electric Corporation without notice due to product improvements or other

reasons. It is therefore recommended that customers contact Mitsubishi

Electric Corporation or an authorized Mitsubishi Semiconductor product

distributor for the latest product information before purchasing a product

listed herein.

Mitsubishi Electric Corporation semiconductors are not designed or

manufactured for use in a device or system that is used under

circumstances in which human life is potentially at stake. Please contact

Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor

product distributor when considering the use of a product contained herein

for any specific purposes, such as apparatus or systems for transportation,

vehicular, medical, aerospace, nuclear, or undersea repeater use.

The prior written approval of Mitsubishi Electric Corporation is necessary to

reprint or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export

control restrictions, they must be exported under a license from the

Japanese government and cannot be imported into a country other than

the approved destination.

Any diversion or reexport contrary to the export control laws and

regulations of Japan and/or the country of destination is prohibited.

Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi

Semiconductor product distributor for further details on these materials or

the products contained therein.

Keep safety first in your circuit designs!

Mitsubishi Electric Corporation puts the maximum effort into making

semiconductor products better and more reliable, but there is always the

possibility that trouble may occur with them. Trouble with semiconductors

may lead to personal injury, fire or property damage. Remember to give due

consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of

non-flammable material or (iii) prevention against any malfunction or mishap.

Preface

This user’s manual describes Mitsubishi’s CMOS 8-

bit microcomputers 3806 Group.

After reading this manual, the user should have a

through knowledge of the functions and features of

the 3806 Group, and should be able to fully utilize

the product. The manual starts with specifications

and ends with application examples.

For details of software, refer to the “SERIES MELPS

740 <SOFTWARE> USER’S MANUAL.”

For details of development support tools, refer to the

“DEVELOPMENT SUPPORT TOOLS FOR MICRO-

COMPUTERS” data book.

BEFORE USING THIS USER’S MANUAL

This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such

as hardware design or software development. Chapter 3 also includes necessary information for systems denelopment.

Be sure to refer to this chapter.

1. Organization

● CHAPTER 1 HARDWARE

This chapter describes features of the microcomputer and operation of each peripheral function.

● CHAPTER 2 APPLICATION

This chapter describes usage and application examples of peripheral functions, based mainly on setting examples

of related registers.

● CHAPTER 3 APPENDIX

This chapter includes necessary information for systems development using the microcomputer, electric

characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which

are to be submitted when ordering.

2. Structure of register

The figure of each register structure describes its functions, contents at reset, and attributes as follows :

Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only

and read and write. In the figure, these attributes are represented as follows :

: Bit in which nothing is arranged

0 1 :

Name Function At reset RWB

0

1

2

3

4

0

0

0

0

0✕

✕

5

6

7

1

✻

b0b1b2b3b4b5b6b7

Contents immediately after reset release

Bit attributes

(Note 1)

Processor mode bits

Stack page selection bit

Nothing arranged for these bits. These are write disabled

bits. When these bits are read out, the contents are “0.”

Fix this bit to “0.”

Main clock (XIN-XOUT) stop bit

Internal system clock selection bit

0 0 : Single-chip mode

1 0 :

1 1 : Not available

b1 b0

0 : 0 page

1 : 1 page

0 : Operating

1 : Stopped

0 : XIN-XOUT selected

1 : XCIN-XCOUT selected

: Bit that is not used for control of the corresponding function

0

Note 1. Contents immediately after reset release

0••••••“0” at reset release

1••••••“1” at reset release

Undefined••••••Undefined or reset release

••••••Contents determined by option at reset release

✻

R••••••Read

••••••Read enabled

✕••••••Read disabled

W••••••Write

••••••Write enabled

✕ ••••••Write disabled

(Note 2)

✻

CPU mode register (CPUM) [Address : 3B16]

Bits

LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS

3806 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with

standard functions.

The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the

detailed functions of each group, refer to the related data book and user’s manual.

Prescaler : 3

Timer : 4

<8-bit>

—

—

—

Function Group

Pin

(Package type)

Timer

A-D converter

D-A converter

Clock generating circuit

Serial I/O

Remarks

One Time

PROM

EPROM

RAM

Mask

ROM

Memory

type

✽

24K

512 384

32K

8K

16K 32K

16K

(Note 1)

8K

(Note 1) 16K

(Note 1) 32K

(Note 1)

384 384 640

—

—

—

—

—

8K

(Note 1) 24K

384 384 640

16K

(Note 1) 32K

(Note 1)

32K

(Note 1)

32K

1024

—

—

PWM output

512

16K

16K

16K

3800 group

64 pin

• 64P4B

• 64P6N-A

• 64P6D-A

1 circuit

Prescaler : 3

Timer : 4

<8-bit>

UART or

Clock synchronous ✕ 1

3802 group

64 pin

• 64P4B

• 64P6N-A

8-bit ✕ 8-channel

8-bit ✕ 2-channel

UART or

Clock synchronous ✕ 1

Clock synchronous ✕ 1

1 circuit 1 circuit

Prescaler : 3

Timer : 4

<8-bit>

UART or

Clock synchronous ✕ 1

Clock synchronous ✕ 1

3806 group 3807 group

80 pin

• 80P6N-A

2 circuits

8-bit ✕ 13-channel

8-bit ✕ 4-channel

UART or

Clock synchronous ✕ 1

Clock synchronous ✕ 1

Timer : 3

<8-bit>

Timer X/Y : 2

Timer A/B : 2

<16-bit>

80 pin

• 80P6N-A

• 80P6S-A

• 80P6D-A

12K

(Note 1) 16K

(Note 1) 24K

(Note 3)

24K

32K

(Note 3)48K

(Note 3)

1024512384 384 1024

24K

(Note 2) 48K

(Note 3)

—

—

—

—

—

—

8-bit ✕ 8-channel

8-bit ✕ 2-channel

As of September 1995

Real time port output

Analog comparator

Watchdog timer

48K

(Note 2)

Notes 1: Extended operating temperature version available

2: High-speed version available

3: Extended operating temperature version and High-speed version available

✽. ROM expansion

List of groups having the same functions

——

——

i

Table of contents

3806 GROUP USER'S MANUAL

Table of contents

CHAPTER 1. HARDWARE

DESCRIPTION ................................................................................................................................ 1-2

FEATURES...................................................................................................................................... 1-2

APPLICATIONS.............................................................................................................................. 1-2

PIN CONFIGURATION .................................................................................................................. 1-2

FUNCTIONAL BLOCK................................................................................................................... 1-4

PIN DESCRIPTION ........................................................................................................................ 1-5

PART NUMBERING....................................................................................................................... 1-7

GROUP EXPANSION .................................................................................................................... 1-8

GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) ................. 1-10

GROUP EXPANSION (HIGH-SPEED VERSION) .................................................................... 1-11

FUNCTIONAL DESCRIPTION .................................................................................................... 1-12

Central Processing Unit (CPU) ............................................................................................ 1-12

Memory .................................................................................................................................... 1-16

I/O Ports .................................................................................................................................. 1-18

Interrupts ................................................................................................................................. 1-21

Timers ...................................................................................................................................... 1-23

Serial I/O ................................................................................................................................. 1-25

A-D Converter......................................................................................................................... 1-31

D-A Converter......................................................................................................................... 1-32

Reset Circuit ........................................................................................................................... 1-31

Clock Generating Circuit ....................................................................................................... 1-35

Processor Modes.................................................................................................................... 1-36

NOTES ON PROGRAMMING ..................................................................................................... 1-38

Processor Status Register .................................................................................................... 1-38

Interrupts ................................................................................................................................. 1-38

Decimal Calculations.............................................................................................................. 1-38

Timers ...................................................................................................................................... 1-38

Multiplication and Division Instructions ............................................................................... 1-38

Ports......................................................................................................................................... 1-38

Serial I/O ................................................................................................................................. 1-38

A-D Converter......................................................................................................................... 1-38

D-A Converter......................................................................................................................... 1-38

Instruction Execution Time.................................................................................................... 1-38

Memory Expansion Mode and Microprocessor Mode ....................................................... 1-38

DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-39

ii 3806 GROUP USER'S MANUAL

Table of contents

ROM PROGRAMMING METHOD .............................................................................................. 1-39

FUNCTIONAL DESCRIPTION SUPPLEMENT......................................................................... 1-40

Interrupt ................................................................................................................................... 1-40

Timing After Interrupt............................................................................................................. 1-41

A-D Converter......................................................................................................................... 1-42

CHAPTER 2. APPLICATION

2.1 I/O port ..................................................................................................................................... 2-2

2.1.1 Memory map of I/O port ............................................................................................... 2-2

2.1.2 Related registers ............................................................................................................ 2-3

2.1.3 Handling of unused pins ............................................................................................... 2-4

2.2 Timer......................................................................................................................................... 2-5

2.2.1 Memory map of timer .................................................................................................... 2-5

2.2.2 Related registers ............................................................................................................ 2-6

2.2.3 Timer application examples ........................................................................................ 2-11

2.3 Serial I/O ................................................................................................................................ 2-23

2.3.1 Memory map of serial I/O ........................................................................................... 2-23

2.3.2 Related registers .......................................................................................................... 2-24

2.3.3 Serial I/O connection examples ................................................................................. 2-30

2.3.4 Setting of serial I/O transfer data format ................................................................. 2-32

2.3.5 Serial I/O application examples ................................................................................. 2-33

2.4 A-D converter ....................................................................................................................... 2-53

2.4.1 Memory map of A-D conversion ................................................................................ 2-53

2.4.2 Related registers .......................................................................................................... 2-54

2.4.3 A-D conversion application example ......................................................................... 2-56

2.5 Processor mode ................................................................................................................... 2-58

2.5.1 Memory map of processor mode............................................................................... 2-58

2.5.2 Related register ............................................................................................................ 2-58

2.5.3 Processor mode application examples ...................................................................... 2-59

2.6 Reset....................................................................................................................................... 2-66

2.6.1 Connection example of reset IC ................................................................................ 2-66

CHAPTER 3. APPENDIX

3.1 Electrical characteristics ..................................................................................................... 3-2

3.1.1 Absolute maximum ratings ............................................................................................ 3-2

3.1.2 Recommended operating conditions ............................................................................ 3-3

3.1.3 Electrical characteristics................................................................................................ 3-4

3.1.4 A-D converter characteristics ....................................................................................... 3-4

3.1.5 D-A converter characteristics ....................................................................................... 3-5

3.1.6 Timing requirements and Switching characteristics .................................................. 3-6

3.1.7 Absolute maximum ratings (Extended operating temperature version)................ 3-10

3.1.8 Recommended operating conditions(Extended operating temperature version).. 3-10

iii

Table of contents

3806 GROUP USER'S MANUAL

3.1.9 Electrical characteristics (Extended operating temperature version) .................... 3-11

3.1.10 A-D converter characteristics (Extended operating temperature version) ........ 3-11

3.1.11 D-A converter characteristics (Extended operating temperature version) ........ 3-12

3.1.12 Timing requirements and Switching characteristics

(Extended operating temperature version).......................................................... 3-13

3.1.13 Absolute maximum ratings (High-speed version) .................................................. 3-15

3.1.14 Recommended operating conditions(High-speed version).................................... 3-15

3.1.15 Electrical characteristics (High-speed version) ...................................................... 3-16

3.1.16 A-D converter characteristics (High-speed version) ............................................ 3-16

3.1.17 D-A converter characteristics (High-speed version) ............................................ 3-17

3.1.18 Timing requirements and Switching characteristics (High-speed version) ......... 3-18

3.1.19 Timing diagram ........................................................................................................... 3-22

3.2 Standard characteristics.................................................................................................... 3-25

3.2.1 Power source current characteristic examples ........................................................ 3-25

3.2.2 Port standard characteristic examples ...................................................................... 3-26

3.2.3 A-D conversion standard characteristics................................................................... 3-28

3.2.4 D-A conversion standard characteristics................................................................... 3-29

3.3 Notes on use ........................................................................................................................ 3-30

3.3.1 Notes on interrupts ...................................................................................................... 3-30

3.3.2 Notes on the serial I/O1 ............................................................................................. 3-30

3.3.3 Notes on the A-D converter ....................................................................................... 3-31

3.3.4 Notes on the RESET pin ............................................................................................ 3-32

3.3.5 Notes on input and output pins ................................................................................. 3-32

3.3.6 Notes on memory expansion mode and microprocessor mode ............................ 3-33

3.3.7 Notes on built-in PROM .............................................................................................. 3-34

3.4 Countermeasures against noise ...................................................................................... 3-36

3.4.1 Shortest wiring length .................................................................................................. 3-36

3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line............ 3-37

3.4.3 Wiring to analog input pins ........................................................................................ 3-38

3.4.4 Consideration for oscillator ......................................................................................... 3-38

3.4.5 Setup for I/O ports ....................................................................................................... 3-39

3.4.6 Providing of watchdog timer function by software .................................................. 3-39

3.5 List of registers ................................................................................................................... 3-41

3.6 Mask ROM ordering method............................................................................................. 3-53

3.7 Mark specification form ..................................................................................................... 3-79

3.8 Package outline ................................................................................................................... 3-81

3.9 List of instruction codes ................................................................................................... 3-83

3.10 Machine Instructions ........................................................................................................ 3-84

3.11 SFR memory map .............................................................................................................. 3-94

3.12 Pin configuration ............................................................................................................... 3-95

3806 GROUP USER’S MANUAL i

List of figures

List of figures

CHAPTER 1 HARDWARE

Fig. 1 Pin configuration of M38063M6-XXXFP .......................................................................... 1-2

Fig. 2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP ............................. 1-3

Fig. 3 Functional block diagram .................................................................................................. 1-4

Fig. 4 Part numbering ................................................................................................................... 1-7

Fig. 5 Memory expansion plan .................................................................................................... 1-8

Fig. 6 Memory expansion plan (Extended operating temperature version)........................ 1-10

Fig. 7 Memory expansion plan (High-speed version) ............................................................ 1-11

Fig. 8 740 Family CPU register structure................................................................................ 1-12

Fig. 9 Register push and pop at interrupt generation and subroutine call ........................ 1-13

Fig. 10 Structure of CPU mode register .................................................................................. 1-15

Fig. 11 Memory map diagram.................................................................................................... 1-16

Fig. 12 Memory map of special function register (SFR) ....................................................... 1-17

Fig. 13 Port block diagram (single-chip mode) (1)................................................................. 1-19

Fig. 14 Port block diagram (single-chip mode) (2)................................................................. 1-20

Fig. 15 Interrupt control .............................................................................................................. 1-22

Fig. 16 Structure of interrupt-related registers ........................................................................ 1-22

Fig. 17 Structure of timer XY register...................................................................................... 1-23

Fig. 18 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-24

Fig. 19 Block diagram of clock synchronous serial I/O1....................................................... 1-25

Fig. 20 Operation of clock synchronous serial I/O1 function ............................................... 1-25

Fig. 21 Block diagram of UART serial I/O............................................................................... 1-26

Fig. 22 Operation of UART serial I/O function ....................................................................... 1-27

Fig. 23 Structure of serial I/O control registers...................................................................... 1-28

Fig. 24 Structure of serial I/O2 control register...................................................................... 1-29

Fig. 25 Block diagram of serial I/O2 function ......................................................................... 1-29

Fig. 26 Timing of serial I/O2 function....................................................................................... 1-30

Fig. 27 Structure of AD/DA control register ............................................................................ 1-31

Fig. 28 Block diagram of A-D converter .................................................................................. 1-31

Fig. 29 Block diagram of D-A converter .................................................................................. 1-32

Fig. 30 Equivalent connection circuit of D-A converter ......................................................... 1-32

Fig. 31 Example of reset circuit ................................................................................................ 1-33

Fig. 32 Internal status of microcomputer after reset.............................................................. 1-33

Fig. 33 Timing of reset ............................................................................................................... 1-34

Fig. 34 Ceramic resonator circuit.............................................................................................. 1-35

Fig. 35 External clock input circuit ........................................................................................... 1-35

Fig. 36 Block diagram of clock generating circuit..................................................................................1-35

Fig. 37 Memory maps in various processor modes ............................................................... 1-36

Fig. 38 Structure of CPU mode register .................................................................................. 1-36

Fig. 39 ONW function timing...................................................................................................... 1-37

Fig. 40 Programming and testing of One Time PROM version ........................................... 1-39

Fig. 41 Timing chart after an interrupt occurs ........................................................................ 1-41

Fig. 42 Time up to execution of the interrupt processing routine ....................................... 1-41

Fig. 43 A-D conversion equivalent circuit ................................................................................ 1-43

Fig. 44 A-D conversion timing chart......................................................................................... 1-43

ii 3806 GROUP USER’S MANUAL

List of figures

CHAPTER 2 APPLICATION

Fig. 2.1.1 Memory map of I/O port related registers................................................................ 2-2

Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7, 8)...................................................... 2-3

Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ....................... 2-3

Fig. 2.2.1 Memory map of timer related registers..................................................................... 2-5

Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y.............................................. 2-6

Fig. 2.2.3 Structure of Timer 1 .................................................................................................... 2-6

Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y ................................................................... 2-7

Fig. 2.2.5 Structure of Timer XY mode register ........................................................................ 2-8

Fig. 2.2.6 Structure of Interrupt request register 1 ................................................................... 2-9

Fig. 2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9

Fig. 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10

Fig. 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10

Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12

Fig. 2.2.11 Setting of related registers [Clock function]......................................................... 2-13

Fig. 2.2.12 Control procedure [Clock function] ........................................................................ 2-14

Fig. 2.2.13 Example of a peripheral circuit .............................................................................. 2-15

Fig. 2.2.14

Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]

.......... 2-15

Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]................................... 2-16

Fig. 2.2.16 Control procedure [Piezoelectric buzzer output].................................................. 2-16

Fig. 2.2.17 A method for judging if input pulse exists ........................................................... 2-17

Fig. 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18

Fig. 2.2.19 Control procedure [Measurement of frequency]................................................... 2-19

Fig. 2.2.20

Connection of the timer and setting of the division ratio [Measurement of pulse width] ...........

2-20

Fig. 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21

Fig. 2.2.22 Control procedure [Measurement of pulse width] ................................................ 2-22

Fig. 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23

Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24

Fig. 2.3.3 Structure of Serial I/O1 status register................................................................... 2-24

Fig. 2.3.4 Structure of Serial I/O1 control register .................................................................. 2-25

Fig. 2.3.5 Structure of UART control register .......................................................................... 2-25

Fig. 2.3.6 Structure of Baud rate generator............................................................................. 2-26

Fig. 2.3.7 Structure of Serial I/O2 control register .................................................................. 2-26

Fig. 2.3.8 Structure of Serial I/O2 register ............................................................................... 2-27

Fig. 2.3.9 Structure of Interrupt edge selection register ........................................................ 2-27

Fig. 2.3.10 Structure of Interrupt request register 1............................................................... 2-28

Fig. 2.3.11 Structure of Interrupt request register 2............................................................... 2-28

Fig. 2.3.12 Structure of Interrupt control register 1 ................................................................ 2-29

Fig. 2.3.13 Structure of Interrupt control register 2 ................................................................ 2-29

Fig. 2.3.14 Serial I/O connection examples (1)....................................................................... 2-30

Fig. 2.3.15 Serial I/O connection examples (2)....................................................................... 2-31

Fig. 2.3.16 Setting of Serial I/O transfer data format ............................................................. 2-32

Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] .. 2-33

Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]............... 2-33

Fig. 2.3.19 Setting of related registers at a transmitting side

[Communication using a clock synchronous serial I/O] ................................ 2-34

Fig. 2.3.20 Setting of related registers at a receiving side

[Communication using a clock synchronous serial I/O] ................................ 2-35

3806 GROUP USER’S MANUAL iii

List of figures

Fig. 2.3.21 Control procedure at a transmitting side

[Communication using a clock synchronous serial I/O].................................. 2-36

Fig. 2.3.22

Control procedure at a receiving side[Communication using a clock synchronous serial I/O]

. 2-37

Fig. 2.3.23 Connection diagram [Output of serial data] ......................................................... 2-38

Fig. 2.3.24 Timing chart [Output of serial data] ...................................................................... 2-38

Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data] .......................... 2-39

Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data] ....................... 2-39

Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data] .................................... 2-40

Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data] .......................... 2-41

Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data] ....................... 2-41

Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] .................................... 2-42

Fig. 2.3.31 Connection diagram

[Cyclic transmission or reception of block data between microcomputers] . 2-43

Fig. 2.3.32

Timing chart [Cyclic transmission or reception of block data between microcomputers] ..........

2-44

Fig. 2.3.33 Setting of related registers

[Cyclic transmission or reception of block data between microcomputers] . 2-44

Fig. 2.3.34 Control in the master unit....................................................................................... 2-45

Fig. 2.3.35 Control in the slave unit ......................................................................................... 2-46

Fig. 2.3.36 Connection diagram [Communication using UART] ............................................ 2-47

Fig. 2.3.37 Timing chart [Communication using UART] ......................................................... 2-47

Fig. 2.3.38

Setting of related registers at a transmitting side [Communication using UART]........................

2-49

Fig. 2.3.39

Setting of related registers at a receiving side [Communication using UART] ............................

2-50

Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] ......... 2-51

Fig. 2.3.41 Control procedure at a receiving side [Communication using UART].............. 2-52

Fig. 2.4.1 Memory map of A-D conversion related registers ................................................. 2-53

Fig. 2.4.2 Structure of AD/DA control register ......................................................................... 2-54

Fig. 2.4.3 Structure of A-D conversion register ....................................................................... 2-54

Fig. 2.4.4 Structure of Interrupt request register 2 ................................................................. 2-55

Fig. 2.4.5 Structure of Interrupt control register 2 .................................................................. 2-55

Fig. 2.4.6 Connection diagram [Conversion of Analog input voltage] .................................. 2-56

Fig. 2.4.7 Setting of related registers [Conversion of Analog input voltage] ...................... 2-56

Fig. 2.4.8 Control procedure [Conversion of Analog input voltage] ...................................... 2-57

Fig. 2.5.1 Memory map of processor mode related register ................................................. 2-58

Fig. 2.5.2 Structure of CPU mode register .............................................................................. 2-58

Fig. 2.5.3 Expansion example of ROM and RAM ................................................................... 2-59

Fig. 2.5.4 Read-cycle (OE access, SRAM) .............................................................................. 2-60

Fig. 2.5.5 Read-cycle (OE access, EPROM) ........................................................................... 2-60

Fig. 2.5.6 Write-cycle (W control, SRAM)................................................................................. 2-61

Fig. 2.5.7 Application example of the ONW function .............................................................. 2-62

Fig. 2.5.8 Expansion example of ROM and RAM [High-speed version] .............................. 2-63

Fig. 2.5.9 Read-cycle (OE access, SRAM) [High-speed version] ......................................... 2-64

Fig. 2.5.10 Read-cycle (OE access, EPROM) [High-speed version].................................... 2-64

Fig. 2.5.11 Write-cycle (W control, SRAM) [High-speed version] ......................................... 2-65

Fig. 2.6.1 Example of Poweron reset circuit............................................................................ 2-66

Fig. 2.6.2 RAM back-up system ................................................................................................. 2-66

iv 3806 GROUP USER’S MANUAL

List of figures

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ................................... 3-21

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ................................... 3-21

Fig. 3.1.3 Timing diagram (in single-chip mode)..................................................................... 3-22

Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (1).. 3-23

Fig. 3.1.5 Timing diagram (in memory expansion mode and microprocessor mode) (2).. 3-24

Fig. 3.2.1 Power source current characteristic example ........................................................ 3-25

Fig. 3.2.2 Power source current characteristic example (in wait mode) .............................. 3-25

Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) .. 3-26

Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) .. 3-26

Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1).. 3-27

Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2).. 3-27

Fig. 3.2.7 A-D conversion standard characteristics ................................................................. 3-28

Fig. 3.2.8 D-A conversion standard characteristics ................................................................. 3-29

Fig. 3.3.1 Structure of interrupt control register 2 .................................................................. 3-30

Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-36

Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-37

Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ........ 3-37

Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line...................................... 3-37

Fig. 3.4.5 Analog signal line and a resistor and a capacitor ................................................ 3-38

Fig. 3.4.6 Wiring for a large current signal line ...................................................................... 3-38

Fig. 3.4.7 Wiring to a signal line where potential levels change frequently ....................... 3-38

Fig. 3.4.8 Stepup for I/O ports ................................................................................................... 3-39

Fig. 3.4.9 Watchdog timer by software..................................................................................... 3-39

Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7, 8).................................................... 3-41

Fig. 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ..................... 3-41

Fig. 3.5.3 Structure of Transmit/Receive buffer register ........................................................ 3-42

Fig. 3.5.4 Structure of Serial I/O1 status register................................................................... 3-42

Fig. 3.5.5 Structure of Serial I/O1 control register .................................................................. 3-43

Fig. 3.5.6 Structure of UART control register .......................................................................... 3-43

Fig. 3.5.7 Structure of Baud rate generator............................................................................. 3-44

Fig. 3.5.8 Structure of Serial I/O2 control register .................................................................. 3-44

Fig. 3.5.9 Structure of Serial I/O2 register ............................................................................... 3-45

Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y.......................................... 3-45

Fig. 3.5.11 Structure of Timer 1 ................................................................................................ 3-46

Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-46

Fig. 3.5.13 Structure of Timer XY mode register.................................................................... 3-47

Fig. 3.5.14 Structure of AD/DA control register....................................................................... 3-48

Fig. 3.5.15 Structure of A-D conversion register ..................................................................... 3-48

Fig. 3.5.16 Structure of D-A 1 conversion, D-A 2 conversion register ................................ 3-49

Fig. 3.5.17 Structure of Interrupt edge selection register ...................................................... 3-49

Fig. 3.5.18 Structure of CPU mode register ............................................................................ 3-50

Fig. 3.5.19 Structure of Interrupt request register 1............................................................... 3-51

Fig. 3.5.20 Structure of Interrupt request register 2............................................................... 3-51

Fig. 3.5.21 Structure of Interrupt control register 1 ................................................................ 3-52

Fig. 3.5.22 Structure of Interrupt control register 2 ................................................................ 3-52

3806 GROUP USER’S MANUAL i

List of tables

List of tables

CHAPTER 1 HARDWARE

Table 1 Pin description (1) ........................................................................................................... 1-5

Table 2 Pin description (2) ........................................................................................................... 1-6

Table 3 List of supported products ............................................................................................. 1-9

Table 4 List of supported products (Extended operating temperature version) .................. 1-10

Table 5 List of supported products (High-speed version)...................................................... 1-11

Table 6 Push and pop instructions of accumulator or processor status register............... 1-13

Table 7 Set and clear instructions of each bit of processor status register....................... 1-14

Table 8 List of I/O port functions .............................................................................................. 1-18

Table 9 Interrupt vector addresses and priority ...................................................................... 1-21

Table 10 Functions of ports in memory expansion mode and microprocessor mode ....... 1-36

Table 11 Programming adapter .................................................................................................. 1-39

Table 12 Interrupt sources, vector addresses and interrupt priority ..................................... 1-40

Table 13 Change of A-D conversion register during A-D conversion .................................. 1-42

CHAPTER 2 APPLICATION

Table 2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2-4

Table 2.1.2 Handling of unused pins (

in memory expansion mode and microprocessor mode

) ........ 2-4

Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit .......................................................... 2-8

Table 2.3.1

Setting examples of Baud rate generator values and transfer bit rate values

...................... 2-48

CHAPTER 3 APPENDIX

Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2

Table 3.1.2 Recommended operating conditions ....................................................................... 3-3

Table 3.1.3 Electrical characteristics........................................................................................... 3-4

Table 3.1.4 A-D converter characteristics .................................................................................. 3-4

Table 3.1.5 D-A converter characteristics .................................................................................. 3-5

Table 3.1.6 Timing requirements (1) ........................................................................................... 3-6

Table 3.1.7 Timing requirements (2) ........................................................................................... 3-6

Table 3.1.8 Switching characteristics (1).................................................................................... 3-7

Table 3.1.9 Switching characteristics (2).................................................................................... 3-7

Table 3.1.10

Timing requirements in memory expansion mode and microprocessor mode (1) ......................

3-8

Table 3.1.11

Switching characteristics in memory expansion mode and microprocessor mode (1) ..............

3-8

Table 3.1.12

Timing requirements in memory expansion mode and microprocessor mode (2) ......................

3-9

Table 3.1.13

Switching characteristics in memory expansion mode and microprocessor mode (2) ..............

3-9

Table 3.1.14 Absolute maximum ratings (Extended operating temperature version)......... 3-10

Table 3.1.15 Recommended operating conditions (

Extended operating temperature version

) ..... 3-10

Table 3.1.16 Electrical characteristics (Extended operating temperature version)............. 3-11

Table 3.1.17 A-D converter characteristics (Extended operating temperature version)..... 3-11

Table 3.1.18 D-A converter characteristics (Extended operating temperature version)..... 3-12

Table 3.1.19 Timing requirements (Extended operating temperature version).................... 3-13

Table 3.1.20 Switching characteristics (Extended operating temperature version) ............ 3-13

ii 3806 GROUP USER’S MANUAL

List of tables

Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode

(Extended operating temperature version)................................................... 3-14

Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode

(Extended operating temperature version)................................................... 3-14

Table 3.1.23 Absolute maximum ratings (High-speed version) ............................................. 3-15

Table 3.1.24 Recommended operating conditions (High-speed version) ............................. 3-15

Table 3.1.25 Electrical characteristics (High-speed version) ................................................. 3-16

Table 3.1.26 A-D converter characteristics (High-speed version)......................................... 3-16

Table 3.1.27 D-A converter characteristics (High-speed version)......................................... 3-17

Table 3.1.28 Timing requirements (1) (High-speed version) ................................................. 3-18

Table 3.1.29 Timing requirements (2) (High-speed version) ................................................. 3-18

Table 3.1.30 Switching characteristics (1) (High-speed version) .......................................... 3-19

Table 3.1.31 Switching characteristics (2) (High-speed version) .......................................... 3-19

Table 3.1.32

Timing requirements in memory expansion mode and microprocessor mode (1)

(High-speed version)....................................................................................... 3-20

Table 3.1.33

Switching characteristics in memory expansion mode and microprocessor mode (1)

(High-speed version)....................................................................................... 3-20

Table 3.1.34

Timing requirements in memory expansion mode and microprocessor mode (2)

(High-speed version)....................................................................................... 3-21

Table 3.1.35

Switching characteristics in memory expansion mode and microprocessor mode (2)

(High-speed version)....................................................................................... 3-21

Table 3.3.1 Programming adapter ............................................................................................. 3-34

Table 3.3.2 Setting of programming adapter switch ............................................................... 3-34

Table 3.3.3 Setting of PROM programmer address ................................................................ 3-35

Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit ........................................................ 3-47

CHAPTER 1

HARDWARE

DESCRIPTION

FEATURES

APPLICATIONS

PIN CONFIGURATION

FUNCTIONAL BLOCK

PIN DESCRIPTION

PART NUMBERING

GROUP EXPANSION

FUNCTIONAL DESCRIPTION

NOTES ON PROGRAMMING

DATA REQUIRED FOR MASK

ORDERS

ROM PROGRAMMING METHOD

FUNCTIONAL DESCRIPTION

SUPPLEMENT

HARDWARE

3806 GROUP USER’S MANUAL

1-2

DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION

PIN CONFIGURATION (TOP VIEW)

Fig. 1 Pin configuration of M38063M6-XXXFP

Package type : 80P6N-A

80-pin plastic-molded QFP

DESCRIPTION

The 3806 group is 8-bit microcomputer based on the 740 family

core technology.

The 3806 group is designed for controlling systems that require

analog signal processing and include two serial I/O functions, A-D

converters, and D-A converters.

The various microcomputers in the 3806 group include variations

of internal memory size and packaging. For details, refer to the

section on part numbering.

For details on availability of microcomputers in the 3806 group, re-

fer to the section on group expansion.

FEATURES

•Basic machine-language instructions....................................... 71

•Memory size

ROM ................................................................ 12 K to 48 K bytes

RAM ................................................................. 384 to 1024 bytes

•Programmable input/output ports ............................................. 72

•Interrupts .................................................. 16 sources, 16 vectors

•Timers ............................................................................. 8 bit ✕ 4

•Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)

•Serial I/O2 ....................................8-bit ✕ 1 (Clock-synchronized)

•A-D converter .................................................. 8-bit ✕ 8 channels

•D-A converter .................................................. 8-bit ✕ 2 channels

•Clock generating circuit ....................... Internal feedback resistor

(connect to external ceramic resonator or quartz-crystal)

•Memory expansion possible

APPLICATIONS

Office automation, VCRs, tuners, musical instruments, cameras,

air conditioners, etc.

Specification

(unit)

Minimum instruction

execution time (µs)

Oscillation frequency

(MHz)

Power source voltage

(V)

Power dissipation

(mW)

Operating temperature

range

(°C)

Standard

0.5

8

3.0 to 5.5

32

–20 to 85

0.5

8

4.0 to 5.5

32

–40 to 85

Extended operating

temperature version

0.4

10

2.7 to 5.5

40

–20 to 85

High-speed

version

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24 41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

P3

0

P3

1

P3

4

/φ

P3

5

/SYNC

P0

0

/AD

0

P0

3

/AD

3

P0

4

/AD

4

P0

5

/AD

5

P0

6

/AD

6

P0

7

/AD

7

P1

1

/AD

9

P1

2

/AD

10

P1

3

/AD

11

P1

4

/AD

12

P1

5

/AD

13

P1

6

/AD

14

P1

7

/AD

15

P6

2

/AN

2

P6

1

/AN

1

P6

0

/AN

0

P7

7

M38063M6-XXXFP

P7

6

P7

5

P7

4

P7

2

/S

CLK2

P7

1

/S

OUT2

P7

0

/S

IN2

P5

7

/DA

2

P5

0

P4

6

/S

CLK1

P4

5

/T

X

D

P4

4

/R

X

D

P4

3

/INT

1

P6

3

/AN

3

P6

4

/AN

4

P6

5

/AN

5

AV

SS

V

REF

V

CC

P8

0

P8

1

P8

2

P8

3

P8

4

P8

5

P8

6

P8

7

P4

2

/INT

0

CNV

SS

X

IN

X

OUT

V

SS

P2

7

/DB

7

P2

6

/DB

6

P2

5

/DB

5

P2

4

/DB

4

P2

3

/DB

3

P2

2

/DB

2

P2

1

/DB

1

P2

0

/DB

0

RESET

P7

3

/S

RDY2

P5

1

/INT

2

P5

5

/CNTR

1

P5

4

/CNTR

0

P5

3

/INT

4

P5

2

/INT

3

P5

6

/DA

1

P1

0

/AD

8

P0

1

/AD

1

P0

2

/AD

2

P4

7

/S

RDY1

P3

2

/ONW

P3

3

/RESET

OUT

P3

6

/WR

P3

7

/RD

P4

0

P4

1

P6

7

/AN

7

P6

6

/AN

6

HARDWARE

1-3

3806 GROUP USER’S MANUAL

PIN CONFIGURATION

PIN CONFIGURATION (TOP VIEW)

Fig. 2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP

Package type : 80P6S-A/80P6D-A

80-pin plastic-molded QFP

P3

6

/WR

P3

7

/RD

P0

0

/AD

0

P0

1

/AD

1

P0

2

/AD

2

P0

3

/AD

3

P0

4

/AD

4

P0

5

/AD

5

P0

6

/AD

6

P0

7

/AD

7

P1

0

/AD

8

P1

1

/AD

9

P1

2

/AD

10

P1

3

/AD

11

P1

4

/AD

12

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P1

5

/AD

13

6

P6

0

/AN

0

P7

7

P7

6

P7

5

P7

4

P7

3

/S

RDY2

P7

2

/S

CLK2

P7

1

/S

OUT2

P7

0

/S

IN2

P5

7

/DA

2

P5

6

/DA

1

P5

5

/CNTR

1

P5

4

/CNTR

0

P5

3

/INT

4

P5

2

/INT

3

P5

1

/INT

2

P5

0

1

4

3

2

5

7

8

9

10

11

12

13

14

15

16

17

18

19

20

P4

7

/S

RDY1

P4

6

/S

CLK1

P4

5

/T

X

D

68

80

79

78

77

76

75

74

73

72

71

69

67

66

65

70

P6

4

/AN

4

P6

3

/AN

3

P6

5

/AN

5

P6

6

/AN

6

AV

SS

V

REF

V

CC

P8

5

63

62

61

P8

7

P3

1

64

21

23

22

24

30

25

27

28

29

31

34

35

36

V

ss

P2

7

/DB

7

P2

6

/DB

6

33

32

26

P2

5

/DB

5

38

39

40

P2

4

/DB

4

P2

3

/DB

3

P2

2

/DB

2

37

P4

4

/R

X

D

P4

3

/INT

1

X

IN

P4

2

/INT

0

RESET

X

OUT

CNV

SS

P4

1

P3

0

P8

6

P8

4

P6

2

/AN

2

P6

1

/AN

1

M38063M6-XXXGP

M38063M6AXXXHP

P2

1

/DB

1

P2

0

/DB

0

P1

7

/AD

15

P1

6

/AD

14

P4

0

P3

2

/ONW

P3

3

/RESET

OUT

P3

4

/φ

P3

5

/SYNC

P6

7

/AN

7

P8

3

P8

2

P8

1

P8

0

HARDWARE

3806 GROUP USER’S MANUAL

1-4

FUNCTIONAL BLOCK

Fig. 3 Functional block diagram

FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)

FUNCTIONAL BLOCK

CNTR

1

CNTR

0

V

REF

AV

SS

INT

2

to

INT

4

RAM ROM

CPU

A

X

Y

S

PC

H

PC

L

PS

V

SS

32

RESET

27

V

CC

73 26

CNV

SS

P0(8)

49 50 51 52 53 54 55 56

P1(8)

41 43 45 47

42 44 46 48

P2(8)

33 35 37 3934 36 38 40

P3(8)

57 59 61 6358 60 62 64

P4(8)

20 22 24 28

21 23 25 29

P5(8)

12 14 16 1813 15 17 19

P7(8)

46810579

11

P8(8)

65 67 69 7166 68 70 72

P6(8)

76 78

2

77

13

74 75

X

IN

30

X

OUT

31

Serial I/O2

(8) D-A

(8)

D-A

(8)

Reset input

Clock generating circuit

Clock input Clock output

A-D

converter

converter 2 converter 1

Prescaler 12 (8)

Timer 1 (8)

Timer 2 (8)

I/O port P4 I/O port P0I/O port P1I/O port P2I/O port P3

I/O port P5

I/O port P7

I/O port P8 I/O port P6

(8)

79 80

Serial I/O1

(8)

INT

0

to

INT

1

Prescaler X (8) Timer X (8)

Prescaler Y (8) Timer Y (8)

CPU

Data bus

HARDWARE

1-5

3806 GROUP USER’S MANUAL

Function

• Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS.

(Extended operating temperature version : 4.0 V to 5.5 V)

(High-speed version : 2.7 V to 5.5 V)

• This pin controls the operation mode of the chip.

• Normally connected to VSS.

• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.

• Reference voltage input pin for A-D and D-A converters

• GND input pin for A-D and D-A converters

• Connect to VSS.

• Reset input pin for active “L”

• Input and output signals for the internal clock generating circuit.

• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the

oscillation frequency.

• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• The clock is used as the oscillating source of system clock.

• 8 bit CMOS I/O port

• I/O direction register allows each pin to be individually programmed as either input or output.

• At reset this port is set to input mode.

• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as

port P0

• CMOS compatible input level

• CMOS 3-state output structure

Pin

VCC

VSS

CNVSS

VREF

AVSS

______

RESET

XIN

XOUT

P00 – P07

P10 – P17

P20 – P27

P30 – P37

P40, P41

P42/INT0,

P43/INT1

P44/RXD,

P45/TXD,

P46/SCLK1,

_____

P47/SRDY1

P50

P51/INT2 –

P53/INT4

P54/CNTR0,

P55/CNTR1

P56/DA1,

P57/DA2

P60/AN0 –

P67/AN7

PIN DESCRIPTION

Table 1. Pin description (1)

PIN DESCRIPTION

Name

Power source

CNVSS

Analog reference

voltage

Analog power

source

Reset input

Clock input

Clock output

I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

I/O port P5

I/O port P6

Function except a port function

• External interrupt input pin

• Serial I/O1 I/O pins

• External interrupt input pin

• Timer X and Timer Y I/O pins

• D-A conversion output pins

• A-D conversion input pins

HARDWARE

3806 GROUP USER’S MANUAL

1-6

PIN DESCRIPTION

Function

• 8-bit I/O port with the same function as port P0

• CMOS compatible input level

• N-channel open-drain output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

Pin

P70/SIN2,

P71/SOUT2,

P72/SCLK2,

_____

P73/SRDY2

P74 – P77

P80 – P87

Table 2. Pin description (2)

Name

I/O port P7

I/O port P8

Function except a port function

• Serial I/O2 I/O pins

HARDWARE

1-7

3806 GROUP USER’S MANUAL

PART NUMBERING

Fig. 4 Part numbering

PART NUMBERING

M3806 3 M 6 - XXX FP

Product

Package type

FP : 80P6N-A package

GP : 80P6S-A package

FS : 80D0 package

ROM number

Omitted in some types.

ROM/PROM size

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

: 4096 bytes

: 8192 bytes

: 12288 bytes

: 16384 bytes

: 20480 bytes

: 24576 bytes

: 28672 bytes

: 32768 bytes

: 36864 bytes

: 40960 bytes

: 45056 bytes

: 49152 bytes

: 53248 bytes

: 57344 bytes

: 61440 bytes

The first 128 bytes and the last 2 bytes of ROM

are reserved areas ; they cannot be used.

Memory type

M

E : Mask ROM version

: EPROM or One Time PROM version

RAM size

0

1

2

3

4

5

6

7

: 192 bytes

: 256 bytes

: 384 bytes

: 512 bytes

: 640 bytes

: 768 bytes

: 896 bytes

: 1024 bytes

Normally, using hyphen

When electrical characteristic, or division of quality

identification code using alphanumeric character

– : standard

D : Extended operating temperature version

A : High-speed version

HARDWARE

3806 GROUP USER’S MANUAL

1-8

GROUP EXPANSION

Currently supported products are listed below.

RAM size (bytes)

384

384

512

1024

1024

Remarks

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

EPROM version

Mask ROM version

Mask ROM version

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Package

80P6N-A

80P6S-A

80P6N-A

80P6S-A

80P6N-A

80P6S-A

80D0

80P6N-A

80P6S-A

80P6N-A

80P6S-A

Table 3. List of supported products

Product name

M38062M3-XXXFP

M38062M3-XXXGP

M38062M4-XXXFP

M38062M4-XXXGP

M38063M6-XXXFP

M38063E6-XXXFP

M38063E6FP

M38063M6-XXXGP

M38063E6-XXXGP

M38063E6GP

M38063E6FS

M38067M8-XXXFP

M38067M8-XXXGP

M38067MC-XXXFP

M38067EC-XXXFP

M38067ECFP

M38067MC-XXXGP

M38067EC-XXXGP

M38067ECGP

As of September 1995

12288

(12158)

16384

(16254)

24576

(24446)

(P) ROM size (bytes)

ROM size for User in ( )

32768

(32638)

49152

(49022)

HARDWARE

1-9

3806 GROUP USER’S MANUAL

GROUP EXPANSION

GROUP EXPANSION

Mitsubishi plans to expand the 3806 group as follows:

(1) Support for mask ROM, One Time PROM, and EPROM

versions

ROM/PROM capacity ................................ 12 K to 48 K bytes

RAM capacity.............................................. 384 to 1024 bytes

(2) Packages

80P6N-A............................. 0.8 mm-pitch plastic molded QFP

80P6S-A........................... 0.65 mm-pitch plastic molded QFP

80D0................ 0.8 mm-pitch ceramic LCC (EPROM version)

Memory Expansion Plan

Fig. 5 Memory expansion plan

M38062M3

M38062M4

M38063M6/E6

M38067MC/EC

M38067M8

Mass product

Mass product

Mass product

Mass product

Mass product

48K

ROM size (bytes)

32K

28K

24K

20K

16K

12K

8K

4K

192 256 384 512 640 768 896 1024

RAM size (bytes)

HARDWARE

3806 GROUP USER’S MANUAL

1-10

GROUP EXPANSION

GROUP EXPANSION

(EXTENDED OPERATING TEMPERATURE VERSION)

Mitsubishi plans to expand the 3806 group (extended operating

temperature version) as follows:

(1) Support for mask ROM version

ROM/PROM capacity ................................ 12 K to 48 K bytes

RAM capacity.............................................. 384 to 1024 bytes

(2) Packages

80P6N-A............................. 0.8 mm-pitch plastic molded QFP

Memory Expansion Plan

Fig. 6 Memory expansion plan (Extended operating temperature version)

Currently supported products are listed below.

RAM size (bytes)

384

384

512

1024

1024

12288(12158)

16384(16254)

24576(24446)

32768(32638)

49152(49022)

Remarks

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

One Time PROM version

One Time PROM version (blank)

As of September 1995

Package

80P6N-A

Table 4. List of supported products (Extended operating temperature version)

Product name

M38062M3DXXXFP

M38062M4DXXXFP

M38063M6DXXXFP

M38067M8DXXXFP

M38067MCDXXXFP

M38067ECDXXXFP

M38067ECDFP

(P) ROM size (bytes)

ROM size for User in ( )

M38062M3D

M38062M4D

M38063M6D

M38067ECD

M38067MCD

M38067M8D

Mass product

Mass product

Mass product

Mass product

Mass product

48K

ROM size (bytes)

32K

28K

24K

20K

16K

12K

8K

4K

192 256 384 512 640 768 896 1024

RAM size (bytes)

New product

HARDWARE

1-11

3806 GROUP USER’S MANUAL

GROUP EXPANSION

GROUP EXPANSION

(HIGH-SPEED VERSION)

Mitsubishi plans to expand the 3806 group (high-speed version)

as follows:

(1) Support for mask ROM, One Time PROM, and EPROM

versions

ROM/PROM capacity ................................ 24 K to 48 K bytes

RAM capacity.............................................. 512 to 1024 bytes

(2) Packages

80P6N-A............................. 0.8 mm-pitch plastic molded QFP

80P6S-A........................... 0.65 mm-pitch plastic molded QFP

80P6D-A............................. 0.5 mm-pitch plastic molded QFP

80D0................ 0.8 mm-pitch ceramic LCC (EPROM version)

Memory Expansion Plan

Fig. 7 Memory expansion plan (High-speed version)

Currently supported products are listed below.

RAM size (bytes)

512

1024

1024

24576

(24446)

Remarks

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

EPROM version

As of September 1995

Package

80P6N-A

80P6S-A

80P6D-A

80P6N-A

80P6S-A

80P6N-A

80P6S-A

80D0

Table 5. List of supported products (High-speed version)

Product name

M38063M6AXXXFP

M38063M6AXXXGP

M38063M6AXXXHP

M38067M8AXXXFP

M38067M8AXXXGP

M38067MCAXXXFP

M38067ECAXXXFP

M38067ECAFP

M38067MCAXXXGP

M38067ECAXXXGP

M38067ECAGP

M38067ECAFS

(P) ROM size (bytes)

ROM size for User in ( )

32768

(32638)

49152

(49022)

M38063M6A

M38067MCA/ECA

M38067M8A

New product

New product

New product

48K

ROM size (bytes)

32K

28K

24K

20K

16K

12K

8K

4K

192 256 384 512 640 768 896 1024

RAM size (bytes)

HARDWARE

3806 GROUP USER’S MANUAL

1-12

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The 3806 group uses the standard 740 family instruction set. Re-

fer to the table of 740 family addressing modes and machine in-

structions or the SERIES 740 <Software> User’s Manual for de-

tails on the instruction set.

Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used.

The STP, WIT, MUL, and DIV instruction can be used.

The central processing unit (CPU) has the six registers.

Accumulator (A)

The accumulator is an 8-bit register. Data operations such as data

transfer, etc., are executed mainly through the accumulator.

Index register X (X), Index register Y (Y)

Both index register X and index register Y are 8-bit registers. In

the index addressing modes, the value of the OPERAND is added

to the contents of register X or register Y and specifies the real ad-

dress.

When the T flag in the processor status register is set to “1”, the

value contained in index register X becomes the address for the

second OPERAND.

Stack pointer (S)

The stack pointer is an 8-bit register used during subroutine calls

and interrupts. The stack is used to store the current address data

and processor status when branching to subroutines or interrupt

routines.

The lower eight bits of the stack address are determined by the

contents of the stack pointer. The upper eight bits of the stack ad-

dress are determined by the Stack Page Selection Bit. If the Stack

Page Selection Bit is “0”, then the RAM in the zero page is used

as the stack area. If the Stack Page Selection Bit is “1”, then RAM

in page 1 is used as the stack area.

The Stack Page Selection Bit is located in the SFR area in the

zero page. Note that the initial value of the Stack Page Selection

Bit varies with each microcomputer type. Also some microcom-

puter types have no Stack Page Selection Bit and the upper eight

bits of the stack address are fixed.

The operations of pushing register contents onto the stack and

popping them from the stack are shown in Fig. 9.

Program counter (PC)

The program counter is a 16-bit counter consisting of two 8-bit

registers PCH and PCL. It is used to indicate the address of the

next instruction to be executed.

Fig. 8 740 Family CPU register structure

FUNCTIONAL DESCRIPTION

X

Y

S

PCL

CNVTBDI Z

A

b0

b0

b7

b7

b15

b0b7

b0b7

b0b7

b0b7

Accumulator

Index Register X

Index Register Y

Stack Pointer

Program Counter

Processor Status Register (PS)

Carry Flag

Zero Flag

Interrupt Disable Flag

Decimal Mode Flag

Break Flag

Index X Mode Flag

Overflow Flag

Negative Flag

PCH

HARDWARE

1-13

3806 GROUP USER’S MANUAL

Fig. 9 Register push and pop at interrupt generation and subroutine call

Table 6. Push and pop instructions of accumulator or processor status register

Accumulator

Processor status register

Push instruction to stack

PHA

PHP

Pop instruction from stack

PLA

PLP

FUNCTIONAL DESCRIPTION

On-going Routine

Execute JSR

M(S) ← (PC

H

)

(S) ← (S – 1)

M(S) ← (PC

L

)

(S) ← (S – 1)

Subroutine

(S) ← (S + 1)

(PC

L

) ← M(S)

(S) ← (S + 1)

(PC

H

) ← M(S)

Execute RTS

(S) ← (S – 1)

M(S) ← (PS)

(S) ← (S – 1)

Interrupt

Service Routine

(S) ← (S + 1)

(PS) ← M(S)

(S) ← (S + 1)

(PC

L

) ← M(S)

Execute RTI

(S) ← (S + 1)

(PC

H

) ← M(S)

M(S) ← (PC

H

)

(S) ← (S – 1)

M(S) ← (PC

L

)

Interrupt Request

(Note 1)

Store Return Address

on Stack (Note 2)

Restore Return

Address Restore Contents of

Processor Status

Register

I Flag “0” to “1”

Fetch the Jump

Vector

Store Contents of

Processor Status

Register on Stack

Store Return Address

on Stack (Note 2)

Notes 1 : The condition to enable the interrupt → Interrupt enable bit is “1”

Interrupt disable flag is “0”

2 : When an interrupt occurs, the address of the next instruction to be executed is stored in

the stack area. When a subroutine is called, the address one before the next instruction

to be executed is stored in the stack area.

Restore Return

Address

HARDWARE

3806 GROUP USER’S MANUAL

1-14

Processor status register (PS)

The processor status register is an 8-bit register consisting of flags

which indicate the status of the processor after an arithmetic op-

eration. Branch operations can be performed by testing the Carry

(C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.

In decimal mode, the Z, V, N flags are not valid.

After reset, the Interrupt disable (I) flag is set to “1”, but all other

flags are undefined. Since the Index X mode (T) and Decimal

mode (D) flags directly affect arithmetic operations, they should be

initialized in the beginning of a program.

(1) Carry flag (C)

The C flag contains a carry or borrow generated by the arith-

metic logic unit (ALU) immediately after an arithmetic opera-

tion. It can also be changed by a shift or rotate instruction.

(2) Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic op-

eration or a data transfer is “0”, and cleared if the result is

anything other than “0”.

(3) Interrupt disable flag (I)

The I flag disables all interrupts except for the interrupt gener-

ated by the BRK instruction.

Interrupts are disabled when the I flag is “1”.

When an interrupt occurs, this flag is automatically set to “1”

to prevent other interrupts from interfering until the current in-

terrupt is serviced.

(4) Decimal mode flag (D)

The D flag determines whether additions and subtractions are

executed in binary or decimal. Binary arithmetic is executed

when this flag is “0”; decimal arithmetic is executed when it is

“1”. Decimal correction is automatic in decimal mode. Only

the ADC and SBC instructions can be used for decimal arith-

metic.

(5) Break flag (B)

The B flag is used to indicate that the current interrupt was

generated by the BRK instruction. The BRK flag in the pro-

cessor status register is always “0”. When the BRK instruc-

tion is used to generate an interrupt, the processor status

register is pushed onto the stack with the break flag set to “1”.

The saved processor status is the only place where the break

flag is ever set.

(6) Index X mode flag (T)

When the T flag is “0”, arithmetic operations are perfor med

between accumulator and memory, e.g. the results of an op-

eration between two memory locations is stored in the accu-

mulator. When the T flag is “1”, direct arithmetic operations

and direct data transfers are enabled between memory loca-

tions, i.e. between memory and memor y, memory and I/O,

and I/O and I/O. In this case, the result of an arithmetic op-

eration performed on data in memory location 1 and memory

location 2 is stored in memory location 1. The address of

memory location 1 is specified by index register X, and the

address of memory location 2 is specified by normal address-

ing modes.

(7) Overflow flag (V)

The V flag is used during the addition or subtraction of one

byte of signed data. It is set if the result exceeds + 127 to

–128. When the BIT instruction is executed, bit 6 of the

memory location operated on by the BIT instruction is stored

in the overflow flag.

(8) Negative flag (N)

The N flag is set if the result of an arithmetic operation or data

transfer is negative. When the BIT instruction is executed, bit

7 of the memory location operated on by the BIT instruction is

stored in the negative flag.

FUNCTIONAL DESCRIPTION

Table 7. Set and clear instructions of each bit of processor status register

Set instruction

Clear instruction

C flag

SEC

CLC

Z flag

—

—

I flag

SEI

CLI

D flag

SED

CLD

B flag

—

—

T flag

SET

CLT

V flag

—

CLV

N flag

—

—

HARDWARE

1-15

3806 GROUP USER’S MANUAL

CPU mode register

The CPU mode register is allocated at address 003B16.

The CPU mode register contains the stack page selection bit.

Fig. 10 Structure of CPU mode register

FUNCTIONAL DESCRIPTION

CPU mode register

(

CPUM : address

003B

16

)

b7 b0

Stack page selection bit

0 : 0 page

1 : 1 page

Not used (return “0” when read)

Processor mode bits

b1 b0

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Microprocessor mode

1 1 : Not available

HARDWARE

3806 GROUP USER’S MANUAL

1-16

Memory

Special function register (SFR) area

The Special Function Register area in the zero page contains con-

trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine

calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing and the rest is user area for storing programs.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

Zero page

The 256 bytes from addresses 000016 to 00FF16 are called the

zero page area. The internal RAM and the special function regis-

ters (SFR) are allocated to this area.

The zero page addressing mode can be used to specify memory

and register addresses in the zero page area. Access to this area

with only 2 bytes is possible in the zero page addressing mode.

Special page

The 256 bytes from addresses FF0016 to FFFF16 are called the

special page area. The special page addressing mode can be

used to specify memory addresses in the special page area. Ac-

cess to this area with only 2 bytes is possible in the special page

addressing mode.

Fig. 11 Memory map diagram

FUNCTIONAL DESCRIPTION

0100

16

0000

16

0040

16

0440

16

FF00

16

FFDC

16

FFFE

16

FFFF

16

192

256

384

512

640

768

896

1024 XXXX

16

00FF

16

013F

16

01BF

16

023F

16

02BF

16

033F

16

03BF

16

043F

16

4096

8192

12288

16384

20480

24576

28672

32768

36864

40960

45056

49152

53248

57344

61440

F000

16

E000

16

D000

16

C000

16

B000

16

A000

16

9000

16

8000

16

7000

16

6000

16

5000

16

4000

16

3000

16

2000

16

1000

16

F080

16

E080

16

D080

16

C080

16

B080

16

A080

16

9080

16

8080

16

7080

16

6080

16

5080

16

4080

16

3080

16

2080

16

1080

16

YYYY

16

ZZZZ

16

RAM

ROM

Reserved area

SFR area

Not used

Interrupt vector area

ROM area

Reserved ROM area

(128 bytes)

Zero page

Special page

RAM area

RAM capacity

(bytes) Address

XXXX

16

ROM capacity

(bytes) Address

YYYY

16

Reserved ROM area

Address

ZZZZ

16

HARDWARE

1-17

3806 GROUP USER’S MANUAL

Fig. 12 Memory map of special function register (SFR)

FUNCTIONAL DESCRIPTION

0020

16

0021

16

0022

16

0023

16

0024

16

0025

16

0026

16

0027

16

0028

16

0029

16

002A

16

002B

16

002C

16

002D

16

002E

16

002F

16

0030

16

0031

16

0032

16

0033

16

0034

16

0035

16

0036

16

0037

16

0038

16

0039

16

003A

16

003B

16

003C

16

003D

16

003E

16

003F

16

0000

16

0001

16

0002

16

0003

16

0004

16

0005

16

0006

16

0007

16

0008

16

0009

16

000A

16

000B

16

000C

16

000D

16

000E

16

000F

16

0010

16

0011

16

0012

16

0013

16

0014

16

0015

16

0016

16

0017

16

0018

16

0019

16

001A

16

001B

16

001C

16

001D

16

001E

16

001F

16

Serial I/O2 register (SIO2)

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Port P8 (P8)

Port P8 direction register (P8D)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Serial I/O2 control register (SIO2CON)

Interrupt control register 2(ICON2)

A-D conversion register (AD)

Prescaler Y (PREY)

Timer Y (TY)

AD/DA control register (ADCON)

D-A1 conversion register (DA1)

D-A2 conversion register (DA2)

Interrupt edge selection register

(INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1(IREQ1)

Interrupt request register 2(IREQ2)

Interrupt control register 1(ICON1)

Prescaler 12 (PRE12)

Timer 2 (T2)

Prescaler X (PREX)

Timer X (TX)

Timer 1 (T1)

Timer XY mode register (TM)

HARDWARE

3806 GROUP USER’S MANUAL

1-18

Pin

P00 – P07

P10 – P17

P20 – P27

P30 – P37

P40,P41

P42/INT0,

P43/INT1

P44/RXD,

P45/TXD,

P46/SCLK1,

_____

P47/SRDY1

P50

P51/INT2,

P52/INT3,

P53/INT4

P54/CNTR0,

P55/CNTR1

P56/DA1,

P57/DA2

P60/AN0 –

P67/AN7

P70/SIN2,

P71/SOUT2,

P72/SCLK2,

_____

P73/SRDY2

P74 – P77

P80 – P87

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Port P7

Port P8

Input/Output

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

I/O Format

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

N-channel open-drain output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

Non-Port Function

Address low-order byte

output

Address high-order

byte output

Data bus I/O

Control signal I/O

External interrupt input

Serial I/O1 function I/O

External interrupt input

Timer X and Timer Y

function I/O

D-A conversion output

A-D conversion input

Serial I/O2 function I/O

Ref.No.

(1)

(2)

(3)

(4)

(5)

(6)

(1)

(2)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(1)

Table 8. List of I/O port functions Related SFRs

CPU mode register

CPU mode register

CPU mode register

CPU mode register

Interrupt edge selection

register

Serial I/O1 control

register

UART control register

Interrupt edge selection

register

Timer XY mode register

AD/DA control register

Serial I/O2 control

register

Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-

tion I/O ports, refer to the applicable sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

I/O Ports

Direction registers

The 3806 group has 72 programmable I/O pins arranged in nine

I/O por ts (por ts P0 to P8). The I/O ports have direction registers

which determine the input/output direction of each individual pin.

Each bit in a direction register corresponds to one pin, each pin

can be set to be input port or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

If data is read from a pin which is set to output, the value of the

port output latch is read, not the value of the pin itself. Pins set to

input are floating. If a pin set to input is written to, only the port

output latch is written to and the pin remains floating.

FUNCTIONAL DESCRIPTION

HARDWARE

1-19

3806 GROUP USER’S MANUAL

Fig. 13 Port block diagram (single-chip mode) (1)

FUNCTIONAL DESCRIPTION

(1) Ports P0, P1, P2, P3, P4

0

, P4

1

, P5

0

, P8

Direction register

Data bus Port latch

(2) Ports P4

2

, P4

3

, P5

1

, P5

2

, P5

3

Direction register

Data bus Port latch

Interrupt input

(3) Port P4

4

Direction register

Data bus Port latch

Serial I/O1 input

Serial I/O1 enable bit

Receive enable bit

(4) Port P4

5

Direction register

Data bus Port latch

Serial I/O1output

Serial I/O1 enable bit

Transmit enable bit

P4

5

/T

X

D P-channel output disable bit

(5) Port P4

6

Direction register

Data bus Port latch

Serial I/O1 clock output

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Serial I/O1 enable bit

Serial I/O1

synchronous clock selection bit

Serial I/O1

external

clock input

(6) Port P4

7

Direction register

Data bus Port latch

Serial I/O1 ready output

Serial I/O1 enable bit

S

RDY1

output enable bit

Serial I/O1 mode selection bit

(7) Ports P5

4

, P5

5

Direction register

Data bus Port latch

(8) Ports P5

6

, P5

7

Direction register

Data bus Port latch

D-A conversion output

Pulse output mode

Timer output Counter input

Interrupt input DA

1

output enable bit (P5

6

)

DA

2

output enable bit (P5

7

)

HARDWARE

3806 GROUP USER’S MANUAL

1-20

Fig. 14 Port block diagram (single-chip mode) (2)

FUNCTIONAL DESCRIPTION

(14) Ports P7

4

– Port P7

7

Direction register

Data bus Port latch

(13) Port P7

3

Direction register

Data bus Port latch

Serial I/O2 ready output

S

RDY2

output enable bit

Serial I/O2

synchronous clock selection bit

Direction register

Data bus Port latch

Serial I/O2 clock output

Serial I/O2 port selection bit

(12) Port P7

2

(9) Port P6

Direction register

Data bus Port latch

A-D conversion input

Analog input pin selection bit

(10) Port P7

0

Direction register

Data bus Port latch

Serial I/O2 input

(11) Port P7

1

Direction register

Data bus Port latch

Serial I/O2 output

Serial I/O2 port selection bit

Serial I/O2

transmit completion signal

Serial I/O2

external

clock input

HARDWARE

1-21

3806 GROUP USER’S MANUAL

Interrupts

Interrupts occur by sixteen sources: seven external, eight internal,

and one software.

Interrupt control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the corre-

sponding interrupt request and enable bits are “1” and the inter-

rupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

(interrupt disable) flag disables all interrupts except the BRK in-

struction interrupt.

Interrupt operation

When an interrupt is received, the contents of the program counter

and processor status register are automatically stored into the

stack. The interrupt disable flag is set to inhibit other interrupts

from interfering.The corresponding interrupt request bit is cleared

and the interrupt jump destination address is read from the vector

table into the program counter.

Notes on use

When the active edge of an external interrupt (INT0 to INT4,

CNTR0, or CNTR1) is changed, the corresponding interrupt re-

quest bit may also be set. Therefore, please take following se-

quence;

(1) Disable the external interrupt which is selected.

(2) Change the active edge selection.

(3) Clear the interrupt request bit which is selected to “0”.

(4) Enable the exter nal interr upt which is selected.

FUNCTIONAL DESCRIPTION

Interrupt Source

Reset (Note 2)

INT0

INT1

Serial I/O1

reception

Serial I/O1

transmission

Timer X

Timer Y

Timer 1

Timer 2

CNTR0

CNTR1

Serial I/O2

INT2

INT3

INT4

A-D converter

BRK instruction

Low

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

High

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

Table 9. Interrupt vector addresses and priority

Priority

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

Interrupt Request

Generating Conditions

At reset

At detection of either rising or

falling edge of INT0 input

At detection of either rising or

falling edge of INT1 input

At completion of serial I/O1

data reception

At completion of serial I/O1

transfer shift or when

transmission buffer is empty

At timer X underflow

At timer Y underflow

At timer 1 underflow

At timer 2 underflow

At detection of either rising or

falling edge of CNTR0 input

At detection of either rising or

falling edge of CNTR1 input

At completion of serial I/O2

data transfer

At detection of either rising or

falling edge of INT2 input

At detection of either rising or

falling edge of INT3 input

At detection of either rising or

falling edge of INT4 input

At completion of A-D conversion

At BRK instruction execution

Remarks

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O1 is selected

Valid when serial I/O1 is selected

STP release timer underflow

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O2 is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Non-maskable software interrupt

Note 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Vector Addresses (Note 1)

HARDWARE

3806 GROUP USER’S MANUAL

1-22

Fig. 15 Interrupt control

Fig. 16 Structure of interrupt-related registers

FUNCTIONAL DESCRIPTION

Interrupt disable flag (I)

Interrupt request

Interrupt request bit

Interrupt enable bit

BRK instruction

Reset

b7 b0

b7 b0

b7 b0

b7 b0

b7 b0

Interrupt edge selection register

INT0 active edge selection bit

INT

1

active edge selection bit

Not used (returns “0” when read)

INT

2

active edge selection bit

INT

3

active edge selection bit

INT

4

active edge selection bit

Not used (returns “0” when read)

(INTEDGE : address 003A16)

Interrupt request register 1

INT0 interrupt request bit

INT

1

interrupt request bit

Serial I/O1 receive interrupt request bit

Serial I/O1 transmit interrupt request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 1 interrupt request bit

Timer 2 interrupt request bit

Interrupt control register 1

INT

0

interrupt enable bit

INT

1

interrupt enable bit

Serial I/O1 receive interrupt enable bit

Serial I/O1 transmit interrupt enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

0 : No interrupt request issued

1 : Interrupt request issued

(IREQ1 : address 003C16)

(ICON1 : address 003E16)

Interrupt request register 2

CNTR0 interrupt request bit

CNTR

1

interrupt request bit

Serial I/O2 interrupt request bit

INT

2

interrupt request bit

INT

3

interrupt request bit

INT

4

interrupt request bit

AD converter interrupt request bit

Not used (returns “0” when read)

(IREQ2 : address 003D16)

Interrupt control register 2

CNTR

0

interrupt enable bit

CNTR

1

interrupt enable bit

Serial I/O2 interrupt enable bit

INT

2

interrupt enable bit

INT

3

interrupt enable bit

INT

4

interrupt enable bit

AD converter interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

0 : Interrupts disabled

1 : Interrupts enabled

(ICON2 : address 003F16)

0 : Falling edge active

1 : Rising edge active

HARDWARE

1-23

3806 GROUP USER’S MANUAL

Timers

The 3806 group has four timers: timer X, timer Y, timer 1, and

timer 2.

All timers are count down. When the timer reaches “0016”, an un-

derflow occurs at the next count pulse and the corresponding

timer latch is reloaded into the timer and the count is continued.

When a timer underflows, the interrupt request bit corresponding

to that timer is set to “1”.

The division ratio of each timer or prescaler is given by 1/(n + 1),

where n is the value in the corresponding timer or prescaler latch.

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency di-

vided by 16. The output of prescaler 12 is counted by timer 1 and

timer 2, and a timer underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each be selected in one of four operating

modes by setting the timer XY mode register.

Timer Mode

The timer counts f(XIN)/16 in timer mode.

Pulse Output Mode

Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of

the timer reach “0016”, the signal output from the CNTR0 (or

CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge

switch bit is “0”, output begins at “ H”.

If it is “1”, output starts at “L”. When using a timer in this mode, set

the corresponding port P54 ( or port P55) direction register to out-

put mode.

Event Counter Mode

Operation in event counter mode is the same as in timer mode,

except the timer counts signals input through the CNTR0 or

CNTR1 pin.

Pulse Width Measurement Mode

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer

counts at the oscillation frequency divided by 16 while the CNTR0

(or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge

switch bit is “1”, the count continues during the time that the

CNTR0 (or CNTR1) pin is at “L”.

In all of these modes, the count can be stopped by setting the

timer X (timer Y) count stop bit to “1”. Every time a timer

underflows, the corresponding interrupt request bit is set.

Fig. 17 Structure of timer XY register

FUNCTIONAL DESCRIPTION

Timer X count stop bit

0: Count start

1: Count stop

Timer XY mode register

(TM : address 0023

16)

Timer Y operating mode bit

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width measurement mode

CNTR

1

active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

b7

CNTR

0

active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

b0

Timer X operating mode bit

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width measurement mode

b1b0

b5b4

Timer Y count stop bit

0: Count start

1: Count stop

HARDWARE

3806 GROUP USER’S MANUAL

1-24

Fig. 18 Block diagram of timer X, timer Y, timer 1, and timer 2

FUNCTIONAL DESCRIPTION

Timer X latch (8)

Timer X (8)

Prescaler X latch (8)

Prescaler X (8)

Oscillator Divider

f(X

IN

)1/16

CNTR

0

active

edge switch bit

P5

4

/CNTR

0

pin

Port P5

4

direction register

“0”

“1”

Event

counter

mode Timer X count stop bit

CNTR

0

active

edge switch

bit

Port P5

4

latch

Pulse output

mode

Pulse width

measurement

mode

Timer mode

Pulse output

mode

“1”

“0”

Timer X latch write pulse

Pulse output mode

To timer X interrupt

request bit

To CNTR

0

interrupt

request bit

Data bus

Timer Y latch (8)

Timer Y (8)

Prescaler Y latch (8)

Prescaler Y (8)

CNTR

1

active

edge switch bit

P5

5

/CNTR

1

pin

Port P5

5

direction register

“0”

“1”

Event

counter

mode Timer Y count stop bit

CNTR

1

active

edge switch

bit

Port P5

5

latch

Pulse output

mode

Pulse width

measurement

mode

Timer mode

Pulse output

mode

“1”

“0”

Timer Y latch write pulse

Pulse output mode

To timer Y interrupt

request bit

To CNTR

1

interrupt

request bit

Data bus

Q

QR

Toggle flip- flop T

Q

QR

Toggle flip- flop T

Timer 2 latch (8) Timer 1 latch (8)

Prescaler

12 latch (8)

Prescaler 12 (8) Timer 2 (8)Timer 1 (8)

Data bus

To timer 2 interrupt

request bit

To timer 1 interrupt

request bit

HARDWARE

1-25

3806 GROUP USER’S MANUAL

Serial I/O

Serial I/O1

Serial I/O1 can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer is also provided for

baud rate generation.

Clock synchronous serial I/O mode

Clock synchronous serial I/O1 mode can be selected by setting

the mode selection bit of the serial I/O1 control register to “1”.

For clock synchronous serial I/O1, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

star ted by a write signal to the TB/RB (address 001816).

Fig. 19 Block diagram of clock synchronous serial I/O1

Fig. 20 Operation of clock synchronous serial I/O1 function

FUNCTIONAL DESCRIPTION

1/4

X

IN

1/4

F/F

P4

6

/S

CLK1

Serial I/O1 status register

Serial I/O1 control register

P4

7

/S

RDY1

P4

4

/R

X

D

P4

5

/T

X

D

f(X

IN

)

Receive buffer

Address 0018

16

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O1 synchronous

clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C

16

BRG count source selection bit

Clock control circuit

Falling-edge detector

Transmit buffer

Data bus Address 0018

16

Shift clock Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 0019

16

Data bus

Address 001A

16

Transmit shift register

D

7

D

7

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

D

1

D

2

D

3

D

4

D

5

D

6

RBF = 1

TSC = 1

TBE = 0 TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

Write pulse to receive/transmit

buffer (address 0018

16

)

Overrun error (OE)

detection

Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the

transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1

control register.

2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is

output continuously from the TxD pin.

3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal

S

RDY1

HARDWARE

3806 GROUP USER’S MANUAL

1-26

Asynchronous serial I/O (UART) mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O mode selection bit of the serial I/O control

register to “0”.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer, and receive data is read from the re-

ceive buffer.

The transmit buffer can also hold the next data to be transmitted,

and the receive buffer can hold a character while the next charac-

ter is being received.

Fig. 21 Block diagram of UART serial I/O

FUNCTIONAL DESCRIPTION

f(X

IN

)

1/4

OE

PE FE

1/16

1/16

Data bus

Receive buffer

Address 0018

16

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C

16

ST/SP/PA generator

Transmit buffer

Data bus

Transmit shift register

Address

0018

16

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Address

0019

16

STdetector

SP detector UART control register

Address 001B

16

Character length selection bit

Address 001A

16

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O1 synchronous clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O1 control register

P4

6

/S

CLK1

Serial I/O1 status register

P4

4

/R

X

D

P4

5

/T

X

D

HARDWARE

1-27

3806 GROUP USER’S MANUAL

Fig. 22 Operation of UART serial I/O function

Serial I/O1 control register (SIO1CON) 001A16

The serial I/O control register consists of eight control bits for the

serial I/O function.

UART control register (UARTCON) 001B16

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer. One bit in this register (bit 4) is

always valid and sets the output structure of the P45/TXD pin.

Serial I/O1 status register (SIO1STS) 001916

The read-only serial I/O1 status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer, and

the receive buffer full flag is set. A write to the serial I/O status reg-

ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-

spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of

the Serial I/O Control Register) also clears all the status flags, in-

cluding the error flags.

All bits of the serial I/O1 status register are initialized to “0” at re-

set, but if the transmit enable bit (bit 4) of the serial I/O control reg-

ister has been set to “1”, the transmit shift completion flag (bit 2)

and the transmit buffer empty flag (bit 0) become “1”.

Transmit buffer/Receive buffer register (TB/

RB) 001816

The transmit buffer and the receive buffer are located at the same

address. The transmit buffer is write-only and the receive buffer is

read-only. If a character bit length is 7 bits, the MSB of data stored

in the receive buffer is “0”.

Baud rate generator (BRG) 001C16

The baud rate generator determines the baud rate for serial trans-

fer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate genera-

tor.

FUNCTIONAL DESCRIPTION

TSC=0

TBE=1

RBF=0

TBE=0 TBE=0

RBF=1 RBF=1

ST

D

0

D

1

SP D

0

D

1

ST SP

TBE=1 TSC=1

ST

D

0

D

1

SP D

0

D

1

ST SP

Transmit or receive clock

Transmit buffer write

signal

Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).

2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt

source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes "1".

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

✽

✽

Serial output T

X

D

Serial input R

X

D

Receive buffer read

signal

HARDWARE

3806 GROUP USER’S MANUAL

1-28

b7

b7

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

Transmit shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

Overrun error flag (OE)

0: No error

1: Overrun error

Parity error flag (PE)

0: No error

1: Parity error

Framing error flag (FE)

0: No error

1: Framing error

Summing error flag (SE)

0: (OE) U (PE) U (FE)=0

1: (OE) U (PE) U (FE)=1

Not used (returns "1" when read)

Serial I/O1 status register

(SIO1STS : address 0019

16

) Serial I/O1 control register

(SIO1CON : address 001A

16

)

b0 b0

BRG count source selection bit (CSS)

0: f(X

IN

)

1: f(X

IN

)/4

Serial I/O1 synchronous clock selection bit (SCS)

0: BRG output divided by 4 when clock synchronous

serial I/O is selected, BRG output divided by 16

when UART is selected.

1: External clock input when clock synchronous serial

I/O is selected, external clock input divided by 16

when UART is selected.

S

RDY1

output enable bit (SRDY)

0: P4

7

pin operates as ordinaly I/O pin

1: P4

7

pin operates as S

RDY1

output pin

Transmit interrupt source selection bit (TIC)

0: Interrupt when transmit buffer has emptied

1: Interrupt when transmit shift operation is completed

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Serial I/O1 mode selection bit (SIOM)

0: Clock asynchronous (UART) serial I/O

1: Clock synchronous serial I/O

Serial I/O enable bit (SIOE)

0: Serial I/O disabled

(pins P4

4

to P4

7

operate as ordinary I/O pins)

1: Serial I/O enabled

(pins P4

4

to P4

7

operate as serial I/O pins)

b7

UART control register

(UARTCON : address 001B

16

)

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

P4

5

/T

X

D P-channel output disable bit (POFF)

0: CMOS output (in output mode)

1: N-channel open drain output (in output mode)

Not used (return "1" when read)

b0

Fig. 23 Structure of serial I/O control registers

FUNCTIONAL DESCRIPTION

HARDWARE

1-29

3806 GROUP USER’S MANUAL

Serial I/O2

The serial I/O2 function can be used only for clock synchronous

serial I/O.

For clock synchronous serial I/O the transmitter and the receiver

must use the same clock. If the internal clock is used, transfer is

started by a write signal to the serial I/O2 register.

Serial I/O2 control register (SIO2CON) 001D16

The serial I/O2 control register contains seven bits which control

various serial I/O functions.

Fig. 24 Structure of serial I/O2 control register

Fig. 25 Block diagram of serial I/O2 function

FUNCTIONAL DESCRIPTION

X

IN

"1"

"0"

"0"

"1"

"0"

"1"

SRDY2

SCLK2

"0"

"1"

1/8

1/16

1/32

1/64

1/128

1/256

Data bus

Serial I/O2

interrupt request

Serial I/O2 port selection bit

Serial I/O counter 2 (3)

Serial I/O shift register 2 (8)

Synchronization circuit

Serial I/O2 port selection bit

Serial I/O2 synchronous

clock selection bit

SRDY2 output enable bit

External clock

Internal synchronous

clock selection bits

Divider

P73 latch

P7

3

/S

RDY2

P7

2

/S

CLK2

P7

1

/S

OUT2

P7

0

/S

IN2

P72 latch

P71 latch

Serial I/O2 control register

(SIO2CON : address 001D

16

)

b7

Internal synchronous clock selection bits

0 0 0: f(X

IN

)/8

0 0 1: f(X

IN

)/16

0 1 0: f(X

IN

)/32

0 1 1: f(X

IN

)/64

1 1 0: f(X

IN

)/128

1 1 1: f(X

IN

)/256

Serial I/O2 port selection bit

0: I/O port

1: S

OUT2

,S

CLK2

signal output

S

RDY2

output enable bit

0: I/O port

1: S

RDY2

signal output

Transfer direction selection bit

0: LSB first

1: MSB first

Serial I/O2 synchronous clock selection bit

0: External clock

1: Internal clock

Not used (returns “0” when read)

b0

b2 b1 b0

HARDWARE

3806 GROUP USER’S MANUAL

1-30

Fig. 26 Timing of serial I/O2 function

FUNCTIONAL DESCRIPTION

D7D0D1D2D3D4D5D6

Transfer clock (Note 1)

Serial I/O2 output SOUT2

Serial I/O2 input SIN2

Receive enable signal SRDY2

Serial I/O2 register

write signal

(Note 2)

Serial I/O2 interrupt request bit set

1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial

I/O2 control register.

2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.

Notes

HARDWARE

1-31

3806 GROUP USER’S MANUAL

A-D Converter

The functional blocks of the A-D conver ter are described below.

[A-D conversion register]

The A-D conversion register is a read-only register that stores the

result of an A-D conversion. When reading this register during an

A-D conversion, the previous conversion result is read.

[AD/DA control register]

The AD/DA control register controls the A-D conversion process.

Bits 0 to 2 select a specific analog input pin. Bit 3 signals the

completion of an A-D conversion. The value of this bit remains at

“0” during an A-D conversion, and changes to “1” when an A-D

conversion ends. Writing “0” to this bit starts the A-D conversion.

Bits 6 and 7 are used to control the output of the D-A converter.

[Comparison voltage generator]

The comparison voltage generator divides the voltage between

AVSS and VREF into 256, and outputs the divided voltages.

[Channel selector]

The channel selector selects one of the ports P60/AN0 to P67/AN7,

and inputs the voltage to the comparator.

Fig. 27 Structure of AD/DA control register

Fig. 28 Block diagram of A-D conver ter

FUNCTIONAL DESCRIPTION

[Comparator and Control circuit]

The comparator and control circuit compares an analog input volt-

age with the comparison voltage, then stores the result in the A-D

conversion register. When an A-D conversion is complete, the

control circuit sets the AD conversion completion bit and the AD

interrupt request bit to “1”.

Note that the comparator is constructed linked to a capacitor, so

set f(XIN) to 500 kHz or more during an A-D conversion.

AD/DA control register

(ADCON : address 0034

16

)

Analog input pin selection bits

0 0 0: P6

0

/AN

0

0 0 1: P6

1

/AN

1

0 1 0: P6

2

/AN

2

0 1 1: P6

3

/AN

3

1 0 0: P6

4

/AN

4

1 0 1: P6

5

/AN

5

1 1 0: P6

6

/AN

6

1 1 1: P6

7

/AN

7

AD conversion completion bit

0: Conversion in progress

1: Conversion completed

Not used (return "0" When read)

DA

1

output enable bit

0: DA

1

output disabled

1: DA

1

output enabled

DA

2

output enable bit

0: DA

2

output disabled

1: DA

2

output enabled

b7 b0

b2 b1 b0

Channel selector

A-D control circuit

A-D conversion register

Resistor ladder

VREF AVSS

Comparator

A-D interrupt request

b7 b0

3

8

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

Data bus

(Address 003516)

AD/DA control register

(Address 003416)

HARDWARE

3806 GROUP USER’S MANUAL

1-32

D-A Converter

The 3806 group has two internal D-A converters (DA1 and DA2)

with 8-bit resolutions.

The D-A converter is performed by setting the value in the D-A

conversion register. The result of D-A converter is output from the

DA1 or DA2 pin by setting the DA output enable bit to “1”.

When using the D-A conver ter, the corresponding por t direction

register bit (DA1/P56 or DA2/P57) should be set to “0” (input sta-

tus).

The output analog voltage V is determined by the value n (base

10) in the D-A conversion register as follows:

V = VREF ✕ n/256 (n = 0 to 255)

Where VREF is the reference voltage.

At reset, the D-A conversion registers are cleared to “0016”, the DA

output enable bits are cleared to “0”, and the P56/DA1 and P57/

DA2 pins are set to input (high impedance).

The D-A output is not buffered, so connect an external buffer when

driving a low-impedance load.

Set VCC to 4.0 V or more when using the D-A converter.

Fig. 29 Block diagram of D-A converter

Fig. 30 Equivalent connection circuit of D-A converter

FUNCTIONAL DESCRIPTION

P56/DA1

D-A1 conversion register (8)

R-2R resistor ladder DA1 output enable bit

P57/DA2

D-A2 conversion register (8)

R-2R resistor ladder DA2 output enable bit

Data bus

AV

SS

V

REF

"0"

"1"

MSB

"0" "1"

R

2R

R

2R

R

2R

R

2R

R

2R

R

2R

R

2R 2R

LSB

2R

P5

6

/DA1

D-A1

conversion

register

DA

1

output enable bit

HARDWARE

1-33

3806 GROUP USER’S MANUAL

Reset Circuit

______

To reset the microcomputer, the RESET pin should be held at an

______

“L” level for 2 µs or more. Then the RESET pin is returned to an

“H” level (Note 1), reset is released. Internal operation does not

begin until after 8 to 13 XIN clock cycles are completed. After the

reset is completed, the program starts from the address contained

in address FFFD16 (high-order byte) and address FFFC16 (low-or-

der byte).

Make sure that the reset input voltage is less than 0.8 V for VCC of

4.0 V (Note 2).

Note 1. The power source voltage should be between the follow-

ing voltage.

• Between 3.0 V and 5.5 V for standard version

• Between 4.0 V and 5.5 V for extended operating tem-

perature version

• Between 2.7 V and 5.5 V for high-speed version

Note 2. Reset input voltage is less than the following voltage.

• 0.6 V for VCC = 3.0 V

• 0.8 V for VCC = 4.0 V

• 0.54 V for VCC = 2.7 V

Fig. 32 Internal status of microcomputer after reset

Fig. 31 Example of reset circuit

FUNCTIONAL DESCRIPTION

4.0V

0.8V

0V

0V

V

CC

RESET

Power source

voltage

Reset input

voltage

V

SS

M51953AL 4

5

1

30.1 µ F

3806 group

Note.

✕

: Undefined

✽ : The initial values of CM

1

are determined by the level at the

CNV

SS

pin.

The contents of all other registers and RAM are undefined

after a reset, so they must be initialized by software.

Register contents

(0001

16

) • • •

Timer 2

Port P0 direction register

Port P1 direction register

Port P2 direction register

Port P3 direction register

Port P4 direction register

Port P5 direction register

Port P6 direction register

Port P7 direction register

Port P8 direction register

Timer XY mode register

Serial I/O1 status register

Serial I/O1 control register

UART control register

Serial I/O2 control register

Timer 1

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

(0003

16

) • • •

(0005

16

) • • •

(0007

16

) • • •

(0009

16

) • • •

(000B

16

) • • •

(000D

16

) • • •

(000F

16

) • • •

(0011

16

) • • •

(0019

16

) • • •

(001A

16

) • • •

(001B

16

) • • •

(001D

16

) • • •

(0020

16

) • • •

(0021

16

) • • •

(0022

16

) • • •

(0023

16

) • • •

(0024

16

) • • •

(0025

16

) • • •

(0026

16

) • • •

(0027

16

) • • •

(0034

16

) • • •

(0036

16

) • • •

(0037

16

) • • •

(003A

16

) • • •

(003B

16

) • • •

(003C

16

) • • •

(003D

16

) • • •

(003E

16

) • • •

Address

Prescaler 12

Prescaler X

Timer X

Prescaler Y

Timer Y

AD/DA control register

D-A1 conversion register

D-A2 conversion register

Interrupt edge selection register

CPU mode register

Interrupt request register 1

Interrupt request register 2

Interrupt control register 1

Interrupt control register 2

Processor status register

Program counter

00

16

00

16

00

16

00

16

000000 0

✽

00

16

00

16

00

16

000010 00

FF

16

FF

16

FF

16

FF

16

00

16

FF

16

01

16

FF

16

00

16

00

16

00

16

00

16

00

16

111000 00

100000 00

00

16

00

16

00

16

Contents of address FFFC

16

✕✕✕✕✕

1

✕✕

(PS)

(PC

H

)

(PC

L

)

Contents of address FFFD

16

00

16

00

16

00

16

(003F

16

) • • •

HARDWARE

3806 GROUP USER’S MANUAL

1-34

Fig. 33 Timing of reset

FUNCTIONAL DESCRIPTION

RESET

Data

φ

Address

SYNC

X

IN

: 8 to 13 clock cycles

X

IN

???? ?FFFC FFFD AD

H

, AD

L

??? ??AD

L

AD

H

1: f(X

IN

) and f(φ) are in the relationship: f(X

IN

)=2

•

f(φ).

2: A question mark (?) indicates an undefined status that depends on the previous status.

Reset address from the vector table

Notes

?

?

RESET

OUT

(internal reset)

HARDWARE

1-35

3806 GROUP USER’S MANUAL

Clock Generating Circuit

An oscillation circuit can be formed by connecting a resonator be-

tween XIN and XOUT. To supply a clock signal externally, input it to

the XIN pin and make the XOUT pin open.

Oscillation control

Stop Mode

If the STP instruction is executed, the internal clock φ stops at an

“H”. Timer 1 is set to “0116” and prescaler 12 is set to “FF16”.

Oscillator restarts when an external interrupt is received, but the

internal clock φ remains at an “H” until timer 1 underflow.

This allows time for the clock circuit oscillation to stabilize.

If oscillator is restarted by a reset, no wait time is generated, so

______

keep the RESET pin at an “L” level until oscillation has stabilized.

Wait Mode

If the WIT instruction is executed, the internal clock φ stops at an

“H” level, but the oscillator itself does not stop. The internal clock

restarts if a reset occurs or when an interrupt is received.

Since the oscillator does not stop, normal operation can be started

immediately after the clock is restarted.

To ensure that interr upts will be received to release the STP or

WIT state, interrupt enable bits must be set to “1” before the STP

or WIT instruction is executed.

When the STP status is released, prescaler 12 and timer 1 will

start counting and reset will not be released until timer 1

underflows, so set the timer 1 interrupt enable bit to “0” before the

STP instruction is executed.

Fig. 36 Block diagram of clock generating circuit

Fig. 35 External clock input circuit

Fig. 34 Ceramic resonator circuit

FUNCTIONAL DESCRIPTION

1/8

X

OUT

X

IN

R

SQ

STP instruction WIT

instruction R

SQ

R

S

QReset

STP instruction

Timer 1

ONW

control

Prescaler 12

1/2

φ output

Internal clock φ

Rd

Rf

ONW pin

Single-chip mode

Reset

Interrupt request

Interrupt disable

flag (I)

FF

16

01

16

Reset or STP instruction

C

OUT

X

IN

X

OUT

C

IN

X

IN

X

OUT

Open

External oscillation

circuit Vss

Vcc

HARDWARE

3806 GROUP USER’S MANUAL

1-36

Processor Modes

Single-chip mode, memory expansion mode, and microprocessor

mode can be selected by changing the contents of the processor

mode bits CM0 and CM1 (bits 0 and 1 of address 003B16). In

memory expansion mode and microprocessor mode, memory can

be expanded externally through ports P0 to P3. In these modes,

ports P0 to P3 lose their I/O port functions and become bus pins.

Fig. 37 Memory maps in various processor modes

Fig. 38 Structure of CPU mode register

Single-Chip Mode

Select this mode by resetting the microcomputer with CNVSS con-

nected to VSS.

Memory Expansion Mode

Select this mode by setting the processor mode bits to “01” in soft-

ware with CNVSS connected to VSS. This mode enables external

memory expansion while maintaining the validity of the internal

ROM. Internal ROM will take precedence over external memory if

addresses conflict.

Microprocessor Mode

Select this mode by resetting the microcomputer with CNVSS con-

nected to VCC, or by setting the processor mode bits to “10” in

software with CNVSS connected to VSS. In microprocessor mode,

the internal ROM is no longer valid and external memory must be

used.

FUNCTIONAL DESCRIPTION

Port Name

Port P0

Port P1

Port P2

Port P3

Function

Outputs low-order byte of address.

Outputs high-order byte of address.

Operates as I/O pins for data D7 to D0

(including instruction codes).

P30 and P31 function only as output pins

(except that the port latch cannot be read).

_____

P32 is the ONW input pin.

_________

P33 is the RESETOUT output pin. (Note)

P34 is the φ output pin.

P35 is the SYNC output pin.

___

P36 is the WR output pin, and P37 is the

___

RD output pin.

Note: If CNVSS is connected to V SS, the microcomputer goes to

single-chip mode after a reset, so this pin cannot be used

_________

as the RESETOUT output pin.

Table 10. Functions of ports in memory expansion mode and

microprocessor mode

0000

16

0040

16

0008

16

0000

16

YYYY

16

FFFF

16

0008

16

0040

16

FFFF

16

Internal RAM

reserved area

Internal ROM

Memory expansion mode

The shaded areas are external memory areas.

SFR area

:

YYYY

16

is the start address of internal ROM.

SFR area

Microprocessor mode

✽

Internal RAM

reserved area

0440

16

✽

0440

16

b0

CPU mode register

(CPUM : address 003B

16

)

Processor mode bits

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Microprocessor mode

1 1 : Not available

Stack page selection bit

0 : 0 page

1 : 1 page

b7

Not used (return “0” when read)

b1 b0

HARDWARE

1-37

3806 GROUP USER’S MANUAL

Bus control with memory expansion

_____

The 3806 group has a built-in ONW function to facilitate access to

external memory and I/O devices in memory expansion mode or

microprocessor mode.

_____

If an “L” level signal is input to the ONW pin when the CPU is in a

read or write state, the corresponding read or write cycle is ex-

___

tended by one cycle of φ. During this extended period, the RD or

___

WR signal remains at “L”. This extension period is valid only for

writing to and reading from addresses 000016 to 000716 and

044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in

memory expansion mode, and only read and write cycles are ex-

tended.

_____

Fig. 39 ONW function timing

FUNCTIONAL DESCRIPTION

φ

Read cycle Write cycle

Dummy cycle Write cycle Read cycle Dummy cycle

AD

15

to AD

0

Period during which ONW input signal is received

During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW

signal has no affect on operations.

The bus cycles is not extended for an address in the area 0008

16

to 043F

16,

regardless of whether the ONW signal

is received.

✽ :

✽✽

ONW

WR

RD

✽

HARDWARE

3806 GROUP USER’S MANUAL

1-38

NOTES ON PROGRAMMING

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. Af-

ter a reset, initialize flags which affect program execution.

In par ticular, it is essential to initialize the index X mode (T) and

the decimal mode (D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After wr iting to an interrupt re-

quest register, execute at least one instr uction before executing a

BBC or BBS instruction.

Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to

“1”, then execute an ADC or SBC instruction. Only the ADC and

SBC instructions yield proper decimal results. After executing an

ADC or SBC instruction, execute at least one instruction before

executing a SEC, CLC, or CLD instruction.

In decimal mode, the values of the negative (N), overflow (V), and

zero (Z) flags are invalid.

The carry flag can be used to indicate whether a carry or borrow

has occurred. Initialize the carry flag before each calculation.

Clear the carry flag before an ADC and set the flag before an

SBC.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n + 1).

Multiplication and Division Instructions

The index X mode (T) and the decimal mode (D) flags do not af-

fect the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Ports

The contents of the port direction registers cannot be read.

The following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction regis-

ter as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a

direction register

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex-

_____

ternal clock and it is to output the SRDY1 signal, set the transmit

_____

enable bit, the receive enable bit, and the SRDY1 output enable bit

to “1”.

Serial I/O1 continues to output the final bit from the T XD pin after

transmission is completed. The SOUT2 pin from serial I/O2 goes to

high impedance after transmission is completed.

A-D Converter

The comparator uses internal capacitors whose charge will be lost

if the clock frequency is too low.

Make sure that f(XIN) is at least 500 kHz during an A-D conver-

____

sion. (If the ONW pin has been set to “L”, the A-D conversion will

take twice as long to match the longer bus cycle, and so f(XIN)

must be at least 1 MHz.)

Do not execute the STP or WIT instr uction during an A-D conver-

sion.

D-A Converter

The accuracy of the D-A converter becomes poor rapidly under

the VCC = 4.0 V or less condition.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The frequency of the internal clock φ is half of the XIN frequency.

_____

When the ONW function is used in modes other than single-chip

mode, the frequency of the internal clock φ may be one fourth the

XIN frequency.

Memory Expansion Mode and Microproces-

sor Mode

Execute the LDM or STA instr uction for writing to port P3 (address

000616) in memory expansion mode and microprocessor mode.

Set areas which can be read out and write to port P3 (address

000616) in a memory, using the read-modify-write instruction

(SEB, CLB).

HARDWARE

1-39

3806 GROUP USER’S MANUAL

DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc-

tion:

1. Mask ROM Order Confirmation Form

2. Mark Specification Form

3. Data to be written to ROM, in EPROM form (three identical

copies)

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built-

in EPROM version can be read or programmed with a general-

purpose PROM programmer using a special programming

adapter. Set the address of PROM programmer in the user ROM

area.

The PROM of the blank One Time PROM version is not tested or

screened in the assembly process and following processes. To en-

sure proper operation after programming, the procedure shown in

Figure 40 is recommended to verify programming.

Fig. 40 Programming and testing of One Time PROM version

Table 11. Programming adapter

Package

80P6N-A

80P6S-A

80D0

Name of Programming Adapter

PCA4738F-80A

PCA4738G-80A

PCA4738L-80A

Programming with PROM

programmer

Screening (Caution)

(150°C for 40 hours)

Verification with

PROM programmer

Functional check in

target device

The screening temperature is far higher

than the storage temperature. Never

expose to 150 °C exceeding 100 hours.

Caution :

HARDWARE

3806 GROUP USER’S MANUAL

1-40

Priority

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

FUNCTIONAL DESCRIPTION SUPPLEMENT

Interrupt

3806 group permits interrupts on the basis of 16

sources. It is vector interrupts with a fixed priority

system. Accordingly, when two or more interrupt

requests occur during the same sampling, the higher-

priority interrupt is accepted first. This priority is

determined by hardware, but variety of priority

processing can be performed by software, using an

interrupt enable bit and an interrupt disable flag.

For interrupt sources, vector addresses and inter-

rupt priority, refer to “Table 12.”

Interrupt sources

Reset (Note)

INT0 interrupt

INT1 interrupt

Serial I/O1 receive interrupt

Serial I/O1 transmit interrupt

Timer X interrupt

Timer Y interrupt

Timer 1 interrupt

Timer 2 interrupt

CNTR0 interrupt

CNTR1 interrupt

Serial I/O2 interrupt

INT2 interrupt

INT3 interrupt

INT4 interrupt

A-D conversion interrupt

BRK instruction interrupt

Vector addresses

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

Table 12. Interrupt sources, vector addresses and interrupt priority

Remarks

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O1 is selected

Valid when serial I/O1 is selected

STP release timer underflow

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O2 is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Non-maskable software interrupt

High-order Low-order

Note: Reset functions in the same way as an interrupt with the highest priority.

FUNCTIONAL DESCRIPTION SUPPLEMENT

HARDWARE

3806 GROUP USER’S MANUAL 1-41

FUNCTIONAL DESCRIPTION SUPPLEMENT

Timing After Interrupt

The interrupt processing routine begins with the

machine cycle following the completion of the in-

struction that is currently in execution.

Figure 41 shows a timing chart after an interrupt

occurs, and Figure 42 shows the time up to execu-

tion of the interrupt processing routine.

Fig. 41 Timing chart after an interrupt occurs

Fig. 42 Time up to execution of the interrupt processing routine

Generation of interrupt request

Main routine Interrupt processing routine

7 to 23 cycles

(At performing 8.0 MHz, 1.75

µs to 5.75 µs)

2 cycles 5 cycles

Start of interrupt processing

0 to 16 cycles

Waiting time for

post-processing

of pipeline

Stack push and

Vector fetch

✻

: at execution of DIV instruction (16 cycles)

✻

: CPU operation code fetch cycle

: Vector address of each interrupt

: Jump destination address of each interrupt

: “00

16

” or “01

16

”

SYNC

B

L

, B

H

A

L

, A

H

SPS

Data bus Not used PC

H

PC

L

PS A

L

A

H

Address bus

S

,

SPS S-2

,

SPSS-1, SPS

PC B

L

B

H

A

L

, A

H

SYNC

RD

WR

HARDWARE

3806 GROUP USER’S MANUAL

1-42

FUNCTIONAL DESCRIPTION SUPPLEMENT

A-D Converter

A-D conversion is started by setting AD conversion

completion bit to “0.” During A-D conversion, inter-

nal operations are performed as follows.

1. After the start of A-D conversion, A-D conversion

register goes to “0016.”

2. The highest-order bit of A-D conversion register

is set to “1,” and the comparison voltage Vref is

input to the comparator. Then, Vref is compared

with analog input voltage VIN.

3. As a result of comparison, when Vref < VIN, the

highest-order bit of A-D conversion register be-

comes “1.” When Vref > VIN, the highest-order

bit becomes “0.”

By repeating the above operations up to the lowest-

order bit of the A-D conversion register, an analog

value converts into a digital value.

A-D conversion completes at 50 clock cycles (12.5

µs at f(XIN) = 8.0 MHz) after it is started, and the

result of the conversion is stored into the A-D con-

version register.

Concurrently with the completion of A-D conversion,

A-D conversion interrupt request occurs, so that the

AD conversion interrupt request bit is set to “1.”

Relative formula for a reference voltage VREF of A-D converter and Vref

When n = 0 Vref = 0

When n = 1 to 255 Vref = ✕ (n – 0.5)

n : the value of A-D converter (decimal numeral)

VREF

256

✽1: A result of the first comparison

✽3: A result of the third comparison

✽5: A result of the fifth comparison

✽7: A result of the seventh comparison

✽2: A result of the second comparison

✽4: A result of the fourth comparison

✽6: A result of the sixth comparison

✽8: A result of the eighth comparison

Table 13. Change of A-D conversion register during A-D conversion

At start of conversion

First comparison

Second comparison

Third comparison

After completion of eighth

comparison

100000

1000000

10000000

00000000 0

VREF

VREF

2512

–

512

VREF

4

VREF VREF

±–

2

28

4

VREF VREF VREF VREF

±–

±512

A result of A-D conversion

~

~

✽1

✽1✽2

✽✽ ✽✽✽✽✽✽

12345678

Change of A-D conversion register Value of comparison voltage (Vref)

~

~

HARDWARE

3806 GROUP USER’S MANUAL 1-43

FUNCTIONAL DESCRIPTION SUPPLEMENT

Figures 43 shows A-D conversion equivalent cir-

cuit, and Figure 44 shows A-D conversion timing

chart.

Fig. 43 A-D conversion equivalent circuit

Fig. 44 A-D conversion timing chart

Write signal for AD/DA control register

AD conversion completion bit

Sampling clock

50 cycles

V

SS

V

CC

AV

SS

V

CC

AN

0

AN

1

AN

2

AN

3

AN

4

AN

5

AN

6

AN

7

V

REF

AV

SS

AD/DA control register

Build-in

D-A converter

V

ref

Reference

clock

A-D conversion register

A-D conversion interrupt request

Chopper amplifier

Sampling

clock

V

IN

C

b1b2 b0

about 2 k

HARDWARE

3806 GROUP USER’S MANUAL

1-44

MEMORANDUM

FUNCTIONAL DESCRIPTION SUPPLEMENT

CHAPTER 2

APPLICATION

2.1 I/O port

2.2 Timer

2.3 Serial I/O

2.4 A-D converter

2.5 Processor mode

2.6 Reset

APPLICATION

2.1 I/O port

2-2 3806 GROUP USER’S MANUAL

2.1 I/O port

2.1.1 Memory map of I/O port

Fig. 2.1.1 Memory map of I/O port related registers

0009

16

0000

16

0001

16

0002

16

0003

16

0004

16

0005

16

0006

16

0007

16

0008

16

000A

16

000B

16

000C

16

000D

16

000E

16

000F

16

0010

16

0011

16

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Port P8 (P8)

Port P8 direction register (P8D)

APPLICATION

2.1 I/O port

2-3

3806 GROUP USER’S MANUAL

2.1.2 Related registers

Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

Port Pi

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

4

5

6

7

Name

Port Pi0

Port Pi1

Port Pi2

Port Pi3

Port Pi4

Port Pi5

Port Pi6

Port Pi7

In output mode

Write

Read

●

Port latch

In input mode

Write : Port latch

Read : Value of pins

●

?

Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]

?

?

?

?

?

?

?

Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

Port Pi direction register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

Name

Port Pi

direction register

0

0

0

0

0

0

0

0

Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

[Address : 01

16

, 03

16

, 05

16

, 07

16

, 09

16

, 0B

16

, 0D

16

, 0F

16

, 11

16

]

0 : Port Pi

0

input mode

1 : Port Pi

0

output mode

0 : Port Pi

1

input mode

1 : Port Pi

1

output mode

0 : Port Pi

2

input mode

1 : Port Pi

2

output mode

0 : Port Pi

3

input mode

1 : Port Pi

3

output mode

0 : Port Pi

4

input mode

1 : Port Pi

4

output mode

0 : Port Pi

5

input mode

1 : Port Pi

5

output mode

0 : Port Pi

6

input mode

1 : Port Pi

6

output mode

0 : Port Pi

7

input mode

1 : Port Pi

7

output mode

✕

✕

✕

✕

✕

✕

✕

✕

APPLICATION

2.1 I/O port

2-4 3806 GROUP USER’S MANUAL

P0, P1, P2, P3, P4, P5, P6, P7, P8

VREF

AVSS

XOUT

2.1.3 Handling of unused pins

Table 2.1.1 Handling of unused pins (in single-chip mode)

Name of Pins/Ports

•

Set to the input mode and connect to VCC or VSS through a

resistor of 1 k to 10 k .

• Set to the output mode and open at “L” or “H.”

Connect to VSS(GND) or open.

Connect to VSS(GND).

Open (only when using external clock).

Handling

Name of Pins/Ports Handling

Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode)

Open

•

Set to the input mode and connect to VCC or VSS through a

resistor of 1 k to 10 k .

• Set to the output mode and open at “L” or “H.”

Connect to VSS(GND) or open.

Connect to VCC through a resistor of 1 k to 10 k .

Open

Open

Open

Connect to VSS(GND).

Open (only when using external clock).

P30, P31

P4, P5, P6, P7, P8

VREF

____

ONW

_________

RESETOUT

SYNC

AVSS

XOUT

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-5

2.2 Timer

2.2.1 Memory map of timer

Fig. 2.2.1 Memory map of timer related registers

003C

16

0020

16

0021

16

0022

16

0023

16

0024

16

0025

16

0026

16

0027

16

003D

16

003E

16

003F

16

Prescaler 12 (PRE12)

Timer 1 (T1)

Timer 2 (T2)

Timer XY mode register (TM)

Prescaler X (PREX)

Timer X (TX)

Prescaler Y (PREY)

Timer Y (TY)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Interrupt control register 2 (ICON2)

~

~~

~

APPLICATION

2.2 Timer

2-6 3806 GROUP USER’S MANUAL

2.2.2 Related registers

Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y

Fig. 2.2.3 Structure of Timer 1

Prescaler 12, Prescaler X, Prescaler Y

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

1

1

1

1

1

1

1

1

Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)

[Address : 2016, 2416, 2616]

The count value of each prescaler is set.

The value set in this register is written to both the prescaler and

the prescaler latch at the same time.

When the prescaler is read out, the value (count value) of the

prescaler is read out.

●

●

●

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

1

0

0

0

0

0

0

0

Timer 1 (T1) [Address : 21

16

]

The count value of the Timer 1 is set.

The value set in this register is written to both the Timer 1 and

the Timer 1 latch at the same time.

When the Timer 1 is read out, the value (count value) of the

Timer 1 is read out.

●

●

●

Timer 1

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-7

Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y

Timer 2, Timer X, Timer Y

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

4

5

6

7

1

1

1

1

1

1

1

1

Timer 2 (T2), Timer X (TX), Timer Y (TY)

[Address : 2216, 2516, 2716]

The count value of each timer is set.

The value set in this register is written to both the Timer and the

Timer latch at the same time.

When the Timer is read out, the value (count value) of the Timer

is read out.

●

●

●

APPLICATION

2.2 Timer

2-8 3806 GROUP USER’S MANUAL

Operating mode of

Timer X/Timer Y

Timer mode

Pulse output mode

Event counter mode

Pulse width measurement mode

Table. 2.2.1 Function of CNTR0/CNTR1 edge switch bit

Fig. 2.2.5 Structure of Timer XY mode register

Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

(No effect on timer count)

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

(No effect on timer count)

• Start of pulse output : From “H” level

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

• Start of pulse output : From “L” level

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

• Timer X/Timer Y : Count of rising edge

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

• Timer X/Timer Y : Count of falling edge

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

• Timer X/Timer Y : Measurement of “H” level width

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

• Timer X/Timer Y : Measurement of “L” level width

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

Function

Timer XY mode register

b7 b6 b5 b4 b3 b2 b1 b0

B

At reset

RW

0

1

2

3

4

5

6

7

0

0

0

0

0

0

0

0

Timer XY mode register (TM)

Name

Timer X operating mode

CNTR

0

active edge switch

bit

Timer Y operating mode

CNTR

1

active edge switch

bit

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

It depends on the operating mode

of the Timer X (refer to Table 2.2.1).

It depends on the operating mode

of the Timer Y (refer to Table 2.2.1).

b5 b4

Timer X count stop bit

[Address : 23

16

]

b1 b0

Timer Y count stop bit

0 : Count start

1 : Count stop

0 : Count start

1 : Count stop

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-9

Fig. 2.2.7 Structure of Interrupt request register 2

Fig. 2.2.6 Structure of Interrupt request register 1

Interrupt request register 1

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

Interrupt request reigster 1 (IREQ1) [Address : 3C16]

Name

✻“0” is set by software, but not “1.”

Timer Y interrupt request

bit

4

5

6

7

0

0

0

0

Timer X interrupt request

bit

Timer 1 interrupt request bit 0 : No interrupt request

1 : Interrupt request

Timer 2 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

✻

✻

✻

✻

✻

✻

✻

✻

0

0

0

0

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

INT0 interrupt request bit

INT1 interrupt request bit

Serial I/O1 receive interrupt

request bit

Serial I/O1 transmit interrupt

request bit

0

1

2

3

Interrupt request register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

0

0

0

0

Interrupt request reigster 2 (IREQ2) [Address : 3D

16

]

Name

CNTR

0

interrupt request bit

CNTR

1

interrupt request bit

Serial I/O2 interrupt request

bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

INT

2

interrupt request bit

✻

✻

✻

✻

5

6

7

0

0

0 : No interrupt request

1 : Interrupt request

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “0.”

AD conversion interrupt

request bit

INT

4

interrupt request bit

0 : No interrupt request

1 : Interrupt request

✻

✻

✻“0” is set by software, but not “1.”

4 0

0 : No interrupt request

1 : Interrupt request

INT

3

interrupt request bit ✻

0

✕

APPLICATION

2.2 Timer

2-10 3806 GROUP USER’S MANUAL

Fig. 2.2.8 Structure of Interrupt control register 1

Fig. 2.2.9 Structure of Interrupt control register 2

Timer Y interrupt enable bit

Interrupt control register 1

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

0

0

0

0

Interrupt control register 1 (ICON1) [Address : 3E16]

Name

INT0 interrupt enable bit

INT1 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

4

5

6

7

0

0

0

0

Timer X interrupt enable bit

Timer 1 interrupt enable bit 0 : Interrupt disabled

1 : Interrupt enabled

Timer 2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Serial I/O1 transmit interrupt

enable bit

Serial I/O1 receive interrupt

enable bit

Interrupt control register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

0

0

0

0

Interrupt control reigster 2 (ICON2) [Address : 3F

16

]

Name

CNTR

0

interrupt enable bit

CNTR

1

interrupt enable bit

Serial I/O2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

INT

2

interrupt enable bit

5

6

7

0

0

0 : Interrupt disabled

1 : Interrupt enabled

Fix this bit to “0.”

AD conversion interrupt

enable bit

INT

4

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

4 0

0 : Interrupt disabled

1 : Interrupt enabled

INT

3

interrupt enable bit

0

0

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-11

2.2.3 Timer application examples

(1) Basic functions and uses

[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)

The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt

request occurs after a certain period.

[Use] • Generation of an output signal timing

• Generation of a waiting time

[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)

The value of a timer latch is automatically written to a corresponding timer every time a timer

underflows, and each cyclic timer interrupt request occurs.

[Use] • Generation of cyclic interrupts

• Clock function (measurement of 250m second) → Application example 1

• Control of a main routine cycle

[Function 3] Output of Rectangular waveform (Timer X, Timer Y)

The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode).

[Use] • A piezoelectric buzzer output → Application example 2

• Generation of the remote-control carrier waveforms

[Function 4] Count of External pulse (Timer X, Timer Y)

External pulses input to the CNTR pin are selected as a timer count source (Event counter

mode).

[Use] • Measurement of frequency → Application example 3

• Division of external pulses.

• Generation of interrupts in a cycle based on an external pulse.

(count of a reel pulse)

[Function 5] Measurement of External pulse width (Timer X, Timer Y)

The “H” or “L” level width of external pulses input to CNTR pin is measured (Pulse width

measurement mode).

[Use] • Measurement of external pulse frequency (Measurement of pulse width of FG pulse✽ gener-

ated by motor) → Application example 4

• Measurement of external pulse duty (when the frequency is fixed)

✽FG pulse : Pulse used for detecting the motor speed to control the motor speed.

APPLICATION

2.2 Timer

2-12 3806 GROUP USER’S MANUAL

(2) Timer application example 1 : Clock function (measurement of 250 ms)

Outline : The input clock is divided by a timer so that the clock counts up every 250 ms.

Specifications : • The clock f(XIN) = 4.19 MHz (222 Hz) is divided by a timer.

• The clock is counted at intervals of 250 ms by the Timer X interrupt.

Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figure 2.2.11 shows a

setting of related registers, and Figure 2.2.12 shows a control procedure.

Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function]

Timer X interrupt request bit

1/16 0 or 11/2561/256

f(X

IN

) =

4.19 MHz

Fixed Prescaler X Timer X

250 ms

0 : No interrupt request

1 : Interrupt request

1/4

The clock is divided by 4 by software.

1 second

APPLICATION

2.2 Timer

2-13

3806 GROUP USER’S MANUAL

Fig. 2.2.11 Setting of related registers [Clock function]

255

PREX

Prescaler X (Address : 24

16

)

255

TX

Timer X (Address : 25

16

)

Set “division ratio – 1”

Timer X interrupt enable bit : Interrupt enabled

ICON1

Interrupt control register 1 (Address : 3E

16

)

Timer X interrupt request bit

(becomes “1” every 250 ms)

IREQ1

Interrupt request register 1 (Address : 3C

16

)

0

Timer X operating mode bits : Timer mode

TM

Timer XY mode register (Address : 23

16

)

00

1

Timer X count stop bit : Count stop

Set to “0” at starting count.

1

b7 b0

b7 b0

b7 b0

b7 b0

b7 b0

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-14

Control procedure :

Figure 2.2.12 shows a control procedure.

Fig. 2.2.12 Control procedure [Clock function]

RESET

Initialization

SEI

TM

ICON1

PREX

TX

TM

CLI

.... .... .... ....

(Address : 23

16

)

(Address : 3E

16

), bit4

(Address : 24

16

)

(Address : 25

16

)

(Address : 23

16

), bit3

XXXX1X00

2

1

256 – 1

256 – 1

0

All interrupts : Disabled

Timer X : Timer mode

Timer X interrupt : Enabled

Set “division ratio – 1” to the Prescaler X

and Timer X.

Timer X count : Operating

Interrupts : Enabled

●

●

●

●

●

●

●

X : This bit is not used in this application.

Set it to “0” or “1.” It’s value can be disregarded.

Timer X interrupt processing routine

CLT (Note 2)

CLD (Note 3)

Push register to stack

RTI

Y

N

Clock stop?

Clock count up (1/4 second-year)

Pop registers

Check if the clock has already been set.

Count up the clock.

Pop registers which is pushed to stack

Main processing

PREX

TX

IREQ1

....

(Address : 24

16

)

(Address : 25

16

)

(Address : 3C

16

), bit4

256 – 1

256 – 1

0

[Processing for completion of setting clock]

(Note 1)Note 1: This processing is performed only

at completing to set the clock.

When restarting the clock from zero

second after completing to set the

clock, reset timers.

●

~

~

●

●

●

●

Note 2: When using the Index X mode flag (T).

Note 3: When using the Decimal mode flag (D).

Push the register used in the interrupt

processing routine into the stack.

APPLICATION

2.2 Timer

2-15

3806 GROUP USER’S MANUAL

(3) Timer application example 2 : Piezoelectric buzzer output

Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer

output.

Specifications : • The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about

2 kHz (2048 Hz) is output from the P54/CNTR0 pin.

• The level of the P54/CNTR0 pin fixes to “H” while a piezoelectric buzzer output is

stopped.

Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the

timer and setting of the division ratio.

Fig. 2.2.13 Example of a peripheral circuit

Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]

244 µs 244 µs

3806 group

PiPiPi....

P54/CNTR0

Set a division ratio so that the underflow output cycle of the Timer X becomes this value.

The “H” level is output while a piezoelectric buzzer output is stopped.

CNTR0 output

1/16 1/2

f(X

IN

) = 4.19 MHz

Fixed Timer X Fixed

1/64

CNTR

0

1

Prescaler X

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-16

Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]

Control procedure :

Figure 2.2.16 shows a control procedure.

Fig. 2.2.16 Control procedure [Piezoelectric buzzer output]

0

63

TX

Timer X (Address : 25

16

)

Set “division ratio – 1”

010

CNTR

0

active edge switch bit : Output from the “H” level

Timer X count stop bit : Count stop

Set to “0” at starting to count.

Timer X operating mode bits : Pulse output mode

TM

Timer XY mode register (Address : 23

16

)

b7 b0

1

b7 b0

PREX

Prescaler X (Address : 24

16

)

b7 b0

Initialization

P5

P5D

ICON1

TM

TX

PREX

.... .... ....

0

XXXX1001

2

(Address : 0A

16

), bit4

(Address : 0B

16

)

(Address : 3E

16

), bit4

(Address : 23

16

)

(Address : 25

16

)

(Address : 24

16

)

A piezoelectric buzzer

is requested?

RESET

Y

N

Main processing

TM (Address : 23

16

), bit3 0

Timer X interrupts : Disabled

The CNTR

0

output is stopped at this point (stop

outputting a piezoelectric buzzer).

Set “division ratio – 1” to the Prescaler X and

Timer X.

During stopping outputting a piezoelectric buzzer During outputting a piezoelectric buzzer

Output unit

●

●

●

TM (Address : 23

16

), bit3 1

TX (Address : 25

16

) 64 –1

X : This bit is not used in this application.

Set it to “0” or “1.” It’s value can be disregarded.

●

●

The piezoelectric buzzer request occured in the

main processing is processed in the output unit.

1

XXX1XXXX

2

64 – 1

1 – 1

APPLICATION

2.2 Timer

2-17

3806 GROUP USER’S MANUAL

(4) Timer application example 3 : Measurement of frequency

Outline : The following two values are compared for judging if the frequency is within a certain range.

• A value counted a pulse which is input to P55/CNTR1 pin by a timer.

• A referance value

Specifications : • The pulse is input to the P55/CNTR1 pin and counted by the Timer Y.

• A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval

: 244 µs ✕ 8). When the count value is 28 to 40, it is regarded the input pulse

as a valid.

• Because the timer is a down-counter, the count value is compared with 227 to 215✽ .

227 to 215 = 255 (initialized value of counter) – 28 to 40 (the number of valid

value).

Figure 2.2.17 shows a method for judging if input pulse exists, and Figure 2.2.18 shows a setting of

related registers.

Fig 2.2.17 A method for judging if input pulse exists

Input pulse

71.4 µs or more

(14 kHz or less) 71.4 µs

(14 kHz) 50 µs

(20 kHz) 50 µs or less

(20 kHz or more)

Invalid Valid Invalid

2 ms

71.4 µs = 28 counts 2 ms

50 µs = 40 counts

• • • • • • • • • • • •

✽

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-18

Fig. 2.2.18 Setting of related registers [Measurement of frequency]

0

PREY

Prescaler Y (Address : 26

16

)

Set “division ratio – 1”

255

TY

Timer Y (Address : 27

16

)

Set “255” to this register immediately before

counting pulse.

(After a certain time, this value is decreased by

the number of input pulses)

1

Timer Y interrupt enable bit : Interrupt disabled

ICON1

Interrupt control register 1 (Address : 3E

16

)

0

Judgment of Timer Y interrupt request bit

(When this bit is set to “1” at reading out

the count value of the Timer Y (address : 27

16

),

256 pulses or more are input (at setting 255 to

the Timer Y).)

IREQ1

Interrupt request register 1 (Address : 3C

16

)

1

CNTR

1

active edge switch bit : Count at falling edge

Timer Y count stop bit : Count stop

Set to “0” at starting to count.

Timer Y operating mode bit : Event counter mode.

TM

Timer XY mode register (Address : 23

16

)

b7 b0

01

Prescaler 12 (Address : 20

16

)

b7 b0

63

PRE12

7

T1

Timer 1 (Address : 21

16

)

b7 b0

b7 b0

b7 b0

b7 b0

0

Timer 1 interrupt enable bit : Interrupt enabled

b7 b0

1

APPLICATION

2.2 Timer

2-19

3806 GROUP USER’S MANUAL

Control procedure :

Figure 2.2.19 shows a control procedure.

Fig. 2.2.19 Control procedure [Measurement of frequency]

Initialization

SEI

TM

PRE12

T1

PREY

TY

ICON1

TM

CLI

.... ....

....

(Address : 23

16

)

(Address : 20

16

)

(Address : 21

16

)

(Address : 26

16

)

(Address : 27

16

)

(Address : 3E

16

), bit6

(Address : 23

16

), bit7

1110XXXX

2

64–1

8–1

1–1

256–1

1

~

~

(A) TY (Address : 27

16

)

TY

IREQ1 (Address : 27

16

)

(Address : 3C

16

), bit5 256 – 1

0

1

0

Fpulse 0 Fpulse 1

Processing for a result of judgment

RTI

IREQ1 (Address : 3C

16

), bit5?

214 (A) 228?

< <

Compare the count value read with the

reference value.

Store the comparison result in flag Fpulse.

Out of range

In range

●

●

●

●

●

●

●

●

●

●

●

All interrupts : Disabled

Timer Y : Event counter mode

(Count at falling edge of pulse input from CNTR

1

pin)

Set the division ratio so that the Timer 1 interrupt

occurs every 2 ms.

Timer 1 interrupt : Enabled

Timer Y count : Start

Interrupts : Enabled

●

●

●

CLT (Note 1)

CLD (Note 2)

Push register to stack

Note 1: When using the Index X mode flag (T).

Note 2: When using the Decimal mode flag (D).

Push the register used in the interrupt

processing routine into the stack

Pop registers Pop registers which is pushed to stack.

●

0

Read the count value.

Store the count value in the accumulator (A).

Initialize the count value.

Set the Timer Y interrupt request bit to “0.”

When the count value is 256 or more, the

processing is performed as out of range.

RESET

●

X

:

This bit is not used in this application.

Set it to

“0”

or

“1.”

It’s value can be disregarded.

Timer 1 interrupt processing routine

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-20

(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor

Outline : The “H” level width of a pulse input to the P54/CNTR0 pin is counted by Timer X. An

underflow is detected by Timer X interrupt and an end of the input pulse “H” level is

detected by CNTR0 interrupt.

Specifications : • The “H” level width of FG pulse input to the P54/CNTR0 pin is counted by Timer

X.

(Example : When the clock frequency is 4.19 MHz, the count source would be 3.8

µs that is obtained by dividing the clock frequency by 16. Measure-

ment can be made up to 250 ms in the range of FFFF16 to 000016.)

Figure 2.2.20 shows a connection of the timer and a setting of the division ratio, and Figure 2.2.21

shows a setting of related registers.

Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width]

Timer X interrupt request bit

1/16 0 or 1

1/2561/256

f(XIN) = 4.19 MHz

Fixed Prescaler X Timer X

250 ms

0 : No interrupt request

1 : Interrupt request

APPLICATION

2.2 Timer

2-21

3806 GROUP USER’S MANUAL

Fig. 2.2.21 Setting of related registers [Measurement of pulse width]

01

CNTR

0

active edge switch bit : Count “H” level width

Timer X operating mode bits : Pulse width

measurement mode

Timer X count stop bit : Count stop

Set to “0” at starting to count.

TM

Timer XY mode register (Address : 23

16

)

b7 b0

11

255

PREX

Prescaler X (Address : 24

16

)

Set “division ratio – 1”

255

TX

Timer X (Address : 25

16

)

1

Timer X interrupt enable bit : Interrupt enabled

ICON1

Interrupt control register 1 (Address : 3E

16

)

b7 b0

b7 b0

b7 b0

1

CNTR

0

interrupt enable bit : Interrupt enabled

ICON2

Interrupt control register 2 (Address : 3F

16

)

0

CNTR

0

interrupt request bit

(This bit is set to “1” at completion of inputting

“H” level signal.)

IREQ2

Interrupt request register 2 (Address : 3D

16

)

b7 b0

b7 b0

Timer X interrupt request bit

(This bit is set to “1” at underflow of Timer X.)

IREQ1

Interrupt request register (Address : 3C

16

)

0

b7 b0

3806 GROUP USER’S MANUAL

APPLICATION

2.2 Timer

2-22

Fig. 2.2.22 Control procedure [Measurement of pulse width]

Figure 2.2.22 shows a control procedure.

~

~

RESET

Initialization

CNTR

0

interrupt processing routine

CLT (Note 1)

CLD (Note 2)

Push register to stack

RTI

Pop registers

Timer X interrupt processing routine

Processing for error

RTI

Error occurs

●

Set the division ratio so that the Timer X interrupt

occurs every 250 ms.

●

●

●

●

●

●

●

●

Set the division ratio so that the Timer X

interrupt occurs every 250 ms.

●

●

SEI

TM

PREX

TX

ICON1

IREQ1

ICON2

IREQ2

TM

CLI

....

....

....

(Address : 23

16

)

(Address : 24

16

)

(Address : 25

16

)

(Address : 3E

16

), bit4

(Address : 3C

16

), bit4

(Address : 3F

16

), bit0

(Address : 3D

16

), bit0

(Address : 23

16

), bit3

●

X: This bit is not used in this application.

Set it to

“0”

or

“1.”

It’s value can be disregarded.

(A)

Result of pulse width measurement

low–order 8-bit

(A)

Result of pulse width measurement

high–order 8-bit

PREX (Address : 24

16

)

TX (Address : 25

16

)

PREX

Inversion of (A)

TX

256–1

Inversion of (A)

256 – 1

Push the register used in the interrupt

processing routine into the stack.

Pop registers which is pushed to stack .

Note 1: When using the Index X mode flag (T).

Note 2: When using the Decimal mode flag (D).

CNTR

0

interrupt : Enabled

Timer X count : Start

Interrupts : Enabled

All interrupts : Disabled

Timer X : Pulse width measurement mode

(Count “H” level width of pulse input from CNTR

0

pin.)

A count value is read out and stored to RAM.

XXXX1011

2

●

Timer X interrupt : Enabled

256–1

256–1

1

0

1

0

0

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-23

2.3 Serial I/O

2.3.1 Memory map of serial I/O

Fig. 2.3.1 Memory map of serial I/O related registers

001F

16

0018

16

0019

16

001A

16

001B

16

001C

16

001D

16

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Serial I/O2 control register (SIO2CON)

Serial I/O2 register (SIO2)

003F

16

003A

16

003C

16

003D

16

003E

16

Interrupt edge selection register (INTEDGE)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 2 (ICON2)

Interrupt control register 1 (ICON1)

~~

~~

~

~

~

~

~

~

~

~

~

~

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-24

2.3.2 Related registers

Fig. 2.3.2 Structure of Transmit/Receive buffer register

Fig. 2.3.3 Structure of Serial I/O1 status register

Transmit/Receive buffer register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

6

7

Transmit/Receive buffer register

(TB/RB) [Address : 1816]

A transmission data is written to or a receive data is read out

from this buffer register.

• At writing : a data is written to the Transmit buffer register.

• At reading : a content of the Receive buffer register is read out.

?

?

?

?

?

5?

?

?

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

0

0

0

0

0

0

0

1

Serial I/O1 status reigster (SIO1STS) [Address : 1916]

Name

Transmit buffer empty flag

(TBE)

0 : (OE) (PE) (FE) = 0

1 : (OE) (PE) (FE) = 1

Overrun error flag (OE)

0 : Buffer full

1 : Buffer empty

Nothing is allocated for this bit. It is a write disabled bit.

When this bit is read out, the value is “0.”

Receive buffer full flag (RBF)

Transmit shift register shift

completion flag (TSC)

Parity error flag (PE)

Framing error flag (FE)

Summing error flag (SE)

0 : Buffer empty

1 : Buffer full

0 : Transmit shift in progress

1 : Transmit shift completed

0 : No error

1 : Overrun error

0 : No error

1 : Parity error

0 : No error

1 : Framing error

✕

✕

✕

✕

✕

✕

✕

✕

Serial I/O1 status register

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-25

Fig. 2.3.4 Structure of Serial I/O1 control register

Fig. 2.3.5 Structure of UART control register

b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A

16

]

Serial I/O1 control register

0 : I/O port (P47)

1 : S

RDY1

output pin

0

0

0

0

0

0

0

0

Function

At reset

RW

Name

B

0

1

2

3

4

5

6

7

At selecting clock synchronous serial I/O

0 : BRG output divided by 4

1 : External clock input

At selecting UART

0 : BRG output divided by 16

1 : External clock input divided by 16

0 : Transmit buffer empty

1 : Transmit shift operating

completion

0 : f(X

IN

)

1 : f(X

IN

)/4

0 : Serial I/O1 disabled

(P4

4

–P4

7 :

I/O port)

1 : Serial I/O1 enabled

(P4

4

–P4

7 :

Serial I/O function pin)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

0 : UART

1 : Clock synchronous serial I/O

BRG count source

selection bit (CSS)

Serial I/O1

synchronous clock

selection bit (SCS)

Transmit interrupt

source selection bit

(TIC)

S

RDY1 output enable bit

(SRDY)

Transmit enable bit (TE)

Receive enable bit (RE)

Serial I/O1 enable bit

(SIOE)

Serial I/O1 mode

selection bit (SIOM)

UART control register (UARTCON) [Address : 1B

16

]

UART control register

Function

0

0

0

0

0

1

1

1

Character length

selection bit (CHAS)

Parity enable bit

(PARE)

Stop bit length selection

bit (STPS)

P4

5

/TxD P-channel

output disable bit

(POFF)

Nothing is allocated for these bits. These are write

disabled bits. When these bits are read out, the

values are “1.”

Parity selection bit

(PARS)

In output mode

0 CMOS output

1 N-channel open-drain

output

0 : 8 bits

1 : 7 bits

0 :

Parity checking disabled

1 :

Parity checking enabled

0 1 stop bit

1 : 2 stop bits

0 : Even parity

1 : Odd parity

B

0

1

2

3

4

5

6

7

b7 b6 b5 b4 b3 b2 b1 b0

At reset

RW

Name

✕

✕

✕

:

:

:

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-26

Fig. 2.3.6 Structure of Baud rate generator

Fig. 2.3.7 Structure of Serial I/O2 control register

Serial I/O2 control register (SIO2CON) [Address : 1D

16

]

B

0

1

2

3

4

5

6

7

0

:

I/O port (P7

1

, P7

2

)

1

:

S

OUT2

, S

CLK2

output pin

0

:

I/O port (P7

3

)

1

:

S

RDY2

output pin

0

:

LSB first

1

:

MSB first

0

:

External clock

1

:

Internal clock

0 0 0 : f(X

IN

)/8

0 0 1 : f(X

IN

)/16

0 1 0 : f(X

IN

)/32

0 1 1 : f(X

IN

)/64

1 1 0 : f(X

IN

)/128

1 1 1 : f(X

IN

)/256

b2 b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

S

RDY2

output enable bit

Internal synchronous

clock selection bits

Transfer direction

selection bit

Serial I/O2 port selection bit

Serial I/O2 synchronous clock

selection bit

Nothing is allocated for this bit. This is write disabled bit. When

this bit is read out, the value is “0.”

0

0

0

0

0

0

0

0

✕

Function

At reset

RW

Name

Serial I/O2 control register

Baud rate generator

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

A count value of Baud rate generator is set.

?

Baud rate generator (BRG) [Address : 1C

16

]

?

?

?

?

?

?

?

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-27

Fig. 2.3.9 Structure of Interrupt edge selection register

Fig. 2.3.8 Structure of Serial I/O2 register

Serial I/O2 register

b7 b6 b5 b4 b3 b2 b1 b0

Function

Serial I/O2 register (SIO2) [Address : 1F16]

A shift register for serial transmission and reception.

At transmitting : Set a transmission data.

At receiving : Store a reception data.

B

0

1

2

3

4

5

6

7

At reset

RW

?

?

?

?

?

?

?

?

●

●

Interrupt edge selection register (INTEDGE) [Address : 3A

16

]

Interrupt edge selection register

B

0

1

2

6

7

3

4

5

b7 b6 b5 b4 b3 b2 b1 b0

0

0

0

0

0

0

0

0

✕

✕

✕

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “0.”

INT

0

interrupt edge

selection bit

INT

1

interrupt edge

selection bit

INT

2

interrupt edge

selection bit

Nothing is allocated for these bits. These are write disabled

bits. When these bits are read out, the values are “0.”

INT

3

interrupt edge

selection bit

INT

4

interrupt edge

selection bit

Function

At reset

RW

Name 0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-28

Timer X interrupt request

bit

Serial I/O1 receive interrupt

request bit

Interrupt request register 1

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

0

0

0

0

Interrupt request reigster 1 (IREQ1) [Address : 3C

16

]

Name

INT

0

interrupt request bit

INT

1

interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

Serial I/O1 transmit interrupt

request bit

✻

✻

✻

✻

Timer Y interrupt request bit

4

5

6

7

0

0

0

0

Timer 1 interrupt request bit 0 : No interrupt request

1 : Interrupt request

Timer 2 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

✻

✻

✻

✻

✻“0” is set by software, but not “1.”

Timer X interrupt request bit

Fig. 2.3.10 Structure of Interrupt request register 1

Fig. 2.3.11 Structure of Interrupt request register 2

Interrupt request register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

0

0

0

0

Interrupt request reigster 2 (IREQ2) [Address : 3D

16

]

Name

CNTR

0

interrupt request bit

CNTR

1

interrupt request bit

Serial I/O2 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

INT

2

interrupt request bit

✻

✻

✻

✻

5

6

7

0

0

0 : No interrupt request

1 : Interrupt request

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “0.”

AD conversion interrupt

request bit

INT

4

interrupt request bit

0 : No interrupt request

1 : Interrupt request

✻

✻

✻“0” is set by software, but not “1.”

40

0 : No interrupt request

1 : Interrupt request

INT

3

interrupt request bit ✻

0

✕

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-29

Fig. 2.3.12 Structure of Interrupt control register 1

Fig. 2.3.13 Structure of Interrupt control register 2

Interrupt control register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

0

0

0

0

Interrupt control reigster 2 (ICON2) [Address : 3F16]

Name

CNTR0 interrupt enable bit

CNTR1 interrupt enable bit

Serial I/O2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

INT2 interrupt enable bit

5

6

7

0

0

0 : Interrupt disabled

1 : Interrupt enabled

Fix this bit to “0.”

AD conversion interrupt

enable bit

INT4 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

40

0 : Interrupt disabled

1 : Interrupt enabled

INT3 interrupt enable bit

0

0

Timer Y interrupt enable bit

Interrupt control register 1

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

0

0

0

0

Interrupt control register 1 (ICON1) [Address : 3E16]

Name

INT0 interrupt enable bit

INT1 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

4

5

6

7

0

0

0

0

Timer X interrupt enable bit

Timer 1 interrupt enable bit 0 : Interrupt disabled

1 : Interrupt enabled

Timer 2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Serial I/O1 transmit interrupt

enable bit

Serial I/O1 receive interrupt

enable bit

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-30

2.3.3 Serial I/O connection examples

(1) Control of peripheral IC equipped with CS pin

There are connection examples using a clock synchronous serial I/O mode.

Figure 2.3.14 shows connection examples of a peripheral IC equipped with the CS pin.

Fig. 2.3.14 Serial I/O connection examples (1)

Port

S

CLK

T

X

D

R

X

D

Port

CS

CLK

IN

OUT

CS

CLK

IN

OUT

(4) Connecting ICs

3806 group

Peripheral IC 1

Peripheral IC 2

Port

S

CLK

T

X

D

CS

CLK

IN

OUT

(2) Transmission and reception

3806 group Peripheral IC

(E PROM etc.)

2

(3) Transmission and reception

(Pins R

X

D

and T

X

D

are connected)

(Pins IN

and OUT in peripheral IC

are connected)

CS

CLK

IN

OUT

3806 group Peripheral IC

(E PROM etc.)

2

✻2

“Port” is an output port controlled by software.

Use S

OUT

and S

IN

instead of T

X

D and R

X

D in the

serial I/O2.

Notes1:

2:

Port

S

CLK

T

X

D

CS

CLK

DATA

(1) Only transmission

(using the R

X

D pin as an I/O port)

3806 group Peripheral IC

(OSD controller etc.)

✻1

✻

1: Select an N-channel open-drain output control of T

X

D pin.

2: Use such OUT pin of peripheral IC as an N-channel open-

drain output in high impedance during receiving data.

Port

S

CLK

T

X

D

R

X

D

R

X

D

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-31

(2) Connection with microcomputer

Figure 2.3.15 shows connection examples of the other microcomputers.

Fig. 2.3.15 Serial I/O connection examples (2)

(4) Using UART

S

CLK

T

X

D

R

X

D

CLK

IN

OUT

(2) Selecting an external clock

3806 group Microcomputer

(3) Using the

SRDY

signal output function

(Selecting an external clock)

SRDY

S

CLK

T

X

D

R

X

D

RDY

CLK

IN

OUT

3806 group Microcomputer

CLK

IN

OUT

(1) Selecting an internal clock

3806 group Microcomputer

✻: UART can not be used in the serial I/O2

.

Note: Use S

OUT

and S

IN

instead of T

X

D and R

X

D in the serial I/O2.

R

X

D

T

X

D

S

CLK

T

X

D

R

X

DR

X

D

T

X

D

3806 group Microcomputer

✻

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-32

2.3.4 Setting of serial I/O transfer data format

A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The

serial I/O2 operates in a clock synchronous.

Figure 2.3.16 shows a setting of serial I/O transfer data format.

Fig. 2.3.16 Setting of Serial I/O transfer data format

1ST-8DATA-1SP

ST LSB

Serial

I/O1

UART

Clock synchronous

Serial I/O

1ST-7DATA-1SP

ST LSB

1ST-8DATA-1PAR-1SP

ST LSB

1ST-7DATA-1PAR-1SP

ST LSB

1ST-8DATA-2SP

ST LSB

1ST-7DATA-2SP

ST LSB

1ST-8DATA-1PAR-2SP

ST LSB

1ST-7DATA-1PAR-2SP

ST LSB

MSB SP

MSB SP

MSB PAR SP

MSB PAR SP

MSB 2SP

MSB 2SP

MSB PAR 2SP

MSB PAR 2SP

LSB first

Serial

I/O2 Clock synchronous

Serial I/O

LSB first

MSB first

ST : Start bit

SP : Stop bit

PAR : Parity bit

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-33

2.3.5 Serial I/O application examples

(1) Communication using a clock synchronous serial I/O (transmit/receive)

____

Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The SRDY

signal is used for communication control.

Figure 2.3.17 shows a connection diagram, and Figure 2.3.18 shows a timing chart.

Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O]

Specifications : • The Serial I/O1 is used (clock synchronous serial I/O is selected)

• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)

_____

• The SRDY1 (receivable signal) is used.

_____

• The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by

timer), and 2-byte data is transferred from the transmitting side to the receiving

side.

P4

2

/

INT

0

S

CLK1

T

X

D

3806 group

S

RDY1

S

CLK

R

X

D

3806 group

Transmitting side Receiving side

Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]

• • • •

D

0

D

4

D

2

D

1

D

6

D

5

D

7

D

3

D

0

D

4

D

2

D

1

D

6

D

5

D

7

D

3

D

0

D

1

• • • •

• • • •

T

X

D

S

CLK1

S

RDY1

2 ms

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-34

Fig. 2.3.19 Setting of related registers at a transmitting side [Communication using a clock

synchronous serial I/O]

Serial I/O1 status register (Address : 19

16

)

SIO1STS

Baud rate generator (Address : 1C

16

)

BRG

Set “division radio – 1”

Transmit buffer empty flag

• Check to be transferred data from the Transmit buffer register to

Transmit shift register.

• Writable the next transmission data to the Transmit buffer register

at being set to “1.”

Transmitting side

Transmit shift register shift completion flag

Check a completion of transmitting 1-byte data with this flag

“1” : Transmit shift completed

Serial I/O1 control register (Address : 1A

16

)

SIO1CON

BRG counter source selection bit : f(X

IN

)

Serial I/O1 synchronous clock selection bit : BRG/4

Transmit enable bit

:

Transmit enabled

Receive enable bit

:

Receive disabled

Serial I/O1 mode selection bit : Clock synchronous serial I/O

Serial I/O1 enable bit

:

Serial I/O1 enabled

Interrupt edge selection register (Address : 3A

16

)

INTEDGE

INT

0

active edge selection bit : Select INT

0

falling edge

b7 b0

1101 00

b7 b0

7

b7 b0

0

b7 b0

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-35

Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock

synchronous serial I/O]

Receive buffer full flag

Check a completion of receiving 1-byte data with this flag.

“1” : At completing to receive

“0” : At reading out a receive buffer

Receiving side

Serial I/O1 control register (Address : 1A

16

)

SIO1CON

Serial I/O1 synchronous clock selection bit : External clock

S

RDY1

output enable bit

:

Use the S

RDY1

output

Transmit enable bit

:

Transmit enabled

Set this bit to “1,” using S

RDY1

output.

Receive enable bit

:

Receive enabled

Serial I/O1 mode selection bit

:

Clock synchronous serial I/O

Serial I/O1 enable bit

:

Serial I/O1 enabled

Serial I/O1 status register (Address : 19

16

)

SIO1STS

b7 b0

b7 b0

1111 11

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-36

Control procedure : Figure 2.3.21 shows a control procedure at a transmitting side, and Figure

2.3.22 shows a control procedure at a receiving side.

Fig. 2.3.21 Control procedure at a transmitting side [Communication using a clock synchronous

serial I/O]

• Write a transmission data

The Transmit buffer empty flag is set to “0”

by this writing.

RESET

Initialization

(Address : 1A

16

)

(Address : 1C

16

)

(Address : 3A

16

), bit0

SIO1CON

BRG

INTEDGE

.....

TB/RB (Address : 18

16

)

The first byte of a

transmission data

• Detect INT

0

falling edge

IREQ1 (Address:3C

16

), bit0?

1

0

• Check to be transfered data from the Transmit

buffer register to the Transmit shift register.

(Transmit buffer empty flag)

SIO1STS (Address : 19

16

), bit0?

1

0

TB/RB (Address : 18

16

)• Write a transmission data

The Transmit buffer empty flag is set to “0”

by this writing.

The second byte of

a transmission data

• Check to be transfered data from the Transmit

buffer register to the Transmit shift register.

(Transmit buffer empty flag)

SIO1STS (Address : 19

16

), bit0?

1

0

• Check a shift completion of the Transmit shift register

(Transmit shift register shift completion flag)

SIO1STS (Address : 19

16

), bit2?

1

0

IREQ1 (Address : 3C

16

), bit0

0

●X : This bit is not used in this application.

Set it to “0” or “1.” It’s value can be disregarded.

8—1

0

1101XX00

2

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-37

Fig. 2.3.22 Control procedure at a receiving side [Communication using a clock synchronous

serial I/O]

Initialization

SIO1CON (Address : 1A

16

)1111X11X

2

.....

• S

RDY1

output

S

RDY1

signal is output by writing data to

the TB/RB.

Using the S

RDY1

, the transmit enabled bit

(bit4) of the SIO1CON is set to “1.”

• An interval of 2 ms is generated by a timer.

Y

N

• Check a completion of receiving

(Receive buffer full flag)

1

• Receive the first byte data.

A Receive buffer full flag is set to “0” by reading data.

• Check a completion of receiving

(Receive buffer full flag)

1

• Receive the second byte data.

A Receive buffer full flag is set to “0” by reading data.

●X : This bit is not used in this application.

Set it to “0” or “1.” It’s value can be disregarded.

RESET

0

0

Read out reception data from

TB/RB (Address : 18

16

)

SIO1STS (Address : 19

16

), bit1?

Read out reception data from

TB/RB (Address : 18

16

)

SIO1STS (Address : 19

16

), bit1?

TB/RB (Address : 18

16

) Dummy data

Pass 2 ms?

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-38

(2) Output of serial data (control of a peripheral IC)

Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS

signal is output to a peripheral IC through the port P53.

Fig. 2.3.23 Connection diagram [Output of serial data]

Specifications : • The Serial I/O is used. (clock synchronous serial I/O is selected)

• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)

• Transfer direction : LSB first

• The Serial I/O1 interrupt is not used.

___

• The Port P53 is connected to the CS pin (“L” active) of the peripheral IC for a

transmission control (the output level of the port P53 is controlled by software).

Figre 2.3.24 shows an output timing chart of serial data.

Fig. 2.3.24 Timing chart [Output of serial data]

P5

3

S

CLK1

T

X

D

CS

Peripheral IC

3806 group

(1) Example for using Serial I/O1 (2) Example for using Serial I/O2

DATA

CS

CLK

P5

3

S

CLK2

S

OUT2

Peripheral IC3806 group

DATA

CS

CLK

CLK

DATA

CS

CLK

DATA

CS

DO

0

DO

1

DO

2

DO

3

CLK

DATA

Note: The S

OUT2

pin is in high impedance after completing to transfer data, using the serial I/O2.

3806 GROUP USER’S MANUAL

APPLICATION

2.3 Serial I/O

2-39

Figure 2.3.25 shows a setting of serial I/O1 related registers, and Figure 2.3.26 shows a setting of

serial I/O1 transmission data.

Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]

Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data]

Serial I/O1 synchronous clock selection bit : BRG/4

SRDY1 output enable bit : Not use the

S

RDY1 signal output function

0

Serial I/O1 transmit interrupt enable bit : Interrupt disabled

ICON1

Interrupt control register 1 (Address : 3E 16)

Serial I/O1 transmit interrupt request bit

Using this bit, check the completion of

transmitting 1-byte base data.

“1” : Transmit shift completion

IREQ1

Interrupt request register 1 (Address : 3C 16)

001SIO1CON

Serial I/O1 control register (Address : 1A 16)

0011

BRG count source selection bit : f(X IN)

Transmit interrupt source selection bit : Transmit shift operating completion

Transmit enable bit : Transmit enabled

1

Receive enable bit : Receive disabled

b7 b0

0

b7 b0

b7 b0

Serial I/O1 mode selection bit : Clock synchronous serial I/O

Serial I/O1 enable bit : Serial I/O1 enabled

0

P45/TXD P-channel output disable bit : CMOS output

UARTCON

UART control register (Address : 1B 16)

b7 b0

7Set “division ratio – 1”

BRG

Baud rate generator (Address : 1C 16)

b7 b0

Set a transmission data.

Check that transmission of the previous data is

completed before writing data (bit 3 of the

Interrupt request register 1 is set to “1”).

TB/RB

Transmit/Receive buffer register (Address : 18

16

)

b7 b0

2.3 Serial I/O

2-40

APPLICATION

3806 GROUP USER’S MANUAL

Control procedure : When the registers are set as shown in Fig. 2.3.25, the Serial I/O1 can transmit

1-byte data simply by writing data to the Transmit buffer register.

Thus, after setting the CS signal to “L,” write the transmission data to the

Receive buffer register on a 1-byte base, and return the CS signal to “H” when

the desired number of bytes have been transmitted.

Figure 2.3.27 shows a control procedure of serial I/O1.

Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data]

(Address : 1C

16

)

(Address : 3E

16

), bit3

(Address : 0A

16

), bit3

(Address : 0B

16

)

Y

1

Set the Serial I/O1.

Set the CS signal output level to “L.”

Set the Serial I/O1 transmit interrupt

request bit to “0.”

Write a transmission data.

(start to transmit 1-byte data)

Check the completion of transmitting 1-

byte data.

Use any of RAM area as a counter for

counting the number of transmitted bytes.

Check that transmission of the target

number of bytes has been completed.

Return the CS signal output level to “H”

when transmission of the target number of

bytes is completed.

P5 (Address : 0A

16

), bit3 0

0

NComplete to transmit data?

Initialization

(Address : 1A

16

)

(Address : 1B

16

), bit4

SIO1CON

UARTCON

BRG

ICON1

P5

P5D

.... ....

0

IREQ1 (Address : 3C

16

), bit3 0

TB/RB (Address : 18

16

)

P5 (Address : 0A

16

), bit3 1

a transmission

data

●

●

●

●

●

●

●

●

●

●X : This bit is not used in this application.

Set it to “0” or “1.” It’s value can be disregarded.

●

Serial I/O1 transmit interrupt : Disabled

Set the CS signal output port.

(“H” level output)

RESET

IREQ1 (Address : 3C

16

), bit3?

8–1

0

1

11011000

2

XXXX1XXX

2

APPLICATION

2.3 Serial I/O

2-41

3806 GROUP USER’S MANUAL

Figure 2.3.28 shows a setting of serial I/O2 related registers, and Figure 2.3.29 shows a setting of

serial I/O2 transmission data.

Serial I/O2 port selection bit : Use the Serial I/O2

S

RDY2

output enable bit : Not use the

S

RDY2

signal output function

0

Serial I/O2 interrupt enable bit

:

Interrupt disabled

ICON2

Interrupt control register 2 (Address : 3F

16

)

Serial I/O2 interrupt request bit

Using this bit, check the completion of

transmitting 1-byte base data.

“1” : Transmit completion

IREQ2

Interrupt request register 2 (Address : 3D

16

)

010SIO2CON

Serial I/O2 control register (Address : 1D

16

)

0011

Internal synchronous clock selection bits : f(X

IN

)/32

Transfer direction selection bit : LSB first

Serial I/O2 synchronous clock selection bit : Internal clock

b7 b0

0

b7 b0

b7 b0

Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data]

Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]

Set a transmission data.

Check that transmission of the previous data is

completed before writing data (bit 2 of the Interrupt

request register 2 is set to “1”).

SIO2

Serial I/O2 register (Address : 1F

16

)

b7 b0

2.3 Serial I/O

2-42

APPLICATION

3806 GROUP USER’S MANUAL

Control procedure : When the registers are set as shown in Fig. 2.3.28, the Serial I/O2 can transmit

1-byte data simply by writing data to the Serial I/O2 register.

Thus, after setting the CS signal to “L,” write the transmission data to the Serial

I/O1 register on a 1-byte base, and return the CS signal to “H” when the desired

number of bytes have been transmitted.

Figure 2.3.30 shows a control procedure of serial I/O2.

Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data]

0

Y

1

N

Set the Serial I/O2 control register.

Serial I/O2 interrupt : Disabled

Set the CS signal output port.

(“H” level output)

Set the CS signal output level to “L.”

Set the Serial I/O2 interrupt

request bit to “0.”

Write a transmission data.

(start to transmit 1-byte data)

Check the completion of transmitting 1-

byte data.

Use any of RAM area as a counter for

counting the number of transmitted bytes.

Check that transmission of the target

number of bytes has been completed.

Return the CS signal output level to “H”

when transmission of the target number of

bytes is completed.

P5 (Address : 0A

16

), bit3 0

Initialization

SIO2CON

ICON2

P5

P5D

.... ....

(Address : 1D

16

)

(Address : 3F

16

), bit2

(Address : 0A

16

), bit3

(Address : 0B

16

)

X1001010

2

XXXX

1

XXX

2

IREQ2 (Address : 3D

16

), bit2 0

P5 (Address : 0A

16

), bit3 1

●

●

●

●

●

●

●

●

●

●X : This bit is not used in this application.

Set it to “0” or “1.” It’s value can be disregarded.

●

SIO2 (Address : 1F

16

)a transmission

data

IREQ2 (Address : 3D

16

), bit2?

Complete to transmit data?

RESET

0

1

APPLICATION

2.3 Serial I/O

2-43

3806 GROUP USER’S MANUAL

(3) Cyclic transmission or reception of block data (data of a specified number of bytes)

between microcomputers

[without using an automatic transfer]

Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock

and the data between the transmitting and receiving sides may be lost because of noise

included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This

“heading adjustment” is carried out by using the interval between blocks in this example.

Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between

microcomputers]

S

CLK

Master unit

S

CLK

Slave unit

Note: Use S

OUT

and S

IN

instead of T

X

D and R

X

D in the serial I/O2.

T

X

D

R

X

DT

X

D

R

X

D

Specifications : • The serial I/O1 is used (clock synchronous serial I/O is selected).

• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)

• Byte cycle: 488 µs

• Number of bytes for transmission or reception : 8 byte/block

• Block transfer cycle : 16 ms

• Block transfer period : 3.5 ms

• Interval between blocks : 12.5 ms

• Heading adjustive time : 8 ms

Limitations of the specifications

1. Reading of the reception data and setting of the next transmission data must be completed

within the time obtained from “byte cycle – time for transferring 1-byte data” (in this example,

the time taken from generating of the Serial I/O1 receive interrupt request to generating of the

next synchronizing clock is 431 µs).

2. “Heading adjustive time < interval between blocks” must be satisfied.

2.3 Serial I/O

2-44

APPLICATION

3806 GROUP USER’S MANUAL

The communication is performed according to the timing shown below. In the slave unit, when a

synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is

processed as the beginning (heading) of a block.

When a clock is input again after one block (8 byte) is received, the clock is ignored.

Figure 2.3.33 shows a setting of related registers.

Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers]

D

0

Byte cycle

Block transfer period

Block transfer cycle

D

1

D

2

D

7

D

0

Interval between blocks

Processing for heading adjustment

Heading adjustive time

Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between

microcomputers]

Transmit enabled

SIO1CON

Serial I/O1 control register (Address : 1A16)

Synchronous

clock : BRG/4

Transmit interrupt source :

Transmit shift operating completion

Receive enabled

Clock synchronous serial I/O

0111100

Master unit

1

Serial I/O1 enabled

BRG count source : f(XIN)

Not use the SRDY1 output

Not be effected by

external clock

Transmit enabled

SIO1CON

Serial I/O1 control register (Address : 1A16)

Not use the serial I/O1 transmit interrupt

Receive enabled

Clock synchronous serial I/O

11

11

Slave unit

1

Serial I/O1 enabled

0

Synchronous clock : External clock

Not use the SRDY1 output

UARTCON

UART control register (Address : 1B16)

P45/TXD pin : CMOS output

0

Both of units

b7 b0

7

BRG b7 b0

Baud rate generator (Address : 1C16)

Set “division ratio – 1”

b7 b0 b7 b0

APPLICATION

2.3 Serial I/O

2-45

3806 GROUP USER’S MANUAL

Control procedure :

Control in the master unit

After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit

transmission or reception of 1-byte data is started simply by writing transmission data to the

Transmit buffer register.

To perform the communication in the timing shown in Figure 2.3.32, therefore, take the timing into

account and write transmission data. Read out the reception data when the Serial I/O1 transmit

interrupt request bit is set to “1,” or before the next transmission data is written to the Transmit

buffer register.

A processing example in the master unit using timer interrupts is shown below.

Fig. 2.3.34 Control in the master unit

Interrupt processing routine

executed every 488

µs

Write a transmission data

Read a reception data

N

Within a block transfer period?

Y

Y

Complete to transfer a block?

N

RTI

Write the first transmission data

(first byte) in a block

Count a block interval counter

N

Start a block transfer?

Y

Generate a certain block interval by

using a timer or other functions.

●

Check the block interval counter and

determine to start of a block transfer.

●

CLT (Note 1)

CLD (Note 2)

Push register to stack

Note 1: When using the Index X mode flag (T).

Note 2: When using the Decimal mode flag (D).

Push the register used in the interrupt

processing routine into the stack.

●

Pop registers Pop registers which is pushed to stack.

●

2.3 Serial I/O

2-46

APPLICATION

3806 GROUP USER’S MANUAL

Control in the slave unit

After a setting of the related registers is completed as shown in Figure 2.3.33, the slave unit becomes the

state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit

is set to “1” every time an 8-bit synchronous clock is received.

By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the

Transmit buffer register after received data is read out.

However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the

following processing will be performed.

1. The first 1 byte data of the transmission data in the block is written into the Transmission buffer register.

2. The data to be received next is processed as the first 1 byte of the received data in the block.

Figure 2.3.35 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt

(for head adjustive).

Fig. 2.3.35 Control in the slave unit

Write a transmission data

Read a reception data

N

Within a block transfer period?

Y

Y

A received byte counter

≥

8?

N

RTI

Write any data (FF16)

A received byte counter +1

Heading adjustive

counter Initialized

value (Note 3)

Serial I/O1 receive interrupt

processing routine Timer interrupt processing

routine

Heading adjustive counter – 1

N

Heading adjustive

counter = 0?

Y

RTI

Write the first transmission data

(first byte) in a block

A received byte counter 0

Check the received byte

counter to judge if a block

has been transfered.

In this example, set the value which is equal to the

heading adjustive time divided by the timer interrupt

cycle as the initialized value of the heading adjustive

counter.

For example: When the heading adjustive time is 8 ms

and the timer interrupt cycle is 1 ms, set

8 as the initialized value.

3:

●

CLT (Note 1)

CLD (Note 2)

Push register to stack Push the register used in

the interrupt processing

routine into the stack.

●CLT (Note 1)

CLD (Note 2)

Push register to stack Push the register used in

the interrupt processing

routine into the stack.

●

Pop registers Pop registers which is

pushed to stack.

●

Pop registers Pop registers which is

pushed to stack.

●

Notes 1: When using the Index X mode flag (T).

2: When using the Decimal mode flag (D).

APPLICATION

2.3 Serial I/O

2-47

3806 GROUP USER’S MANUAL

(4) Communication (transmit/receive) using an asynchronous serial I/O (UART)

Point : 2-byte data is transmitted and received through an asynchronous serial I/O.

The port P40 is used for communication control.

Figure 2.3.36 shows a connection diagram, and Figure 2.3.37 shows a timing chart.

Fig. 2.3.36 Connection diagram [Communication using UART]

Transmitting side

P4

0

3806 group

P4

0

3806 group

Receiving side

T

X

D

X

D

Specifications : • The Serial I/O1 is used (UART is selected).

• Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512)

• Communication control using port P40

(The output level of the port P40 is controlled by softoware.)

• 2-byte data is transferred from the transmitting side to the receiving side at inter-

vals of 10 ms (generated by timer).

Fig. 2.3.37 Timing chart [Communication using UART]

P4

0

T

X

D

10 ms

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

ST SP(2) D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

ST SP(2) D

0

ST

……

…

R

2.3 Serial I/O

2-48

APPLICATION

3806 GROUP USER’S MANUAL

Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values,

Figure 2.3.38 shows a setting of related registers at a transmitting side, and Figure 2.3.39 shows a

setting of related registers at a receiving side.

Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values

BRG setting value

Actual time (bps)

BRG setting value

at f(XIN) = 4.9152 MHZ

600

1200

2400

4800

9600

19200

38400

76800

31250

62500

600.96

1201.92

2403.85

4807.69

9615.38

20833.33

41666.67

83333.33

31250.00

62500.00

207(CF16)

103(6716)

51(3316)

25(1916)

12(0C16)

5(0516)

2(0216)

5(0516)

15(0F16)

7(0716)

600.00

1200.00

2400.00

4800.00

9600.00

19200.00

38400.00

76800.00

191(BF16)

95(5F16)

47(2F16)

23(1716)

11(0B16)

5(0516)

2(0216)

5(0516)

600.00

1200.00

2400.00

4800.00

9600.00

19200.00

38400.00

76800.00

127(7F16)

63(3F16)

31(1F16)

15(0F16)

7(0716)

3(0316)

1(0116)

3(0316)

at f(XIN) = 8 MHZat f(XIN) = 7.3728 MHZ

Transfer bit

rate(bps)

(Note 1)

BRG count

source

(Note 2)

Actual time (bps) Actual time (bps)

Transfer bit rate (bps) = (BRG setting value + 1) ✕ 16 ✕ m

f(XIN)

BRG setting value

f(XIN)/4

f(XIN)/4

f(XIN)/4

f(XIN)/4

f(XIN)/4

f(XIN)/4

f(XIN)/4

f(XIN)

f(XIN)

f(XIN)

Notes 1: Equation of transfer bit rate

m: when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,” a value

of m is 1.

when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1,” a value

of m is 4.

2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A16).

APPLICATION

2.3 Serial I/O

2-49

3806 GROUP USER’S MANUAL

Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART]

b7 b0

00

b7 b0

10011

Serial I/O1 status register (Address : 19

16

)

SIO1STS

Transmitting side

Baud rate generator (Address : 1C

16

)

BRG

SIO1CON

BRG count source selection bit : f(X

IN

)/4

Serial I/O1 synchronous clock selection bit : BRG/16

Transmit enable bit : Transmit enabled

Receive enable bit : Receive disabled

Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)

Serial I/O1 enable bit : Serial I/O1 enabled

S

RDY1

output enable bit : Not use S

RDY1

output

UART control register (Address : 1B

16

)

UARTCON

Character length selection bit : 8 bits

Parity enable bit : Parity checking disabled

P4

5

/T

X

D P-channel output disable bit : CMOS output

Stop bit length selection bit : 2 stop bits

f(X

IN

)

Transfer bit rate ✕ 16 ✕ m–1

Transmit buffer empty flag

•

Check to be transferred data from the Transmit buffer

register to the Transmit shift register.

•

Writable the next transmission data to the Transmit buffer

register at being set to

“1.”

Transmit shift register shift completion flag

Check a completion of transmitting 1-byte data with this flag.

“1” : Transmit shift completed

Serial I/O1 control register (Address : 1A

16

)

Set

when bit 0 of the Serial I/O1 control register (Address : 1A

16

) is set to

“0,” a value of m is 1.

when bit 0 of the Serial I/O1 control register (Address : 1A

16)

is set to

“1,” a value of m is 4.

✻

✻

0

1

b7 b0

00

7

b7 b0

2.3 Serial I/O

2-50

APPLICATION

3806 GROUP USER’S MANUAL

Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART]

Receive buffer full flag

Receiving side

Serial I/O1 status register (Address : 19

16

)

SIO1STS

BRG

Serial I/O1 control register (Address : 1A

16

)

SIO1CON

UARTCON

Check a completion of receiving 1-byte data with this flag.

“1” : at completing to receive

“0” : at reading out a content of the Receive buffer register

Overrun error flag

“1” : when data are ready to be transferred to the

Receive shift register in the state of storing data

into the Receive buffer register.

Parity error flag

“1” : when parity error occurs at enabled parity.

Framing error flag

“1” : when data can not be received at the timing of

setting a stop bit.

Summing error flag

“1” : when even one of the following errors occurs.

• Overrun error

• Parity error

• Framing error

BRG count source selection bit : f(X

IN

)/4

Serial I/O1 synchronous clock selection bit : BRG/16

Transmit enable bit : Transmit disabled

Receive enable bit : Receive enabled

Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)

Serial I/O1 enable bit : Serial I/O1 enabled

S

RDY1

output enable bit : Not use S

RDY1

out

UART control register (Address : 1B

16

)

Character length selection bit : 8 bits

Parity enable bit : Parity checking disabled

Stop bit length selection bit : 2 stop bits

Baud rate generator (Address : 1C

16

)

f(X

IN

)

Transfer bit rate ✕ 16 ✕ m–1

Set

when bit 0 of the Serial I/O1 control register (Address : 1A

16

) is set to

“0,” a value of m is 1.

when bit 0 of the Serial I/O1 control register (Address : 1A

16

) is set to

“1,” a value of m is 4.

✻

✻

7

b7 b0

b7 b0

b7 b0

100

0

b7 b0

101001

APPLICATION

2.3 Serial I/O

2-51

3806 GROUP USER’S MANUAL

Control procedure : Figure 2.3.40 shows a control procedure at a transmitting side, and Figure 2.3.41

shows a control procedure at a receiving side.

Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART]

TB/RB

(

Address : 18

16

)

Y

N

RESET

P4 (Address : 08

16

), bit0 0

SIO1STS (Address : 19

16

), bit0?

SIO1STS (Address : 19

16

), bit2?

1

0

1

0

The second byte of

a transmission data

1

0

SIO1STS (Address : 19

16

), bit0?

TB/RB

(

Address : 18

16

)The first byte of a

transmission data

P4 (Address : 08

16

), bit0 1

Pass 10 ms?

Initialization

SIO1CON

UARTCON

BRG

P4

P4D

.....

(Address : 1A

16

)

(Address : 1B

16

)

(Address : 1C

16

)

(Address : 08

16

), bit0

(Address : 09

16

)

1001X001

2

00001000

2

8

–1

0

XXXXXXX1

2

•

End of communication

●X : This bit is not used in this application.

Set it to

“0”

or

“1.”

It’s value can be disregarded.

•

Set port P4

0

for a communication control.

•

An interval of 10 ms is generated by a timer.

•

Start of communication.

•

Write a transmission data

The Transmit buffer empty flag is set to

“0”

by this writing.

•

Write a transmission data

The Transmit buffer empty flag is set to

“0”

by this writing.

•

Check to be transferred data from the Transmit

buffer register to the Transmit shift register.

(Transmit buffer empty flag)

•

Check to be transferred data from the Transmit

buffer register to the Transmit shift register.

(Transmit buffer empty flag)

•

Check a shift completion of the Transmit shift register.

(Transmit shift register shift completion flag)

2.3 Serial I/O

2-52

APPLICATION

3806 GROUP USER’S MANUAL

Fig. 2.3.41 Control procedure at a receiving side [Communication using UART]

•

Check a completion of receiving.

(Receive buffer full flag)

•

Check an error flag.

•

Receive the first 1 byte data

A Receive buffer full flag is set

to

“0”

by reading data.

•

Check a completion of receiving.

(Receive buffer full flag)

•

Receive the second byte data

A Receive buffer full flag is set

to

“0”

by reading data.

•

Check an error flag.

•

Countermeasure for a bit slippage

●X

: This bit is not used in this application.

Set it to

“0”

or

“1.”

It’s value can be disregarded.

RESET

SIO1CON (Address : 1A

16

)

SIO1CON (Address : 1A

16

)0000X001

2

1010X001

2

0

0

1P4 (Address : 08

16

), bit0?

SIO1STS (Address : 19

16

), bit6?

Read out a reception data

from RB (Address : 18

16

)

SIO1STS (Address : 19

16

), bit1?

SIO1STS (Address : 19

16

), bit6?

Read out a reception data

from RB (Address : 18

16

)

SIO1STS (Address : 19

16

), bit1?

(Address : 1A

16

)

(Address : 1B

16

)

(Address : 1C

16

)

(Address : 09

16

)

Initialization

SIO1CON

UARTCON

BRG

P4D

1010X001

2

00001000

2

8–1

XXXXXXX0

2

.....

1

0

0

1

0

1

1

Processing for error

3806 GROUP USER’S MANUAL

APPLICATION

2.4 A-D converter

2-53

2.4 A-D converter

2.4.1 Memory map of A-D conversion

Fig. 2.4.1 Memory map of A-D conversion related registers

003F

16

0034

16

0035

16

003D

16

Interrupt request register 2 (IREQ2)

Interrupt control register 2 (ICON2)

AD/DA control register (ADCON)

A-D conversion register (AD)

~~

~~

~

~~

~

~

~

APPLICATION

2.4 A-D converter

2-54 3806 GROUP USER’S MANUAL

2.4.2 Related registers

Fig. 2.4.2 Structure of AD/DA control register

Fig. 2.4.3 Structure of A-D conversion register

AD/DA control register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

Name

Analog input pin selection bits

AD/DA control register (ADCON) [Address : 34

16

]

0 0 0 : P6

0

/AN

0

0 0 1 : P6

1

/AN

1

0 1 0 : P6

2

/AN

2

0 1 1 : P6

3

/AN

3

1 0 0 : P6

4

/AN

4

1 0 1 : P6

5

/AN

5

1 1 0 : P6

6

/AN

6

1 1 1 : P6

7

/AN

7

b2 b1 b0

1

3

1

0

0

0

0

0

0 : DA

1

output disable

1 : DA

1

output enable

DA

1

output enable bit

6

0

7

0

✕

Nothing is allocated for these bits. These are write disabled bits.

4

When these bits are read out, the values are “0.”

0 : DA

2

output disabled

1 : DA

2

output enabled

DA

2

output enable bit

2

50

✕

AD conversion completion bit 0 : Conversion in progress

1 : Conversion completed

A-D conversion register

b7 b6 b5 b4 b3 b2 b1 b0

B Function

At reset

RW

A-D conversion register (AD) [Address : 35

16

]

The read-only register which A-D conversion results are stored. ✕

0

1

2

3

4

5

6

7

?

?

?

?

?

?

?

?

✕

✕

✕

✕

✕

✕

✕

3806 GROUP USER’S MANUAL

APPLICATION

2.4 A-D converter

2-55

Fig. 2.4.4 Structure of Interrupt request register 2

Fig. 2.4.5 Structure of Interrupt control register 2

Interrupt request register 2

b7 b6 b5 b4 b3 b2 b1 b0

B Function

At reset

RW

0

1

2

3

0

0

0

0

Interrupt request reigster 2 (IREQ2) [Address : 3D

16

]

Name

CNTR

0

interrupt request bit

CNTR

1

interrupt request bit

Serial I/O2 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

INT

2

interrupt request bit

✻

✻

✻

✻

5

6

7

0

0

0 : No interrupt request

1 : Interrupt request

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “0.”

AD conversion interrupt

request bit

INT

4

interrupt request bit

0 : No interrupt request

1 : Interrupt request

✻

✻

✻“0” is set by software, but not “1.”

4 0

0 : No interrupt request

1 : Interrupt request

INT

3

interrupt request bit ✻

0

✕

Interrupt control register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

0

0

0

0

Interrupt control reigster 2 (ICON2) [Address : 3F

16

]

Name

CNTR

0

interrupt enable bit

CNTR

1

interrupt enable bit

Serial I/O2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

INT

2

interrupt enable bit

5

6

7

0

0

0 : Interrupt disabled

1 : Interrupt enabled

Fix this bit to “0.”

AD conversion interrupt

enable bit

INT

4

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

40

0 : Interrupt disabled

1 : Interrupt enabled

INT

3

interrupt enable bit

0

0

APPLICATION

2.4 A-D converter

2-56 3806 GROUP USER’S MANUAL

2.4.3 A-D conversion application example

Conversion of Analog input voltage

Outline : The analog input voltage input from the sensor is converted into digital values.

Figure 2.4.6 shows a connection diagram, and Figure 2.4.7 shows a setting of related registers.

Fig. 2.4.6 Connection diagram [Conversion of Analog input voltage]

Specifications : • The analog input voltage input from the sensor is converted into digital values.

• The P60/AN0 pin is used as an analog input pin.

Fig. 2.4.7 Setting of related registers [Conversion of Analog input voltage]

P6

0

/AN

0

3806 group

Sensor

0

Analog input pin selection bits : Select the P6

0

/AN

0

pin

ADCON

AD/DA control register (Address : 34

16)

000

AD conversion completion bit : Conversion in progress

Store a result of A-D conversion (Note)

AD

A-D conversion register (Address : 35

16)

(read-only)

Note: Read out a result of A-D conversion after bit 3 of the

AD/DA control register (ADCON) is set to “1.”

3806 GROUP USER’S MANUAL

APPLICATION

2.4 A-D converter

2-57

Control procedure : By setting the related registers as shown in Figure 2.4.7, the analog input

voltage input from the sensor are converted into digital values.

Fig. 2.4.8 Control procedure [Conversion of Analog input voltage]

~

~

Read out AD (Address : 35

16

)

ADCON (Address : 34

16

), bit0 – bit2 000

2

ADCON (Address : 34

16

), bit3 0

0

ADCON (Address : 34

16

), bit3?

1

•

Select the P6

0

/AN

0

pin as an analog input pin.

•

Start A-D conversion.

•

Check the completion of A-D conversion.

•

Read out the conversion result.

~

~

APPLICATION

2.5 Processor mode

2-58 3806 GROUP USER’S MANUAL

2.5 Processor mode

2.5.1 Memory map of processor mode

Fig. 2.5.1 Memory map of processor mode related register

2.5.2 Related register

Fig. 2.5.2 Structure of CPU mode register

CPU mode register (CPUM) [Address : 3B

16

]

B

0

1

2

CPU mode register

00 : Single-chip mode

01 : Memory expansion mode

10 : Microprocessor mode

11 : Not available

0 : 0 page

1 : 1 page

3

4

5

6

7

Processor mode bits

Stack page selection bit

Nothing is allocated for these bits. These are write disabled bits.

When these bits are read out, the values are “0.”

Function

At reset

RW

Name

0

0

0

0

0

0

0

✻

✻ An initial value of bit 1 is determined by a level of the CNV

SS

pin.

b7 b6 b5 b4 b3 b2 b1 b0

✕

✕

✕

✕

✕

003B

16

CPU mode register (CPUM)

APPLICATION

2.5 Processor mode

2-59

3806 GROUP USER’S MANUAL

2.5.3 Processor mode application examples

____

(1) Application example of memory expansion in the case where the ONW (One-Wait)

function is not used

Outline : The external memory is accessed in the microprocessor mode.

At f(XIN) = 8 MHz, an available RAM is given by the following :

___

• OE access time : ta (OE) ≤ 50 ns

• Setup time for writing data : tsu (D) ≤ 65 ns

For example, the M5M5256BP-10 whose address access is 100 ns is available.

Figure 2.5.3 shows an expansion example of a 32K byte ROM and a 32K byte RAM.

Fig. 2.5.3 Expansion example of ROM and RAM

3806 group

CNVSS

ONW

AD15

8P4

8P5

8P6

AD14

AD0

DB0

DB7

RD

WR

M5M27C256AK-10 M5M5256BP-10

CE

A0–A14

D0–D7

OE

A0–A14

DQ1–DQ8

OE W

8MHz VCC = 5.0V ± 10 %

000016

800016

044016

004016

000816

FFFF16

External RAM area

(M5M5256BP)

SFR area

Ineternal RAM area

External RAM area

(M5M5256BP)

External ROM area

(M5M27C256AK)

Memory map

74F04 S

––

15

8

2P30, P31

EPROM SRAM

8P7

8P8

APPLICATION

2.5 Processor mode

2-60 3806 GROUP USER’S MANUAL

Figure 2.5.4, Figure 2.5.5 and Figure 2.5.6 shows a standard timing at 8 MHz (No-Wait).

Fig. 2.5.4 Read-cycle (OE access, SRAM)

Fig. 2.5.5 Read-cycle (OE access, EPROM)

Output enabled access time of M5M5256BP

Data bus setup time before RD of 3806

td(AH–RD)

RD pulse width of 3806

RD delay time after outputting address of 3806

50 ns (max)

65 ns (min)

Address (low-order)

A

0

–A

7

(Port P0)

Address (high-order)

A

8

–A

14

(Port P1)

Data

DQ

1

–DQ

8

(Port P2)

S

(A15)

WR

“H” level

125 ns - 10 ns (min)

125 ns - 35 ns (min)

OE

(RD of 3806)

td(AH–RD) t

WL

(RD)

ta(OE)

tsu(DB–RD)

:

:

t

WL

(RD)

:

ta(OE)

:

tsu(DB–RD)

:

RD delay time after outputting address of 3806

:

Output enabled access time of M5M27C256AK

:

Data bus setup time before RD of 3806

50 ns (max)

65 ns (min)

Address (low-order)

A

0–

A

7

(Port P0)

Address (high-order)

A

8–

A

14

(Port P1)

Data

D

0–

D

7

(Port P2)

WR

“H” level

CE

5.8 ns (max)

t

PHL

125 ns - 10ns (min)

125 ns - 35 ns (min)

OE

(RD of 3806)

td(AH–RD) t

WL

(RD)

ta(OE)

tsu(DB–RD)

:

RD pulse width of 3806

ta(OE)

td(AH–RD)

t

WL

(RD)

tsu(DB–RD)

t

PHL

:

Output delay time of 74F04

APPLICATION

2.5 Processor mode

2-61

3806 GROUP USER’S MANUAL

Fig. 2.5.6 Write-cycle (W control, SRAM)

td(AH–WR)

W

(WR of 3806)

65 ns (max)

35 ns (min)

Address (low-order)

Address (high-order)

Data

DQ1–DQ8

(Port P2)

S

(A15)

OE

(RD of 3806) “H“ level

125 ns - 10 ns (min)

125 ns - 35 ns (min)

td(AH–WR) tWL(WR)

td(WR–DB)

tsu(D)

: WR delay time after outputting address of 3806

: WR pulse width of 3806

tWL(WR) : Data bus delay time after WR of 3806

td(WR–DB) : Data setup time of M5M5256BP

tsu(D)

A0–A7

(Port P0)

A8–A14

(Port P1)

APPLICATION

2.5 Processor mode

2-62 3806 GROUP USER’S MANUAL

_____

(2) Application example of memory expansion in the case where the ONW (One-Wait)

function is used

____

Outline : ONW function is used when the external memory access is slow.

____

If “L” level signal is input to the P32/ONW pin while the CPU is in the read or write status,

the read or write cycle corresponding to 1 cycle of is extended. In the extended period,

___ ___ ____

the RD or WR signal is kept at the “L” level. The ONW function operates only when data is

read from or written into addresses 000016 to 000716 and addresses 044016 to FFFF16.

____

Figure 2.5.7 shows an application example of the ONW function.

____

Fig. 2.5.7 Application example of the ONW function

3806 group

CNV

SS

AD

15

8P5

8P6

ONW

AD

14

AD

0

DB

0

DB

7

RD

WR

M5M27C256AK-10 M5M5256BP-10

CE

A

0

–A

14

D

0

–D

7

OE

A

0

–A

14

DQ

1

–DQ

8

OE W

8MHz V

CC

= 5.0V±10 %

External RAM area

(M5M5256BP)

SFR area

Internal RAM area

External RAM area

(M5M5256BP)

External ROM area

(M5M27C256AK)

0000

16

8000

16

0440

16

0040

16

0008

16

FFFF

16

Memory map

74F04

S

–

15

8

8P4

2P3

0

, P3

1

EPROM SRAM

–

APPLICATION

2.5 Processor mode

2-63

3806 GROUP USER’S MANUAL

(3) Application example of memory expansion in the case where the High-speed version

(A-version) is used

Outline : High-speed version is used when the extarnal memory access is fast.

At f(XIN) = 9 MHz, an available RAM is given by the following :

___

• OE access time : ta (OE) ≤ 35 ns

• Setup time for writing data : tsu (D) ≤ 50 ns

For example, the M5M5256BP-70 whose address access is 70 ns is available.

Figure 2.5.8 shows an expansion example of a 32K byte ROM and a 32K byte RAM.

Fig. 2.5.8 Expansion example of ROM and RAM [High-speed version]

8

3806 group (High-speed version)

CNV

SS

ONW

AD

15

8P4

P5

8P6

AD

14

AD

0

DB

0

DB

7

RD

WR

M5M27C256AK-85 M5M5256BP-70

CE

A

0

–A

14

D

0

–D

7

OE

A

0

–A

14

DQ

1

–DQ

8

OE W

9MHz V

CC

= 5.0V±10 %

External RAM area

(M5M5256BP)

SFR area

Internal RAM area

External RAM area

(M5M5256BP)

External ROM area

(M5M27C256AK)

0000

16

8000

16

0440

16

0040

16

0008

16

FFFF

16

Memory

74F04 S

–

15

8

2P3

0

, P3

1

EPROM SRAM

8P7

8P8

–

APPLICATION

2.5 Processor mode

2-64 3806 GROUP USER’S MANUAL

Figure 2.5.9, Figure 2.5.10 and Figure 2.5.11 shows a standard timing at 9 MHz (No-Wait).

Fig. 2.5.9 Read-cycle (OE access, SRAM) [High-speed version]

Fig. 2.5.10 Read-cycle (OE access, EPROM) [High-speed version]

35 ns (max)

50 ns (min)

Address (low-order)

A

0

–

A

7

(Port P0)

Address (high-order)

A

8

–

A

14

(Port P1)

Data

DQ

1

–

DQ

8

(Port P2)

S

(A15)

WR

“H” level

111 ns - 10ns (min)

111 ns - 35 ns (min)

OE

(RD of 3806)

ta(OE)

tsu(DB–RD)

td(AH–RD) t

WL

(RD)

td(AH–RD)

t

WL

(RD)

ta(OE)

tsu(DB–RD)

: RD delay time after outputting address of 3806

: RD pulse width of 3806

: Output enabled access time of M5M5256BP

: Data bus setup time before RD of 3806

:

RD pulse width of 3806

45 ns (max)

50 ns (min)

Adderss (low-order)

A

0

–A

7

(Port P0)

Adderss (high-order)

A

8

–A

14

(Port P1)

Data

D

0

–D

7

(Port P2)

WR

“H” level

CE

5.8 ns (max)

t

PHL

111 ns - 10ns (min)

111 ns - 35 ns (min)

OE

(RD of 3806)

td(AH–RD) t

WL

(RD)

ta(OE)

tsu(DB–RD)

ta(OE)

td(AH–RD)

t

WL

(RD)

tsu(DB–RD)

t

PHL

:

Output delay time of 74F04

:

RD delay time after outputting address of 3806

:

Data bus setup time before RD of 3806

:

Output enabled access time of M5M27C256AK

APPLICATION

2.5 Processor mode

2-65

3806 GROUP USER’S MANUAL

Fig. 2.5.11 Write-cycle (W control, SRAM) [High-speed version]

30 ns (max)

30 ns (min)

Address (low-order)

Address (high-order)

Data

DQ

1

–DQ

8

(Port P2)

S

(A15)

OE

(RD of 3806) “H” level

111 ns - 10 ns (min)

111 ns - 35 ns (min)

W

(WR of 3806)

td(AH–WR) t

WL

(WR)

td(WR–DB)

tsu(D)

td(AH–WR)

t

WL

(WR)

td(WR–DB)

tsu(D)

A

0

–A

7

(Port P0)

A

8

–A

14

(Port P1)

:

WR delay time after outputting address of 3806

:

WR pulse width of 3806

:

Data bus delay time after WR of 3806

:

Data setup time of M5M5256BP

APPLICATION

2-66

2.6 Reset

3806 GROUP USER’S MANUAL

2.6 Reset

2.6.1 Connection example of reset IC

Figure 2.6.2 shows the system example which switch to the RAM backup mode by detecting a drop of the

system power source voltage with the INT interrupt.

M62022L

3806 group

RESET

1

5

3

91

35

40

0.1

µF

Power source

GND

Delay capacity

4

Output

V

SS

V

CC

Fig. 2.6.1 Example of Poweron reset circuit

Fig. 2.6.2 RAM back-up system

System power

source voltage

+5

M62009L, M62009P, M62009FP

7

5

4

91

35

3

6

2

1

VCC1

RESET

INT

GND Cd

V1

VCC2

3806 group

VCC

INT

RESET

+

40

VSS

CHAPTER 3

APPENDIX

3.1

Electrical characteristics

3.2

Standard characteristics

3.3 Notes on use

3.4

Countermeasures against noise

3.5 List of registers

3.6

Mask ROM ordering method

3.7 Mark specification form

3.8 Package outline

3.9

List of instruction codes

3.10 Machine instructions

3.11 SFR memory map

3.12 Pin configuration

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-2

3.1 ELECTRICAL CHARACTERISTICS

3.1.1 Absolute maximum ratings

Table 3.1.1 Absolute maximum ratings

Power source voltage

Input voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87,

VREF

Input voltage

______

RESET, XIN

Input voltage CNV SS

Output voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87,

XOUT

Power dissipation

Operating temperature

Storage temperature

VCC

VI

VI

VI

VO

Pd

Topr

Tstg

Symbol Parameter Conditions Ratings

–0.3 to 7.0

–0.3 to VCC +0.3

–0.3 to VCC +0.3

–0.3 to 13

–0.3 to VCC +0.3

500

–20 to 85

–40 to 125

V

V

V

V

V

mW

°C

°C

Unit

Ta = 25 °C

All voltages are based on VSS.

Output transistors are cut off.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-3

Table 3.1.2 Recommended operating conditions (VCC = 3.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

3.1.2 Recommended operating conditions

Note 1: The minimum power source voltage is [V] (f(XIN) = XMHz) on the condition of 2 MHz < f(XIN) < 8 MHz.

2: The total output current is the sum of all the currents flowing through all the applicable por ts. The total average current is an aver-

age value measured over 100 ms. The total peak current is the peak value of all the currents.

3: The peak output current is the peak current flowing in each port.

4: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.

5.5

5.5

VCC

VCC

VCC

VCC

VCC

0.2 VCC

0.2 VCC

0.16 V

CC

0.2 VCC

–80

–80

80

80

–40

–40

40

40

–10

10

–5

5

8

6 V

CC

–16

Power source voltage (f(XIN) 2 MHz) (Note 1)

Power source voltage (f(XIN) = 8 MHz) (Note 1)

Power source voltage

Analog reference voltage (when A-D converter is used)

Analog reference voltage (when D-A converter is used)

Analog power source voltage

Analog input voltage AN0–AN7

“H” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87

“H” input voltage

______

RESET, XIN, CNVSS

“L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87

“L” input voltage

______

RESET

“L” input voltage XIN

“L” input voltage CNVSS

“H” total peak output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 2)

“H” total peak output current P40–P47,P50–P57, P60–P67 (Note 2)

“L” total peak output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 2)

“L” total peak output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 2)

“H” total average output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 2)

“H” total average output current P4 0–P47,P50–P57, P60–P67 (Note 2)

“L” total average output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 2)

“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 2)

“H” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 3)

“L” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)

“H” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 4)

“L” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 4)

Internal clock oscillation frequency (VCC = 4.0 to 5.5 V)

Internal clock oscillation frequency (VCC = 3.0 to 4.0 V)

VCC

VSS

VREF

AVSS

VIA

VIH

VIH

VIL

VIL

VIL

VIL

ΣIOH(peak)

ΣIOH(peak)

ΣIOL(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOH(avg)

ΣIOL(avg)

ΣIOL(avg)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(XIN)

Symbol Parameter Limits

Min.

V

V

V

V

V

V

V

V

V

V

V

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

MHz

Unit

3.0

4.0

2.0

3.0

AVSS

0.8 VCC

0.8 VCC

0

0

0

0

5.0

5.0

0

0

Typ. Max.

X+16

6

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-4

When STP instruction

is executed with clock

stopped, output

transistors isolated.

Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.

2.0

1.0

5.0

5.0

–5.0

–5.0

5.5

13

8

2.0

1

10

“H” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P8

0

–P8

7

(Note 1)

“L” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

,P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

Hysteresis CNTR

0

, CNTR

1

, INT

0

–INT

4

Hysteresis R

X

D, S

CLK1

, S

IN2

, S

CLK2

Hysteresis

______

RESET

“H” input current P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

“H” input current

______

RESET, CNV

SS

“H” input current X

IN

“L” input current P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

“L” input current

______

RESET, CNV

SS

“L” input current X

IN

RAM hold voltage

Symbol Parameter Limits

Min.

V

Unit

Table 3.1.3 Electrical characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

3.1.3 Electrical characteristics

V

CC

–2.0

V

CC

–1.0

0.4

0.5

0.5

4

–4

6.4

4

0.8

1.5

1

0.2

0.1

Typ. Max.

IOH = –10 mA

VCC = 4.0 to 5.5 V

IOH = –1.0 mA

VCC = 3.0 to 5.5 V

IOL = 10 mA

VCC = 4.0 to 5.5 V

IOL = 1.0 mA

VCC = 3.0 to 5.5 V

VI = VCC

VI = VCC

VI = VCC

VI = VSS

VI = VSS

VI = VSS

When clock stopped

f(XIN) = 8 MHz, VCC = 5 V

f(XIN) = 5 MHz, VCC = 5 V

f(XIN) = 2 MHz, VCC = 3 V

When WIT instruction is executed

with f(XIN) = 8 MHz, VCC = 5 V

When WIT instruction is executed

with f(XIN) = 5 MHz, VCC = 5 V

When WIT instruction is executed

with f(XIN) = 2 MHz, VCC = 3 V

Ta = 25 °C

(Note 2)

Ta = 85 °C

(Note 2)

2.0

Test conditions

3.1.4 A-D converter characteristics

VT+ – VT–

VT+ – VT–

VT+ – VT–

IIH

IIH

IIH

IIL

IIL

IIL

VRAM

VOH

VOL

ICC

V

V

V

V

µA

µA

µA

µA

µA

µA

V

mA

µA

Power source current

Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.

8

±2.5

50

200

5.0

Resolution

Absolute accuracy (excluding quantization error)

Conversion time

Ladder resistor

Reference power source input current (Note)

A-D port input current

—

—

tCONV

RLADDER

IVREF

II(AD)

Symbol Parameter Limits

Min. Bits

LSB

tC(φ)

kΩ

µA

µA

Unit

Table 3.1.4 A-D converter characteristics

(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to V CC, Ta = –20 to 85 °C, unless otherwise noted)

50

Typ. Max.

VREF = 5.0 V

Test conditions

±1

35

150

0.5

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-5

Table 3.1.5 D-A converter characteristics

(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to V CC, Ta = –20 to 85 °C, unless otherwise noted)

3.1.5 D-A converter characteristics

Note: Using one D-A conver ter, with the value in the D-A conversion register of the other D-A conver ter being “0016”, and excluding cur-

rents flowing through the A-D resistance ladder.

8

1.0

2.5

3

4

3.2

Resolution

Absolute accuracy V

CC

= 4.0 to 5.5 V

V

CC

= 3.0 to 4.0 V

Setting time

Output resistor

Reference power source input current (Note)

—

—

tsu

RO

IVREF

Symbol Parameter Limits

Min. Bits

%

µs

kΩ

mA

Unit

1

Typ. Max.

Test conditions

2.5

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-6

Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

_____

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

t

su(R

X

D–S

CLK1

)

t

su(S

IN2

–S

CLK2

)

t

h(S

CLK1

–R

X

D)

t

h(S

CLK2

–S

IN2

)

Symbol Parameter Limits

Min. µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.6 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

3.1.6 Timing requirements and Switching characteristics

2

125

50

50

200

80

80

80

80

800

1000

370

400

370

400

220

200

100

200

Typ. Max.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

_____

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

t

su(R

X

D–S

CLK1

)

t

su(S

IN2

–S

CLK2

)

t

h(S

CLK1

–R

X

D)

t

h(S

CLK2

–S

IN2

)

Symbol Parameter Limits

Min. µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.7 Timing requirements (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

2

500/

(3 V

CC

–8)

200/

(3 V

CC

–8)

200/

(3 V

CC

–8)

500

230

230

230

230

2000

2000

950

950

950

950

400

400

200

300

Typ. Max.

Note : When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-7

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

30

30

200

40

30

30

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.8 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

t

c(S

CLK1

)

/2–30

t

c(S

CLK1

)

/2–30

–30

t

c(S

CLK2

)

/2–160

t

c(S

CLK2

)

/2–160

0

10

10

Typ. Max.

twH(SCLK1)

twL(SCLK1)

t

d(S

CLK1

–T

X

D)

t

v(S

CLK1

–T

X

D)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

t

d(S

CLK2

–S

OUT2

)

t

v(S

CLK2

–S

OUT2

)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 3.1.1

Fig. 3.1.2

Fig. 3.1.1

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: Pins XOUT and P70–P77 are excluded.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

50

50

400

50

50

50

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.9 Switching characteristics (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

t

c(S

CLK1

)

/2–50

t

c(S

CLK1

)

/2–50

–30

t

c(S

CLK2

)

/2–240

t

c(S

CLK2

)

/2–240

0

20

20

Typ. Max.

twH(SCLK1)

twL(SCLK1)

t

d(S

CLK1

–T

X

D)

t

v(S

CLK1

–T

X

D)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

t

d(S

CLK2

–S

OUT2

)

t

v(S

CLK2

–S

OUT2

)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 3.1.1

Fig. 3.1.2

Fig. 3.1.1

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: Pins XOUT and P70–P77 are excluded.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-8

_____

Before φ ONW input set up time

_____

After φ ONW input hold time

Before φ data bus set up time

After φ data bus hold time

___ _____

Before RD ONW input set up time

___

_____

Before WR ONW input set up time

___ _____

After RD ONW input hold time

___

_____

After WR ONW input hold time

___

Before RD data bus set up time

___

After RD data bus hold time

____

tsu(ONW–φ)

____

th(φ–ONW)

tsu(DB–φ)

th(φ–DB)

____

__

tsu

(ONW–RD)

_______

tsu

(ONW–WR)

__

____

th(RD–ONW)

___ ____

th(WR–ONW)

__

tsu(DB–RD)

__

th(RD–DB)

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

Unit

–20

–20

60

0

–20

–20

65

0

Typ. Max.

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

After φ AD15–AD8 delay time

After φ AD15–AD8 valid time

After φ AD7–AD0 delay time

After φ AD7–AD0 valid time

SYNC delay time

SYNC valid time

___

___

RD and WR delay time

___

___

RD and WR valid time

After φ data bus delay time

After φ data bus valid time

___

___

RD pulse width, WR pulse width

___

___

RD pulse width, WR pulse width

(When one-wait is valid)

___

After AD15–AD8 RD delay time

___

After AD15–AD8 WR delay time

___

After AD7–AD0 RD delay time

___

After AD7–AD0 WR delay time

___

After RD AD15–AD8 valid time

___

After WR AD15–AD8 valid time

___

After RD AD7–AD0 valid time

___

After WR AD7–AD0 valid time

___

After WR data bus delay time

___

After WR data bus valid time

_________

RESETOUT output delay time (Note 1)

_________

RESETOUT output valid time (Note 1)

40

45

20

10

70

65

200

200

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

tc(XIN)–10

tc(XIN)–10

6

6

3

15

tc(XIN)–10

3tc(XIN)–10

tc(XIN)–35

tc(XIN)–40

0

0

10

0

2tc(XIN)

20

10

25

10

20

10

10

5

20

t

c(X

IN

)

–15

t

c(X

IN

)

–20

5

5

15

Typ. Max.

tc(φ)

twH(φ)

twL(φ)

td(φ–AH)

tv(φ–AH)

td(φ–AL)

tv(φ–AL)

td(φ–SYNC)

tv(φ–SYNC)

___

td(φ–WR)

___

tv(φ–WR)

td(φ–DB)

tv(φ–DB)

__

twL(RD)

___

twL(WR)

__

td(AH–RD)

___

td(AH–WR)

__

td(AL–RD)

___

td(AL–WR)

__

tv(RD–AH)

___

tv(WR–AH)

__

tv(RD–AL)

___

tv(WR–AL)

___

td(WR–DB)

___

tv(WR–DB)

___

_____

t

d

(RESET–RESET

OUT

)

_____

tv(φ–RESET)

Test conditions

Note 1:

__________

The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after

______

the RESET input goes “H”.

Fig. 3.1.1

Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (1)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (1)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-9

_____

Before φ ONW input set up time

_____

After φ ONW input hold time

Before φ data bus set up time

After φ data bus hold time

___ _____

Before RD ONW input set up time

___

_____

Before WR ONW input set up time

___ _____

After RD ONW input hold time

___

_____

After WR ONW input hold time

___

Before RD data bus set up time

___

After RD data bus hold time

____

tsu(ONW–φ)

____

th(φ–ONW)

tsu(DB–φ)

th(φ–DB)

____

__

tsu

(ONW–RD)

_______

tsu

(ONW–WR)

__

____

th(RD–ONW)

___ ____

th(WR–ONW)

__

tsu(DB–RD)

__

th(RD–DB)

Symbol Parameter Limits

Min. ns

ns

ns

ns

Unit

–20

–20

180

0

–20

–20

185

0

Typ. Max.

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

After φ AD15–AD8 delay time

After φ AD15–AD8 valid time

After φ AD7–AD0 delay time

After φ AD7–AD0 valid time

SYNC delay time

SYNC valid time

___

___

RD and WR delay time

___

___

RD and WR valid time

After φ data bus delay time

After φ data bus valid time

___

___

RD pulse width, WR pulse width

___

___

RD pulse width, WR pulse width

(When one-wait is valid)

___

After AD15–AD8 RD delay time

___

After AD15–AD8 WR delay time

___

After AD7–AD0 RD delay time

___

After AD7–AD0 WR delay time

___

After RD AD15–AD8 valid time

___

After WR AD15–AD8 valid time

___

After RD AD7–AD0 valid time

___

After WR AD7–AD0 valid time

___

After WR data bus delay time

___

After WR data bus valid time

_________

RESETOUT output delay time (Note 1)

_________

RESETOUT output valid time (Note 1)

150

150

25

15

200

195

300

300

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

tc(XIN)–20

tc(XIN)–20

10

10

3

15

tc(XIN)–20

3tc(XIN)–20

tc(XIN)–145

tc(XIN)–145

5

5

10

0

2tc(XIN)

15

15

40

20

15

7

10

10

Typ. Max.

tc(φ)

twH(φ)

twL(φ)

td(φ–AH)

tv(φ–AH)

td(φ–AL)

tv(φ–AL)

td(φ–SYNC)

tv(φ–SYNC)

___

td(φ–WR)

___

tv(φ–WR)

td(φ–DB)

tv(φ–DB)

__

twL(RD)

___

twL(WR)

__

td(AH–RD)

___

td(AH–WR)

__

td(AL–RD)

___

td(AL–WR)

__

tv(RD–AH)

___

tv(WR–AH)

__

tv(RD–AL)

___

tv(WR–AL)

___

td(WR–DB)

___

tv(WR–DB)

___

_____

t

d

(RESET–RESET

OUT

)

_____

tv(φ–RESET)

Test conditions

Fig. 3.1.1

Note1:

__________

The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after

______

the RESET input goes “H”.

Table 3.1.12 Timing requirements in memory expansion mode and microprocessor mode (2)

(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Table 3.1.13 Switching characteristics in memory expansion mode and microprocessor mode (2)

(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

ns

ns

ns

ns

ns

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-10

3.1.7 Absolute maximum ratings (Extended operating temperature version)

Table 3.1.14 Absolute maximum ratings (Extended operating temperature version)

Power source voltage

Input voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87,

VREF

Input voltage

______

RESET, XIN

Input voltage CNV SS

Output voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87,

XOUT

Power dissipation

Operating temperature

Storage temperature

VCC

VI

VI

VI

VO

Pd

Topr

Tstg

Symbol Parameter Conditions Ratings

–0.3 to 7.0

–0.3 to VCC +0.3

–0.3 to VCC +0.3

–0.3 to 13

–0.3 to VCC +0.3

500

–40 to 85

–65 to 150

V

V

V

V

V

mW

°C

°C

Unit

Ta = 25 °C

All voltage are based on VSS.

Output transistors are cut off.

Note 1: The total output current is the sum of all the currents flowing through all the applicable por ts. The total average current is an aver-

age value measured over 100 ms. The total peak current is the peak value of all the currents.

2: The peak output current is the peak current flowing in each port.

3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.

5.5

VCC

VCC

VCC

VCC

VCC

0.2 VCC

0.2 VCC

0.16 V

CC

–80

–80

80

80

–40

–40

40

40

–10

10

–5

5

8

Power source voltage

Power source voltage

Analog reference voltage (when A-D converter is used)

Analog reference voltage (when D-A converter is used)

Analog power source voltage

Analog input voltage AN0–AN7

“H” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87

“H” input voltage

______

RESET, XIN, CNVSS

“L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87

“L” input voltage

______

RESET, CNVSS

“L” input voltage XIN

“H” total peak output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“H” total peak output current P40–P47,P50–P57, P60–P67 (Note 1)

“L” total peak output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“L” total peak output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)

“H” total average output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“H” total average output current P4 0–P47,P50–P57, P60–P67 (Note 1)

“L” total average output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)

“H” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 2)

“L” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)

“H” average output current P00–P07, P10–P17, P2 0–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 3)

“L” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)

Internal clock oscillation frequency

VCC

VSS

VREF

AVSS

VIA

VIH

VIH

VIL

VIL

VIL

ΣIOH(peak)

ΣIOH(peak)

ΣIOL(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOH(avg)

ΣIOL(avg)

ΣIOL(avg)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(XIN)

Symbol Parameter Limits

Min. V

V

V

V

V

V

V

V

V

V

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

MHz

Unit

Table 3.1.15 Recommended operating conditions (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, T a = –40 to 85 °C, unless otherwise noted)

3.1.8 Recommended operating conditions (Extended operating temperature version)

4.0

2.0

4.0

AVSS

0.8 VCC

0.8 VCC

0

0

0

5.0

0

0

Typ. Max.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-11

When STP instruction

is executed with clock

stopped, output

transistors isolated.

Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.

2.0

5.0

5.0

–5.0

–5.0

5.5

13

8

1

10

“H” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P8

0

–P8

7

(Note 1)

“L” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

,P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

Hysteresis CNTR

0

, CNTR

1

, INT

0

–INT

4

Hysteresis R

X

D, S

CLK1

, S

IN2

, S

CLK2

Hysteresis

______

RESET

“H” input current P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

“H” input current

______

RESET, CNV

SS

“H” input current X

IN

“L” input current P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

“L” input current

______

RESET, CNV

SS

“L” input current X

IN

RAM hold voltage

Symbol Parameter Limits

Min. Unit

Table 3.1.16 Electrical characteristics (Extended operating temperature version)

(VCC = 4.0 to 5.5 V,

VSS = 0 V,

Ta = –40 to 85 °C, unless otherwise noted)

3.1.9 Electrical characteristics (Extended operating temperature version)

VCC–2.0

0.4

0.5

0.5

4

–4

6.4

4

1.5

1

0.1

Typ. Max.

IOH = –10 mA

IOL = 10 mA

VI = VCC

VI = VCC

VI = VCC

VI = VSS

VI = VSS

VI = VSS

When clock stopped

f(XIN) = 8 MHz

f(XIN) = 5 MHz

When WIT instruction is executed

with f(XIN) = 8 MHz

When WIT instruction is executed

with f(XIN) = 5 MHz Ta = 25 °C

(Note 2)

Ta = 85 °C

(Note 2)

2.0

Test conditions

Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.

8

±2.5

50

200

5.0

Resolution

Absolute accuracy (excluding quantization error)

Conversion time

Ladder resistor

Reference power source input current (Note)

A-D port input current

—

—

tCONV

RLADDER

IVREF

II(AD)

Symbol Parameter Limits

Min. Bits

LSB

tC(φ)

kΩ

µA

µA

Unit

50

Typ. Max.

VREF = 5.0 V

Test conditions

±1

35

150

0.5

3.1.10 A-D converter characteristics (Extended operating temperature version)

VT+ – VT–

VT+ – VT–

VT+ – VT–

IIH

IIH

IIH

IIL

IIL

IIL

VRAM

VOH

VOL

ICC

V

V

V

V

V

µA

µA

µA

µA

µA

µA

V

Power source current

mA

µA

Table 3.1.17

A-D converter characteristics

(Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted)

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-12

Note: Using one D-A conver ter, with the value in the D-A conversion register of the other D-A conver ter being “0016”, and excluding cur-

rents flowing through the A-D resistance ladder.

8

1.0

3

4

3.2

Resolution

Absolute accuracy

Setting time

Output resistor

Reference power source input current (Note)

—

—

tsu

RO

IVREF

Symbol Parameter Limits

Min. Bits

%

µs

kΩ

mA

Unit

Table 3.1.18

D-A

converter characteristics

(Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted)

1

Typ. Max.

Test conditions

2.5

3.1.11 D-A converter characteristics (Extended operating temperature version)

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-13

3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)

Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

_____

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

t

su(R

X

D–S

CLK1

)

t

su(S

IN2

–S

CLK2

)

t

h(S

CLK1

–R

X

D)

t

h(S

CLK2

–S

IN2

)

Symbol Parameter Limits

Min. µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

2

125

50

50

200

80

80

80

80

800

1000

370

400

370

400

220

200

100

200

Typ. Max.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rise time

Serial I/O1 clock output fall time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output fall time

CMOS output rise time (Note 2)

CMOS output fall time (Note 2)

140

30

30

200

40

30

30

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

t

c(S

CLK1

)

/2–30

t

c(S

CLK1

)

/2–30

–30

t

c(S

CLK2

)

/2–160

t

c(S

CLK2

)

/2–160

0

10

10

Typ. Max.

twH(SCLK1)

twL(SCLK1)

t

d(S

CLK1

–T

X

D)

t

v(S

CLK1

–T

X

D)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

t

d(S

CLK2

–S

OUT2

)

t

v(S

CLK2

–S

OUT2

)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 3.1.1

Fig. 3.1.2

Fig. 3.1.1

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: Pins XOUT pin and P70–77 are excluded.

Table 3.1.19

Timing requirements (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

Table 3.1.20

Switching characteristics (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-14

Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode

(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode

(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

_____

Before φ ONW input set up time

_____

After φ ONW input hold time

Before φ data bus set up time

After φ data bus hold time

___ _____

Before RD ONW input set up time

___

_____

Before WR ONW input set up time

___ _____

After RD ONW input hold time

___

_____

After WR ONW input hold time

___

Before RD data bus set up time

___

After RD data bus hold time

____

tsu(ONW–φ)

____

th(φ–ONW)

tsu(DB–φ)

th(φ–DB)

____

__

tsu

(ONW–RD)

_______

tsu

(ONW–WR)

__

____

th(RD–ONW)

___ ____

th(WR–ONW)

__

tsu(DB–RD)

__

th(RD–DB)

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

Unit

–20

–20

60

0

–20

–20

65

0

Typ. Max.

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

After φ AD15–AD8 delay time

After φ AD15–AD8 valid time

After φ AD7–AD0 delay time

After φ AD7–AD0 valid time

SYNC delay time

SYNC valid time

___

___

RD and WR delay time

___

___

RD and WR valid time

After φ data bus delay time

After φ data bus valid time

___

___

RD pulse width, WR pulse width

___

___

RD pulse width, WR pulse width

(When one-wait is valid)

___

After AD15–AD8 RD delay time

___

After AD15–AD8 WR delay time

___

After AD7–AD0 RD delay time

___

After AD7–AD0 WR delay time

___

After RD AD15–AD8 valid time

___

After WR AD15–AD8 valid time

___

After RD AD7–AD0 valid time

___

After WR AD7–AD0 valid time

___

After WR data bus delay time

___

After WR data bus valid time

_________

RESETOUT output delay time (Note 1)

_________

RESETOUT output valid time (Note 1)

40

45

20

10

70

65

200

200

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

tc(XIN)–10

tc(XIN)–10

6

6

3

15

tc(XIN)–10

3tc(XIN)–10

tc(XIN)–35

tc(XIN)–40

0

0

10

0

2tc(XIN)

20

10

25

10

20

10

10

5

20

t

c(X

IN

)

–15

t

c(X

IN

)

–20

5

5

15

Typ. Max.

tc(φ)

twH(φ)

twL(φ)

td(φ–AH)

tv(φ–AH)

td(φ–AL)

tv(φ–AL)

td(φ–SYNC)

tv(φ–SYNC)

___

td(φ–WR)

___

tv(φ–WR)

td(φ–DB)

tv(φ–DB)

__

twL(RD)

twL(WR)

__

td(AH–RD)

___

td(AH–WR)

__

td(AL–RD)

___

td(AL–WR)

__

tv(RD–AH)

___

tv(WR–AH)

__

tv(RD–AL)

___

tv(WR–AL)

___

td(WR–DB)

___

tv(WR–DB)

___

_____

t

d

(RESET–RESET

OUT

)

_____

tv(φ–RESET)

Test conditions

Note 1:

_________

The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after

______

the RESET input goes “H”.

Fig. 3.1.1

___

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-15

Power source voltage

Input voltage P0 0–P07, P1 0–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87,

VREF, XIN

Input voltage

______

RESET

Input voltage CNV SS

Output voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87,

XOUT

Power dissipation

Operating temperature

Storage temperature

3.1.13 Absolute maximum ratings (High-speed version)

Table 3.1.23 Absolute maximum ratings (High-speed version)

VCC

VI

VI

VI

VO

Pd

Topr

Tstg

Symbol Parameter Conditions Ratings

–0.3 to 7.0

–0.3 to VCC +0.3

–0.3 to 7.0

–0.3 to 7.0

–0.3 to 13

–0.3 to VCC +0.3

500

–20 to 85

–40 to 125

V

V

V

V

V

mW

°C

°C

Unit

Ta = 25 °C

All voltages are based on VSS.

Output transistors are cut off.

Mask ROM version

PROM version

Table 3.1.24 Recommended operating conditions (High-speed version)(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

3.1.14 Recommended operating conditions (High-speed version)

5.5

5.5

VCC

VCC

VCC

VCC

0.2 VCC

0.16 V

CC

–80

–80

80

80

–40

–40

40

40

–10

10

–5

5

10

4.5V

CC

–8

Power source voltage (f(XIN) 4.15 MHz)

Power source voltage (f(XIN) = 10 MHz)

Power source voltage

Analog reference voltage (when A-D converter is used)

Analog reference voltage (when D-A converter is used)

Analog power source voltage

Analog input voltage AN0–AN7

“H” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

______

P50–P57, P60–P67, P70–P77, P80–P87, RESET, XIN,

CNVSS

“L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

______

P5

0

–P5

7

, P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

,

RESET, CNV

SS

“L” input voltage XIN

“H” total peak output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“H” total peak output current P40–P47,P50–P57, P60–P67 (Note 1)

“L” total peak output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“L” total peak output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)

“H” total average output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“H” total average output current P4 0–P47,P50–P57, P60–P67 (Note 1)

“L” total average output current

P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

(Note 1)

“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)

“H” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 2)

“L” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)

“H” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 3)

“L” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)

Internal clock oscillation frequency (4.0 V VCC 5.5 V)

Internal clock oscillation frequency (2.7 V VCC 4.0 V)

VCC

VSS

VREF

AVSS

VIA

VIH

VIL

VIL

ΣIOH(peak)

ΣIOH(peak)

ΣIOL(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOH(avg)

ΣIOL(avg)

ΣIOL(avg)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(XIN)

Symbol Parameter Limits

Min.

V

V

V

V

V

V

V

V

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

MHz

Unit

2.7

4.0

2.0

2.7

AVSS

0.8 VCC

0

0

5.0

5.0

0

0

Typ. Max.

Note 1: The total output current is the sum of all the currents flowing through all the applicable por ts. The total average current is an aver-

age value measured over 100 ms. The total peak current is the peak value of all the currents.

2: The peak output current is the peak current flowing in each port.

3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-16

When STP instruction

is executed with clock

stopped, output

transistors isolated.

Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.

2.0

1.0

5.0

5.0

–5.0

5.5

16

2

1

10

“H” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P8

0

–P8

7

(Note 1)

“L” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

,P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

Hysteresis CNTR

0

, CNTR

1

, INT

0

–INT

4

Hysteresis R

X

D, S

CLK1

, S

IN2

, S

CLK2

Hysteresis

______

RESET

“H” input current P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7

“H” input current

______

RESET, CNV

SS

“H” input current X

IN

“L” input current P0

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

,

P3

0

–P3

7

, P4

0

–P4

7

, P5

0

–P5

7

,

P6

0

–P6

7

, P7

0

–P7

7

, P8

0

–P8

7,

______

RESET, CNV

SS

“L” input current X

IN

RAM hold voltage

Symbol Parameter Limits

Min.

V

Unit

Table 3.1.25 Electrical characteristics (High-speed version) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

3.1.15 Electrical characteristics (High-speed version)

V

CC

–2.0

V

CC

–1.0

0.4

0.5

0.5

4

–4

8

1.3

2

0.3

0.1

Typ. Max.

IOH = –10 mA

VCC = 4.0 to 5.5 V

IOH = –1.0 mA

VCC = 2.7 to 5.5 V

IOL = 10 mA

VCC = 4.0 to 5.5 V

IOL = 1.0 mA

VCC = 2.7 to 5.5 V

VI = VCC

VI = VCC

VI = VCC

VI = VSS

VI = VSS

With clock stopped

f(XIN) = 10 MHz, VCC = 5 V

f(XIN) = 4 MHz, VCC = 2.7 V

When WIT instruction is executed

with f(XIN) = 10 MHz, VCC = 5 V

When WIT instruction is executed

with f(XIN) = 4 MHz, VCC = 2.7 V

Ta = 25 °C

(Note 2)

Ta = 85 °C

(Note 2)

2.0

Test conditions

3.1.16 A-D converter characteristics (High-speed version)

VT+ – VT–

VT+ – VT–

VT+ – VT–

IIH

IIH

IIH

IIL

IIL

VRAM

VOH

VOL

ICC

V

V

V

V

µA

µA

µA

µA

µA

V

Power source current

Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.

8

±2.5

50

200

5.0

Resolution

Absolute accuracy (excluding quantization error)

Conversion time

Ladder resistor

Reference power source input current (Note)

A-D port input current

—

—

tCONV

RLADDER

IVREF

II(AD)

Symbol Parameter Limits

Min. Bits

LSB

tC(φ)

kΩ

µA

µA

Unit

Table 3.1.26 A-D converter characteristics (High-speed version)

(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)

50

Typ. Max.

VREF = 5.0 V

Test conditions

±1

35

150

0.5

mA

µA

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-17

Table 3.1.27

D-A

converter characteristics

(High-speed version)

(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.7 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)

3.1.17 D-A converter characteristics (High-speed version)

Note: Using one D-A conver ter, with the value in the D-A conversion register of the other D-A conver ter being “0016”, and excluding cur-

rents flowing through the A-D resistance ladder.

8

1.0

2.5

3

4

3.2

Resolution

Absolute accuracy V

CC

= 4.0 to 5.5 V

V

CC

= 2.7 to 5.5 V

Setting time

Output resistor

Reference power source input current (Note)

—

—

tsu

RO

IVREF

Symbol Parameter Limits

Min. Bits

%

µs

kΩ

mA

Unit

1

Typ. Max.

Test conditions

2.5

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-18

Note: When f(XIN) = 8 MHz and bit 6 of address 001A 16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A 16 is “0”.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

_____

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

t

su(R

X

D–S

CLK1

)

t

su(S

IN2

–S

CLK2

)

t

h(S

CLK1

–R

X

D)

t

h(S

CLK2

–S

IN2

)

Symbol Parameter Limits

Min. µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.28 Timing requirements (1) (High-speed version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

3.1.18 Timing requirements and Switching characteristics (High-speed version)

2

100

40

40

200

80

80

80

80

800

1000

370

400

370

400

220

200

100

200

Typ. Max.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

_____

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

t

su(R

X

D–S

CLK1

)

t

su(S

IN2

–S

CLK2

)

t

h(S

CLK1

–R

X

D)

t

h(S

CLK2

–S

IN2

)

Symbol Parameter Limits

Min. µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.29 Timing requirements (2) (High-speed version) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

2

1000/

(4.5 V

CC

–8)

400/

(4.5 V

CC

–8)

400/

(4.5 V

CC

–8)

500

230

230

230

230

2000

2000

950

950

950

950

400

400

200

300

Typ. Max.

Note: When f(XIN) = 2 MHz and bit 6 of address 001A 16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A 16 is “0”.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-19

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

30

30

200

30

30

30

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.30 Switching characteristics (1) (High-speed version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

t

c(S

CLK1

)

/2–30

t

c(S

CLK1

)

/2–30

–30

t

c(S

CLK2

)

/2–160

t

c(S

CLK2

)

/2–160

0

10

10

Typ. Max.

twH(SCLK1)

twL(SCLK1)

t

d(S

CLK1

–T

X

D)

t

v(S

CLK1

–T

X

D)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

t

d(S

CLK2

–S

OUT2

)

t

v(S

CLK2

–S

OUT2

)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 3.1.1

Fig. 3.1.2

Fig. 3.1.1

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT pin is excluded.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

50

50

400

50

50

50

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Table 3.1.31 Switching characteristics (2) (High-speed version)

(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

t

c(S

CLK1

)

/2–50

t

c(S

CLK1

)

/2–50

–30

t

c(S

CLK2

)

/2–240

t

c(S

CLK2

)

/2–240

0

20

20

Typ. Max.

twH(SCLK1)

twL(SCLK1)

t

d(S

CLK1

–T

X

D)

t

v(S

CLK1

–T

X

D)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

t

d(S

CLK2

–S

OUT2

)

t

v(S

CLK2

–S

OUT2

)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 3.1.1

Fig. 3.1.2

Fig. 3.1.1

Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT pin is excluded.

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-20

_____

Before φ ONW input set up time

_____

After φ ONW input hold time

Before φ data bus set up time

After φ data bus hold time

___ _____

Before RD ONW input set up time

___

_____

Before WR ONW input set up time

___ _____

After RD ONW input hold time

___

_____

After WR ONW input hold time

___

Before RD data bus set up time

___

After RD data bus hold time

____

tsu(ONW–φ)

____

th(φ–ONW)

tsu(DB–φ)

th(φ–DB)

____

__

tsu

(ONW–RD)

_______

tsu

(ONW–WR)

__

____

th(RD–ONW)

___ ____

th(WR–ONW)

__

tsu(DB–RD)

__

th(RD–DB)

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

Unit

–20

–20

50

0

–20

–20

50

0

Typ. Max.

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

After φ AD15–AD8 delay time

After φ AD15–AD8 valid time

After φ AD7–AD0 delay time

After φ AD7–AD0 valid time

SYNC delay time

SYNC valid time

After φ data bus delay time

After φ data bus valid time

___

___

RD pulse width, WR pulse width

___

___

RD pulse width, WR pulse width

(When one-wait is valid)

___

After AD15–AD8 RD delay time

___

After AD15–AD8 WR delay time

___

After AD7–AD0 RD delay time

___

After AD7–AD0 WR delay time

___

After RD AD15–AD8 valid time

___

After WR AD15–AD8 valid time

___

After RD AD7–AD0 valid time

___

After WR AD7–AD0 valid time

___

After WR data bus delay time

___

After WR data bus valid time

_________

RESETOUT output delay time (Note 1)

_________

RESETOUT output valid time (Note 1)

35

40

30

30

200

100

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

tc(XIN)–10

tc(XIN)–10

2

2

10

tc(XIN)–10

3tc(XIN)–10

tc(XIN)–35

tc(XIN)–40

2

2

10

0

2tc(XIN)

16

5

20

5

16

5

15

t

c(X

IN

)

–16

t

c(X

IN

)

–20

5

5

15

Typ. Max.

tc(φ)

twH(φ)

twL(φ)

td(φ–AH)

tv(φ–AH)

td(φ–AL)

tv(φ–AL)

td(φ–SYNC)

tv(φ–SYNC)

td(φ–DB)

tv(φ–DB)

__

twL(RD)

___

twL(WR)

__

td(AH–RD)

___

td(AH–WR)

__

td(AL–RD)

___

td(AL–WR)

__

tv(RD–AH)

___

tv(WR–AH)

__

tv(RD–AL)

___

tv(WR–AL)

___

td(WR–DB)

___

tv(WR–DB)

___

_____

t

d

(RESET–RESET

OUT

)

_____

tv(φ–RESET)

Test conditions

Note 1:

_________

The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after

______

the RESET input goes “H”.

Fig. 3.1.1

Table 3.1.32 Timing requirements in memory expansion mode and microprocessor mode (1) (High-speed version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Table 3.1.33 Switching characteristics in memory expansion mode and microprocessor mode (1) (High-speed version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

25

25

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-21

_____

Before φ ONW input set up time

_____

After φ ONW input hold time

Before φ data bus set up time

After φ data bus hold time

___ _____

Before RD ONW input set up time

___

_____

Before WR ONW input set up time

___ _____

After RD ONW input hold time

___

_____

After WR ONW input hold time

___

Before RD data bus set up time

___

After RD data bus hold time

____

tsu(ONW–φ)

____

th(φ–ONW)

tsu(DB–φ)

th(φ–DB)

____

__

tsu

(ONW–RD)

_______

tsu

(ONW–WR)

__

____

th(RD–ONW)

___ ____

th(WR–ONW)

__

tsu(DB–RD)

__

th(RD–DB)

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

Unit

–20

–20

120

0

–20

–20

120

0

Typ. Max.

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

AD15–AD8 delay time

AD15–AD8 valid time

AD7–AD0 delay time

AD7–AD0 valid time

SYNC delay time

SYNC valid time

Data bus delay time

Data bus valid time

___

___

RD pulse width, WR pulse width

___

___

RD pulse width, WR pulse width

(When one-wait is valid)

___

After AD15–AD8 RD delay time

___

After AD15–AD8 WR delay time

___

After AD7–AD0 RD delay time

___

After AD7–AD0 WR delay time

___

After RD AD15–AD8 valid time

___

After WR AD15–AD8 valid time

___

After RD AD7–AD0 valid time

___

After WR AD7–AD0 valid time

___

After WR data bus delay time

___

After WR data bus valid time

_________

RESETOUT output delay time (Note 1)

_________

RESETOUT output valid time (Note 1)

100

100

80

80

300

150

Symbol Parameter Limits

Min. ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

tc(XIN)–20

tc(XIN)–20

5

5

10

tc(X

IN

)–20

3tc(X

IN

)–20

tc(X

IN

)–100

tc(XIN)–100

5

5

10

0

2tc(XIN)

40

10

50

10

40

10

30

t

c(X

IN

)

–40

t

c(X

IN

)

–50

10

10

30

Typ. Max.

tc(φ)

twH(φ)

twL(φ)

td(φ–AH)

tv(φ–AH)

td(φ–AL)

tv(φ–AL)

td(φ–SYNC)

tv(φ–SYNC)

td(φ–DB)

tv(φ–DB)

__

twL(RD)

___

twL(WR)

__

td(AH–RD)

___

td(AH–WR)

__

td(AL–RD)

___

td(AL–WR)

__

tv(RD–AH)

___

tv(WR–AH)

__

tv(RD–AL)

___

tv(WR–AL)

___

td(WR–DB)

___

tv(WR–DB)

___

_____

t

d

(RESET–RESET

OUT

)

_____

tv(φ–RESET)

Test conditions

Note 1:

_________

The RESETOUT output goes “H” in sync with the r ise of the φ clock that is anywhere between about 8 cycle and 13 cycles after

______

the RESET input goes “H”.

Fig. 3.1.1

Table 3.1.34 Timing requirements in memory expansion mode and microprocessor mode (2) (High-speed version)

(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Table 3.1.35 Switching characteristics in memory expansion mode and microprocessor mode (2) (High-speed version)

(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

60

60

Fig. 3.1.1 Circuit for measuring output switching

characteristics (1) Fig. 3.1.2 Circuit for measuring output switching

characteristics (2)

Measurement output pin

100pF

CMOS output

100pF

N-channel open-drain output

1kΩ

Measurement output pin

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-22

3.1.19 Timing diagram

Timing Diagram

Fig. 3.1.3 Timing diagram (in single-chip mode)

0.2 V

CC

t

WL(INT)

0.8 V

CC

t

WH(INT)

0.2 V

CC

0.2 V

CC

0.8 V

CC

0.8 V

CC

0.2 V

CC

t

WL(X

IN

)

0.8 V

CC

t

WH(X

IN)

t

C(X

IN

)

X

IN

0.2 V

CC

0.8 V

CC

t

W(RESET)

RESET

t

f

t

r

0.2 V

CC

t

WL(CNTR)

0.8 V

CC

t

WH(CNTR)

t

C(CNTR)

t

d(S

CLK1

-T

X

D)

,t

d(S

CLK2-

S

OUT2

)

t

v(S

CLK1

-T

X

D),

t

v(S

CLK2-

S

OUT2

)

t

C(S

CLK1

),

t

C(S

CLK2

)

t

WL(S

CLK1

),

t

WL(S

CLK2

)

t

WH(S

CLK1

),

t

WH(S

CLK2

)

th

(S

CLK1-

R

X

D),

t

h

(S

CLK2-

S

IN2

)

t

su(R

X

D

-

S

CLK1

),

t

su(S

IN2-

S

CLK2

)

T

X

D

S

OUT2

R

X

D

S

IN2

S

CLK1

S

CLK2

INT

0–

INT

4

CNTR

0

, CNTR

1

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-23

Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1)

Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (1)

Timing Diagram in Microprocessor Mode

t

WL(φ)

t

WH(φ)

t

C(φ)

φ

t

d(φ-AH)

t

d(φ-AL)

t

d(φ-SYNC)

t

v(φ-AH)

t

v(φ-AL)

t

v(φ-SYNC)

t

d(φ-WR)

t

v(φ-WR)

t

SU(ONW-φ)

t

h(φ-ONW)

t

SU(DB-φ)

t

h(φ-DB)

t

d(φ-DB)

t

v(φ-DB)

t

d(RESET- RESET

OUT

)

AD

15

–AD

8

AD

7

–AD

0

SYNC

RD,WR

ONW

DB

0

–DB

7

DB

0

–DB

7

RESET

φ

RESET

OUT

t

v(φ- RESET

OUT

)

0.5 V

CC

0.8 V

CC

0.2 V

CC

(At CPU reading)

(At CPU writing)

0.5 V

CC

0.5 V

CC

0.8 V

CC

0.2 V

CC

0.8 V

CC

0.2 V

CC

0.5 V

CC

0.5 V

CC

0.5 V

CC

0.5 V

CC

0.5 V

CC

3806 GROUP USER’S MANUAL

APPENDIX

3.1 Electrical characteristics

3-24

Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2)

Fig. 3.1.5 Timing diagram (in memory expansion mode and microprocessor mode) (2)

0.5 V

CC

RD,WR

0.5 V

CC

AD15–AD8

t

d(AH-WR)

t

v(WR-AH)

0.5 V

CC

AD7–AD0

t

d(AL-WR)

t

v(WR-AL)

0.8 V

CC

0.2 V

CC

DB

0

–DB

7

0.5 V

CC

RD

t

SU(DB-RD)

t

h(RD-DB)

0.5 V

CC

DB

0

–DB

7

0.5 V

CC

WR

t

d(WR-DB)

t

v(WR-DB)

t

h(WR-ONW)

ONW

t

su(ONW-WR)

t

v(RD-AH)

t

d(AH-RD)

t

d(AL-RD)

t

v(RD-AL)

t

h(RD-ONW)

t

su(ONW-RD)

t

WL(RD)

t

WL(WR)

(At CPU reading)

(At CPU writing)

t

WL(RD)

t

WL(WR)

0.8 V

CC

0.2 V

CC

APPENDIX

3.2 Standard characteristics

3-25

3806 GROUP USER’S MANUAL

3.2 Standard characteristics

3.2.1 Power source current characteristic examples

Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples.

Fig. 3.2.1 Power source current characteristic example

[Measuring condition : 25 °C, A-D conversion stopped]

Fig. 3.2.2 Power source current characteristic example (in wait mode)

[Measuring condition : 25 °C, A-D conversion stopped]

Vcc = 5.5 V, Ta = 25 °C

Vcc = 4.0 V, Ta = 25 °C

0

0

8

4

3

2

1

84321 567

5

6

7

910

9

Vcc = 2.7 V, Ta = 25 °C

Frequency f(X

IN

) (MHz)

Power source current

(mA)

Rectangular waveform

Vcc = 5.5 V, Ta = 25 °C

Vcc = 4.0 V, Ta = 25 °C

0

0Frequency f(XIN) (MHz)

Power source current

(mA)

Rectangular waveform

8

4

3

2

1

84321 567

5

6

7

910

9

Vcc = 2.7V, Ta = 25 °C

APPENDIX

3.2 Standard characteristics

3-26 3806 GROUP USER’S MANUAL

3.2.2 Port standard characteristic examples

Figures 3.2.3, Figure 3.2.4, Figure 3.2.5 and Figure 3.2.6 show port standard characteristic examples.

Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1)

[Port P00 IOH–VOH characteristic (P-channel drive)]

Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2)

[Port P00 IOH–VOH characteristic (P-channel drive)]

(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P8)

(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P8)

0V

OH

(V)

I

OH

(mA)

0.5

01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

–5

–10

–20

–25

–30

–35

–40

–45

–50

5.5

–15

Vcc = 5.0 V

Ta = 85 °C

Vcc

=

4.0 V

Ta

=

85 °C

Vcc

=

2.7 V

Ta = 85 °C

0 0.5

01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

–5

–10

–20

–25

–30

–35

–40

–45

–50

–15

V

OH

(V)

I

OH

(mA)

Vcc = 5.0 V

Ta = 25 °C

Vcc = 4.0 V

Ta = 25 °C

Vcc = 2.7 V

Ta = 25 °C

APPENDIX

3.2 Standard characteristics

3-27

3806 GROUP USER’S MANUAL

Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1)

[Port P00 IOL–VOL characteristic (N-channel drive)]

(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7, P8)

(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7, P8)

Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2)

[Port P00 IOL–VOL characteristic (N-channel drive)]

0 0.5

01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

5

10

15

20

25

30

35

40

45

50

Vcc = 4.0 V

Ta = 85 °C

Vcc = 5.0 V

Ta = 85 °C

Vcc = 2.7 V

Ta = 85 °C

I

OL

(mA)

V

OL

(V)

V

OL

(V)

I

OL

(mA)

00.5

01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

5

10

15

20

25

30

35

40

45

50

Vcc

=

5.0 V

Ta

=

25 °C

Vcc

=

4.0 V

Ta

=

25 °C

Vcc

=

2.7 V

Ta

=

25 °C

APPENDIX

3.2 Standard characteristics

3-28 3806 GROUP USER’S MANUAL

3.2.3 A-D conversion standard characteristics

Figure 3.2.7 shows the A-D conversion standard characteristics.

The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the

ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 =

10 mV, but the measured value is 0 mV. Accordingly, the measured point of conversion is represented as

“10 – 0 = 10 mV.”

The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For

example, the measured width of the input voltage for output code 13 is 22 mV, so the differential nonlinear

error is represented as “22 – 20 = 2 mV” (0.1 LSB).

Fig. 3.2.7 A-D conversion standard characteristics

A-D CONVERTER STEP WIDTH MEASUREMENT

Measured when a power source voltage is stable in the single-chip mode and the high-speed mode

0

+1LSB

–1LSB

ERROR [mV]

STEP No.

0

8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128

128

+1LSB

–1LSB

1LSB WIDTH [mV]

ERROR [mV]

STEP No.

0

10

136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256

1LSB WIDTH [mV]

20

10

30

– 10

– 20

– 30

20

10

30

0

20

30

– 10

– 20

– 30

20

10

30

0

1LSB WIDTH

V

CC

= 5.12 [V] , V

REF

= 5.12 [V]

X

IN

= 4.80 [MH

Z

] , ANALOG Port P6

0

Temp. = 25deg.

Absolute precision error

APPENDIX

3.2 Standard characteristics

3-29

3806 GROUP USER’S MANUAL

3.2.4 D-A conversion standard characteristics

Figure 3.2.8 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates

the absolute precision error. In this case, it represents the difference between the ideal analog output value

for an input code and the measured value.

The upper-side line on the graph indicates the change width of output analog value to a one-bit change

of input code.

Fig. 3.2.8 D-A conversion standard characteristics

D-A CONVERTER STEP WIDTH MEASUREMENT

Measured when a power source voltage is stable in the single-chip mode and the high-speed mode

0

+1LSB

–1LSB

ERROR [mV]

STEP No.

0

8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128

128

+1LSB

–1LSB

ERROR [mV]

STEP No.

0

10

136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256

1LSB WIDTH [mV]

V

CC

= 5.12 [V] , V

REF

= 5.12 [V]

X

IN

= 4.80 [MH

Z

] , ANALOG OUTPUT DA

Temp. = 25deg.

20

10

30

– 10

– 20

– 30

20

10

30

0

20

30

– 10

– 20

– 30

20

30

Absolute precision error

1LSB WIDTH

1LSB WIDTH [mV]

10

0

3806 GROUP USER’S MANUAL

3-30

APPENDIX

3.3 Notes on use

(1) Sequence for switching an external interrupt

detection edge Clear an interrupt enable bit to “0” (interrupt disabled)

Switch the detection edge

Clear an interrupt request bit to “0” (no interrupt requ-

est issued)

Set the interrupt enable bit to “1” ( interrupt enabled )

3.3 Notes on use

3.3.1 Notes on interrupts

When the external interrupt detection edge must be

switched, make sure the following sequence.

Reason

The interrupt circuit recognizes the switching of the

detection edge as the change of external input

signals. This may cause an unnecessary interrupt.

(2) Bit 7 of the interrupt control register 2

Fix the bit 7 of the interrupt control register 2

(Address:003F16) to “0”.

Figure 3.3.1 shows the structure of the interrupt

control register 2.

Fig. 3.3.1 Structure of interrupt control register 2

3.3.2 Notes on the serial I/O1

(1) Stop of data transmission

As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear

the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O1 disabled)in

the following cases :

● when stopping data transmission during transmitting data in the clock synchronous serial I/O mode

● when stopping data transmission during transmitting data in the UART mode

● when stopping only data transmission during transmitting and receiving data in the UART mode

Reason

Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit

is cleared to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1,

______

and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer

register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial

I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and ti may cause

an operation failure to a microcomputer.

(2) Stop of data reception

As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear

the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the

following case :

● when stopping data reception during receiving data in the clock synchronous serial I/O mode

Clear the receive enable bit to “0” (receive disabled) in the following cases :

● when stopping data reception during receiving data in the UART mode

● when stopping only data reception during transmitting and receiving data in the UART mode

b7 b0 Interrupt control register 2

Address 003F16

Interrupt enable bits

Not used

Fix this bit to “0”

0

3806 GROUP USER’S MANUAL 3-31

APPENDIX

3.3 Notes on use

(3) Stop of data transmission and reception in a clock synchronous serial I/O mode

As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear

both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the

following case:

● when stopping data transmission and reception during transmitting and receiving data in the clock synchronous

mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data

transmission and reception cannot be stopped.)

Reason

In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of

transmission and reception is disabled, a bit error occurs because transmission and reception cannot be

synchronized.

In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the

transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the

transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O1 disabled) (refer to (1)).

_____

(4) The SRDY pin on a receiving side

_____

When signals are output from the SRDY pin on the reception side by using an external clock in the clock

_____

synchronous serial I/O mode, set all of the receive enable bit, the S RDY output enable bit, and the transmit enable

bit to “1” (transmit enabled).

(5) Stop of data reception in a clock synchronous

serial I/O mode

Set the serial I/O1 control register again after the

transmission and the reception circuits are reset by

clearing both the transmit enable bit and the receive

enable bit to “0.”

Clear both the transmit

enable bit (TE) and the

receive enable bit (RE) to “0”

Set the bits 0 to 3 and bit 6 of

the serial I/O1 control

register

Set both the transmit enable

bit (TE) and the receive

enable bit (RE) to “1”

Can be set with the

LDM instruction at

the same time

(6) Control of data transmission using the transmit shift completion flag

The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking

the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data

transmission, note this delay.

(7) Control of data transmission using an external clock

When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1”

at “H” level of the SCLK input signal. Also, write data to the transmit buffer register at “H” level of the SCLK input

signal.

3.3.3 Notes on the A-D converter

(1) Input of signals from signal source with high impedance to an analog input pin

Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor

of 0.01

µ

F to 1

µ

F. Further, maek sure to check the operation of application products on the user side.

Reason

The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal

source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may

cause the A-D conversion precision to be worse.

3806 GROUP USER’S MANUAL

3-32

APPENDIX

3.3 Notes on use

(2) AVSS pin

Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit.

(3) A clock frequency during an A-D conversion

The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is

too low. Thus, make sure the following during an A-D conversion.

● f(XIN) is 500 kHz or more .

(When the ONW pin is "L", f(XIN) is 1 MHz or more.)

● Do not execute the STP instruction and WIT instruction.

3.3.4 Notes on the RESET pin

When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and

the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make

sure the following :

●Make the length of the wiring which is connected to a capacitor the shortest possible.

●Make sure to check the operation of application products on the user side.

Reason

If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may

malfunction.

3.3.5 Notes on input and output pins

(1) Fix of a port input level in stand-by state

Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially

for the I/O ports of the N-channel open-drain.

Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.

When determining a resistance value, make sure the following:

●External circuit

●Variation of output levels during the ordinary operation

* stand-by state : the stop mode by executing the STP instruction

the wait mode by executing the WIT instruction

Reason

Even when setting as an output port with its direction register, in the following state :

●N-channel......when the content of the port latch is “1”

the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the

level becomes “undefined” depending on external circuits.

Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input

levels of an input and an I/O port are “undefined.” This may cause power source current.

(2) Modify of the content of I/O port latch

When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the

unspecified bit may be changed.

Reason

The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit.

Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed

to all bits of the port latch.

●As for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit

managing.

●As for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit

managing.

3806 GROUP USER’S MANUAL 3-33

APPENDIX

3.3 Notes on use

Make sure the following :

●Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.

●Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction,

its value may be changed in case where content of the pin differs from a content of the port latch.

* bit managing instructions : SEB and CLB instruction

(3) The AVSS pin when not using the A-D converter

When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows :

● AVSS : Connect to the VSS pin

Reason

If the AVSS pin is opened, the microcomputer may malfunction by effect of noise or others.

3.3.6 Notes on memory expansion mode and microprocessor mode

(1) Writing data to the port latch of port P3

In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the

LDM or STA instruction for writing data to the port latch (address 000616) of port P3.

When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write

enabled memory at address 000616.

Reason

In the memory expansion or microprocessor mode, address 000616 is allocated in the external area.

Accordingly,

● Data is read from the external memory.

● Data is written to both the port latch of the port P3 and the external memory.

Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and

modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled

memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written

to the port latch of the port P3. The port latch data of port P3 becomes “undefined.”

(2) Overlap of an internal memory and an external memory

When the internal and the external memory are overlapped in the memory expansion mode, the internal memory

is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed :

● When reading data

Only the data in the internal memory is read into the CPU and the data in the external memory is not read into

the CPU. However, as the read signal and address are still valid, the external memory data of the

corresponding address is output to the external data bus.

● When writing data

Data is written in both the internal and the external memory.

3806 GROUP USER’S MANUAL

3-34

APPENDIX

3.3 Notes on use

3.3.7 Notes on built-in PROM

(1) Programming adapter

To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose

PROM programmer as shown in Table 3.3.1.

Table 3.3.1 Programming adapter PROM mode

256K

1M

(2) Write and read

In PROM mode, operation is the same as that of the M5M27C256AK and the M5M27C101, but programming

conditions of PROM programmer are not set automatically because there are no internal device ID codes.

Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as

the CNVSS pin), or the product may be permanently damaged.

● Programming voltage : 12.5 V

● Setting of programming adapter switch : refer to table 3.3.2

● Setting of PROM programmer address : refer to table 3.3.3

Table 3.3.2 Setting of programming adapter switch SW 1

CMOS

SW 2

CMOS

SW 3

OFF

Microcomputer

M38063E6FS

M38063E6FP

(one-time blank)

M38063E6GP

(one-time blank)

M38067ECAFS

M38067ECFP

(one-time blank)

M38067ECDFP

(one-time blank)

M38067ECAFP

(one-time blank)

M38067ECGP

(one-time blank)

M38067ECAGP

(one-time blank)

Programming adapter

PCA4738L-80A

PCA4738F-80A

PCA4738G-80A

PCA4738L-80A

PCA4738F-80A

PCA4738G-80A

Programming adapter

PCA4738F-80A

PCA4738L-80A

PCA4738G-80A

3806 GROUP USER’S MANUAL 3-35

APPENDIX

3.3 Notes on use

Table 3.3.3 Setting of PROM programmer address

PROM programmer completion address

Address : 7FFD16 (Note 1)

Address : FFFD16 (Note 2)

PROM programmer start address

Address : 208016 (Note 1)

Address : 408016 (Note 2)

Microcomputer

M38063E6FS

M38063E6FP

M38063E6GP

M38067ECFP

M38067ECGP

M38067ECDFP

M38067ECAFS

M38067ECAFP

M38067ECAGP

Note1 : Addresses A08016 to FFFD16 in the internal PROM correspond to addresses 208016 to 7FFD16 in the

ROM programmer.

2 : Addresses 408016 to FFFD16 in the internal PROM correspond to addresses 408016 to FFFD16 in the

ROM programmer.

(3) Erasing

Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537-

Angstrom . At least 15 W-sec/cm are required to erase EPROM contents.

2

3806 GROUP USER’S MANUAL

3-36

APPENDIX

3.4 Countermeasures against noise

3.4 Countermeasures against noise

Countermeasures against noise are described below. The following countermeasures are effective against noise in

theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.

3.4.1 Shortest wiring length

The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.

The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.

(1) Wiring for the RESET pin

Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor

across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm).

Reason

The reset works to initialize a microcomputer.

The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having

a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state

of the microcomputer is completely initialized. This may cause a program runaway.

Fig. 3.4.1 Wiring for the RESET pin

(2) Wiring for clock input/output pins

●Make the length of wiring which is connected to clock I/O pins as short as possible.

●Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an

oscillatorand the VSS pin of a microcomputer as short as possible.

●Separate the VSS pattern only for oscillation from other VSS patterns.

Reason

A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock

I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway.

Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the V SS level

of an oscillator, the correct clock will not be input in the microcomputer.

RESET

Reset

circuit

Noise

V

SS

V

SS

Reset

circuit

V

SS

RESET

V

SS

3806 group 3806 group

N.G. O.K.

3806 GROUP USER’S MANUAL 3-37

APPENDIX

3.4 Countermeasures against noise

Fig. 3.4.2 Wiring for clock I/O pins

(3) Wiring for the VPP pin of the One Time PROM

version and the EPROM version

(In this microcomputer the VPP pin is also used

as the CNVSS pin)

Connect an approximately 5 kΩ resistor to theVPP

pin the shortest possible in series and also to the VSS

pin. When not connecting the resistor, make the

length of wiring between the VPP pin and the VSS pin

the shortest possible.

Note:Even when a circuit which inclued an

approximately 5 kΩ resistor is used in the Mask ROM

version, the maicrocomputer operates correctly.

Reason

The VPP pin of the One Time PROM and the EPROM

version is the power source input pin for the built-in

PROM. When programming in the built-in PROM,

the impedance of the VPP pin is low to allow the

electric current for wiring flow into the PROM. Be-

cause of this, noise can enter easily. If noise enters

the VPP pin, abnormal in struction codes or data are

read from the built-in PROM, which may cause a

program runaway.

3.4.2 Connection of a bypass capacitor across the

Vss line and the Vcc line

Connect an approximately 0.1

µ

F bypass capacitor

across the VSS line and the VCC line as follows:

●Connect a bypass capacitor across the VSS pin

and the VCC pin at equal length .

●Connect a bypass capacitor across the VSS pin

and the VCC pin with the shortest possible wiring.

●Use lines with a larger diameter than other signal

lines for VSS line and VCC line.

Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM

and the EPROM version

Fig. 3.4.4 Bypass capacitor across the VSS line and

the VCC line

X

IN

X

OUT

V

SS

An example of V

SS

patterns on the

underside of a printed circuit board

Oscillator wiring

pattern example

Separate the V

SS

line for oscillation from other V

SS

lines

Noise

X

IN

X

OUT

V

SS

X

IN

X

OUT

V

SS

N.G. O.K.

CNV

SS

/V

PP

Approximately

5kΩ

3806 group

V

SS

Make it the shortest possible

V

SS

V

CC

V

SS

V

CC

Chip

3806 GROUP USER’S MANUAL

3-38

APPENDIX

3.4 Countermeasures against noise

3.4.3 Wiring to analog input pins

●Connect an approximately 100 Ω to 1 kΩ resistor to an

analog signal line which is connected to an analog

input pin in series. Besides, connect the resistor to

the microcomputer as close as possible.

●Connect an approximately 1000 pF capacitor across

the VSS pin and the analog input pin. Besides,

connect the capacitor to the VSS pin as close as

possible. Also, connect the capacitor across the

analog input pin and the VSS pin at equal length.

Reason

Signals which is input in an analog input pin (such as

an A-D converter input pin) are usually output signals

from sensor. The sensor which detects a change of

event is installed far from the printed circuit board

with a microcomputer, the wiring to an analog input

pin is longer necessarily. This long wiring functions

as an antenna which feeds noise into the

microcomputer, which causes noise to an analog

input pin.

3.4.4. Consideration for oscillator

Take care to prevent an oscillator that generates

clocks for a microcomputer operation from being

affected by other signals.

(1) Keeping an oscillator away from large current

signal lines

Install a microcomputer (and especially an oscillator)

as far as possible from signal lines where a current

larger than the tolerance of current value flows.

Reason

In the system using a microcomputer, there are

signal lines for controlling motors, LEDs, and thermal

heads or others. When a large current flows through

those signal lines, strong noise occurs because of

mutual inductance.

(2) Keeping an oscillator away from signal lines

where potential levels change frequently

Install an oscillator and a connecting pattern of an

osillator away from signal lines where potential levels

change frequently. Also, do not cross such signal

lines over the clock lines or the signal lines which are

sensitive to noise.

Reason

Signal lines where potential levels change frequently

(such as the CNTR pin line) may affect other lines at

signal rising or falling edge. If such lines cross over

a clock line, clock waveforms may be deformed,

which causes a microcomputer failure or a program

runaway.

Fig.3.4.6 Wiring for a large current signal line

Fig.3.4.7 Wiring to a signal line where potential levels

change frequently

Fig.3.4.5 Analog signal line and a resistor and a

capacitor

N.G. O.K.

V

SS

Analog

input pin

Microcomputer

(Note)

Thermistor

Noise

Note:The resistor is for dividing resistance

with a thermister.

X

IN

X

OUT

V

SS

M

Microcomputer

Mutual inductance

Large

current

GND

X

IN

X

OUT

V

SS

CNTR

Do not cross

3806 GROUP USER’S MANUAL 3-39

APPENDIX

3.4 Countermeasures against noise

3.4.5 Setup for I/O ports

Setup I/O ports using hardware and software as follows:

<Hardware>

●Connect a resistor of 100 Ω or more to an I/O port

inseries.

<Software>

●As for an input port, read data several times by a

program for checking whether input levels are

equal or not.

●As for an output port, since the output data may

reverse because of noise, rewrite data to its port

latch at fixed periods.

●Rewirte data to direction registers and pull-up

control registers (only the product having it) at fixed

periods.

Fig. 3.4.8 Setup for I/O ports

When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be

output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.

3.4.6 Providing of watchdog timer function by

software

If a microcomputer runs away because of noise or

others, it can be detected by a software watchdog

timer and the microcomputer can be reset to normal

operation. This is equal to or more effective than

program runaway detection by a hardware watchdog

timer. The following shows an example of a watchdog

timer provided by software.

In the following example, to reset a microcomputer to

normal operation, the main routine detects errors of

the interrupt processing routine and the interrupt

processing routine detects errors of the main routine.

This example assumes that interrupt processing is

repeated multiple times in a single main routine

processing.

<The main routine>

●Assigns a single byte of RAM to a software watchdog

timer (SWDT) and writes the initial value N in the

SWDT once at each execution of the main routine.

The initial value N should satisfy the following

condition: Fig. 3.4.9 Watchdog timer by software

N+1 ≥ (Counts of interrupt processing executed in each main routine)

As the main routine execution cycle may change because of an interrupt processing or others, the initial value N

should have a margin.

●Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of

interrupt processing count after the initial value N has been set.

●Detects that the interrupt processing routine has failed and determines to branch to the program initialization

routine for recovery processing in the following cases:

If the SWDT contents do not change after interrupt processing

Direction register

Port latch

Data bus

I/O port

pins

Noise

Noise

N.G.

O.K.

Main routine

(SWDT)← N

CLI

Main processing

(SWDT)

Interrupt processing

routine errors

=N

Interrupt processing routine

(SWDT) ← (SWDT)—1

Interrupt processing

(SWDT)

Main routine

errors

>0

≤0RTI

Return

=N?

≤0?

N

3806 GROUP USER’S MANUAL

3-40

APPENDIX

3.4 Countermeasures against noise

<The interrupt processing routine>

●Decrements the SWDT contents by 1 at each interrupt processing.

●Determins that the main routine operates normally when the S WDT contents are reset to the initial value N at

almost fixed cycles (at the fixed interrupt processing count).

●Detects that the main routine has failed and determines to branch to the program initialization routine for recovery

processing in the following case:

When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value

N .

3806 GROUP USER’S MANUAL 3-41

APPENDIX

3.5 List of registers

3.5 List of registers

Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

Port Pi

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

4

5

6

7

Name

Port Pi0

Port Pi1

Port Pi2

Port Pi3

Port Pi4

Port Pi5

Port Pi6

Port Pi7

In output mode

Write

Read

●

Port latch

In input mode

Write : Port latch

Read : Value of pins

●

?

Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]

?

?

?

?

?

?

?

Port Pi direction register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

Name

Port Pi

direction register

0

0

0

0

0

0

0

0

Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)

[Address : 01

16

, 03

16

, 05

16

, 07

16

, 09

16

, 0B

16

, 0D

16

, 0F

16

, 11

16

]

0 : Port Pi

0

input mode

1 : Port Pi

0

output mode

0 : Port Pi

1

input mode

1 : Port Pi

1

output mode

0 : Port Pi

2

input mode

1 : Port Pi

2

output mode

0 : Port Pi

3

input mode

1 : Port Pi

3

output mode

0 : Port Pi

4

input mode

1 : Port Pi

4

output mode

0 : Port Pi

5

input mode

1 : Port Pi

5

output mode

0 : Port Pi

6

input mode

1 : Port Pi

6

output mode

0 : Port Pi

7

input mode

1 : Port Pi

7

output mode

✕

✕

✕

✕

✕

✕

✕

✕

3806 GROUP USER’S MANUAL

3-42

APPENDIX

3.5 List of registers

Fig. 3.5.3 Structure of Transmit/Receive buffer register

Fig. 3.5.4 Structure of Serial I/O1 status register

Transmit/Receive buffer register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

6

7

Transmit/Receive buffer register

(TB/RB) [Address : 1816]

A transmission data is written to or a receive data is read out

from this buffer register.

• At writing : a data is written to the transmit buffer register.

• At reading : a content of the receive buffer register is read out.

?

?

?

?

?

5?

?

?

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

0

0

0

0

0

0

0

1

Serial I/O1 status reigster (SIO1STS) [Address : 1916]

Name

Transmit buffer empty flag

(TBE)

0 : (OE) (PE) (FE) = 0

1 : (OE) (PE) (FE) = 1

Overrun error flag (OE)

0 : Buffer full

1 : Buffer empty

Nothing is allocated for this bit. It is a write disabled bit.

When this bit is read out, the value is “0.”

Receive buffer full flag (RBF)

Transmit shift register shift

completion flag (TSC)

Parity error flag (PE)

Framing error flag (FE)

Summing error flag (SE)

0 : Buffer empty

1 : Buffer full

0 : Transmit shift in progress

1 : Transmit shift completed

0 : No error

1 : Overrun error

0 : No error

1 : Parity error

0 : No error

1 : Framing error

✕

✕

✕

✕

✕

✕

✕

✕

Serial I/O1 status register

3806 GROUP USER’S MANUAL 3-43

APPENDIX

3.5 List of registers

Fig. 3.5.6 Structure of UART control register

Fig. 3.5.5 Structure of Serial I/O1 control register

UART control register (UARTCON) [Address : 1B

16

]

UART control register

Function

0

0

0

0

0

1

1

1

Character length

selection bit (CHAS)

Parity enable bit

(PARE)

Stop bit length selection

bit (STPS)

P4

5

/TxD P-channel

output disable bit

(POFF)

Nothing is allocated for these bits. These are write

disabled bits. When these bits are read out, the

values are “1.”

Parity selection bit

(PARS)

In output mode

0 : CMOS output

1 : N-channel open-drain

output

0 : 8 bits

1 : 7 bits

0 :

Parity checking disabled

1 :

Parity checking enabled

0 : 1 stop bit

1 : 2 stop bits

0 : Even parity

1 : Odd parity

B

0

1

2

3

4

5

6

7

b7 b6 b5 b4 b3 b2 b1 b0

At reset

RW

Name

✕

✕

✕

b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A16]

Serial I/O1 control register

0 : I/O port (P47)

1 : SRDY1 output pin

0

0

0

0

0

0

0

0

Function At reset RW

Name

B

0

1

2

3

4

5

6

7

At selecting clock synchronous serial I/O

0 : BRG output divided by 4

1 : External clock input

At selecting UART

0 : BRG output divided by 16

1 : External clock input divided by 16

0 : Transmit buffer empty

1 : Transmit shift operating

completion

0 : f(XIN)

1 : f(XIN)/4

0 : Serial I/O1 disabled

(P44–P47 : I/O port)

1 : Serial I/O1 enabled

(P44–P47 : Serial I/O function pin)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

0 : UART

1 : Clock synchronous serial I/O

BRG count source

selection bit (CSS)

Serial I/O1

synchronous clock

selection bit (SCS)

Transmit interrupt

source selection bit

(TIC)

SRDY1 output enable bit

(SRDY)

Transmit enable bit (TE)

Receive enable bit (RE)

Serial I/O1 enable bit

(SIOE)

Serial I/O1 mode

selection bit (SIOM)

3806 GROUP USER’S MANUAL

3-44

APPENDIX

3.5 List of registers

Fig. 3.5.7 Structure of Baud rate generator

Fig. 3.5.8 Structure of Serial I/O2 control register

Serial I/O2 control register (SIO2CON) [Address : 1D

16

]

B

0

1

2

3

4

5

6

7

0

:

I/O port (P7

1

, P7

2

)

1

:

S

OUT2

, S

CLK2

output pin

0

:

I/O port (P7

3

)

1

:

S

RDY2

output pin

0

:

LSB first

1

:

MSB first

0

:

External clock

1

:

Internal clock

0 0 0 : f(X

IN

)/8

0 0 1 : f(X

IN

)/16

0 1 0 : f(X

IN

)/32

0 1 1 : f(X

IN

)/64

1 1 0 : f(X

IN

)/128

1 1 1 : f(X

IN

)/256

b2 b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

S

RDY2

output enable bit

Internal synchronous

clock selection bits

Transfer direction

selection bit

Serial I/O2 port selection bit

Serial I/O2 synchronous clock

selection bit

Nothing is allocated for this bit. This is write disabled bit. When

this bit is read out, the value is “0.”

0

0

0

0

0

0

0

0

✕

Function

At reset

RW

Name

Serial I/O2 control register

Baud rate generator

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

A count value of Baud rate generator is set.

?

Baud rate generator (BRG) [Address : 1C

16

]

?

?

?

?

?

?

?

3806 GROUP USER’S MANUAL 3-45

APPENDIX

3.5 List of registers

Fig. 3.5.9 Structure of Serial I/O2 register

Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y

Serial I/O2 register

b7 b6 b5 b4 b3 b2 b1 b0

Function

Serial I/O2 register (SIO2) [Address : 1F16]

A shift register for serial transmission and reception.

At transmitting : Set a transmission data.

At receiving : Store a reception data.

B

0

1

2

3

4

5

6

7

At reset

RW

?

?

?

?

?

?

?

?

●

●

Prescaler 12, Prescaler X, Prescaler Y

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

1

1

1

1

1

1

1

1

Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)

[Address : 20

16

, 24

16

, 26

16

]

The count value of each prescaler is set.

The value set in this register is written to both the prescaler and

the prescaler latch at the same time.

When the prescaler is read out, the value (count value) of the

prescaler is read out.

●

●

●

3806 GROUP USER’S MANUAL

3-46

APPENDIX

3.5 List of registers

Fig. 3.5.11 Structure of Timer 1

Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

4

5

6

7

1

0

0

0

0

0

0

0

Timer 1 (T1) [Address : 2116]

The count value of the Timer 1 is set.

The value set in this register is written to both the Timer 1 and

the Timer 1 latch at the same time.

When the Timer 1 is read out, the value (count value) of the

Timer 1 is read out.

●

●

●

Timer 1

Timer 2, Timer X, Timer Y

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

4

5

6

7

1

1

1

1

1

1

1

1

Timer 2 (T2), Timer X (TX), Timer Y (TY)

[Address : 2216, 2516, 2716]

The count value of each timer is set.

The value set in this register is written to both the Timer and the

Timer latch at the same time.

When the Timer is read out, the value (count value) of the Timer

is read out.

●

●

●

3806 GROUP USER’S MANUAL 3-47

APPENDIX

3.5 List of registers

Operating mode of

Timer X/Timer Y

Timer mode

Pulse output mode

Event counter mode

Pulse width measurement mode

Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit

Fig. 3.5.13 Structure of Timer XY mode register

Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

(No effect on timer count)

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

(No effect on timer count)

• Start of pulse output : From “H” level

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

• Start of pulse output : From “L” level

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

• Timer X/Timer Y : Count of rising edge

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

• Timer X/Timer Y : Count of falling edge

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

• Timer X/Timer Y : Measurement of “H” level width

• Generation of CNTR0/CNTR1 interrupt request : Falling edge

• Timer X/Timer Y : Measurement of “L” level width

• Generation of CNTR0/CNTR1 interrupt request : Rising edge

Function

Timer XY mode register

b7 b6 b5 b4 b3 b2 b1 b0

B

At reset

RW

0

1

2

3

4

5

6

7

0

0

0

0

0

0

0

0

Timer XY mode register (TM)

Name

Timer X operating mode

CNTR0 active edge switch

bit

Timer Y operating mode

CNTR1 active edge switch

bit

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

It depends on the operating mode

of the Timer X (refer to Table 3.5.1).

It depends on the operating mode

of the Timer Y (refer to Table 3.5.1 ).

b5 b4

Timer X count stop bit

[Address : 2316]

b1 b0

Timer Y count stop bit

0 : Count start

1 : Count stop

0 : Count start

1 : Count stop

3806 GROUP USER’S MANUAL

3-48

APPENDIX

3.5 List of registers

Fig. 3.5.15 Structure of A-D conversion register

Fig. 3.5.14 Structure of AD/DA control register

A-D conversion register

b7 b6 b5 b4 b3 b2 b1 b0

B Function

At reset

RW

A-D conversion register (AD) [Address : 35

16

]

The read-only register which A-D conversion results are stored. ✕

0

1

2

3

4

5

6

7

?

?

?

?

?

?

?

?

✕

✕

✕

✕

✕

✕

✕

AD/DA control register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

Name

Analog input pin selection bits

AD/DA control register (ADCON) [Address : 34

16

]

0 0 0 : P6

0

/AN

0

0 0 1 : P6

1

/AN

1

0 1 0 : P6

2

/AN

2

0 1 1 : P6

3

/AN

3

1 0 0 : P6

4

/AN

4

1 0 1 : P6

5

/AN

5

1 1 0 : P6

6

/AN

6

1 1 1 : P6

7

/AN

7

b2 b1 b0

1

3

1

0

0

0

0

0

0 : DA

1

output disable

1 : DA

1

output enable

DA

1

output enable bit

6

0

7

0

✕

Nothing is allocated for these bits. These are write disabled bits.

4

When these bits are read out, the values are “0.”

0 : DA

2

output disabled

1 : DA

2

output enabled

DA

2

output enable bit

2

50

✕

AD conversion completion bit 0 : Conversion in progress

1 : Conversion completed

3806 GROUP USER’S MANUAL 3-49

APPENDIX

3.5 List of registers

Fig. 3.5.16 Structure of D-A 1 conversion, D-A 2 conversion register

Fig. 3.5.17 Structure of Interrupt edge selection register

D-A1 conversion register, D-A2 conversion register

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

4

5

6

7

0

0

0

0

0

0

0

0

D-A1 conversion register (DA1), D-A2 conversion register (DA2)

[Address : 3616, 3716]

An output value of each D-A converter is set.

Interrupt edge selection register (INTEDGE) [Address : 3A

16

]

Interrupt edge selection register

B

0

1

2

6

7

3

4

5

b7 b6 b5 b4 b3 b2 b1 b0

0

0

0

0

0

0

0

0

✕

✕

✕

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “0.”

INT

0

interrupt edge

selection bit

INT

1

interrupt edge

selection bit

INT

2

interrupt edge

selection bit

Nothing is allocated for these bits. These are write disabled

bits. When these bits are read out, the values are “0.”

INT

3

interrupt edge

selection bit

INT

4

interrupt edge

selection bit

Function

At reset

RW

Name

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

3806 GROUP USER’S MANUAL

3-50

APPENDIX

3.5 List of registers

Fig. 3.5.18 Structure of CPU mode register

CPU mode register (CPUM) [Address : 3B

16

]

B

0

1

2

CPU mode register

00 : Single-chip mode

01 : Memory expansion mode

10 : Microprocessor mode

11 : Not available

0 : 0 page

1 : 1 page

3

4

5

6

7

Processor mode bits

Stack page selection bit

Nothing is allocated for these bits. These are write disabled bits.

When these bits are read out, the values are “0.”

Function

At reset

RW

Name

0

0

0

0

0

0

0

✻

✻ An initial value of bit 1 is determined by a level of the CNV

SS

pin.

b7 b6 b5 b4 b3 b2 b1 b0

✕

✕

✕

✕

✕

3806 GROUP USER’S MANUAL 3-51

APPENDIX

3.5 List of registers

Fig. 3.5.19 Structure of Interrupt request register 1

Fig. 3.5.20 Structure of Interrupt request register 2

Timer X interrupt request

bit

Serial I/O1 receive interrupt

request bit

Interrupt request register 1

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

0

0

0

0

Interrupt request reigster 1 (IREQ1) [Address : 3C16]

Name

INT0 interrupt request bit

INT1 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

Serial I/O1 transmit interrupt

request bit

✻

✻

✻

✻

Timer Y interrupt request bit

4

5

6

7

0

0

0

0

Timer 1 interrupt request bit 0 : No interrupt request

1 : Interrupt request

Timer 2 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

✻

✻

✻

✻

✻“0” is set by software, but not “1.”

Interrupt request register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction

At reset

RW

0

1

2

3

0

0

0

0

Interrupt request reigster 2 (IREQ2) [Address : 3D

16

]

Name

CNTR

0

interrupt request bit

CNTR

1

interrupt request bit

Serial I/O2 interrupt request

bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

INT

2

interrupt request bit

✻

✻

✻

✻

5

6

7

0

0

0 : No interrupt request

1 : Interrupt request

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “0.”

AD conversion interrupt

request bit

INT

4

interrupt request bit

0 : No interrupt request

1 : Interrupt request

✻

✻

✻“0” is set by software, but not “1.”

4 0

0 : No interrupt request

1 : Interrupt request

INT

3

interrupt request bit ✻

0

✕

3806 GROUP USER’S MANUAL

3-52

APPENDIX

3.5 List of registers

Fig. 3.5.21 Structure of Interrupt control register 1

Fig. 3.5.22 Structure of Interrupt control register 2

Timer Y interrupt enable bit

Interrupt control register 1

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

0

0

0

0

Interrupt control register 1 (ICON1) [Address : 3E16]

Name

INT0 interrupt enable bit

INT1 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

4

5

6

7

0

0

0

0

Timer X interrupt enable bit

Timer 1 interrupt enable bit 0 : Interrupt disabled

1 : Interrupt enabled

Timer 2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Serial I/O1 transmit interrupt

enable bit

Serial I/O1 receive interrupt

enable bit

Interrupt control register 2

b7 b6 b5 b4 b3 b2 b1 b0

BFunction At reset RW

0

1

2

3

0

0

0

0

Interrupt control reigster 2 (ICON2) [Address : 3F

16

]

Name

CNTR

0

interrupt enable bit

CNTR

1

interrupt enable bit

Serial I/O2 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

INT

2

interrupt enable bit

5

6

7

0

0

0 : Interrupt disabled

1 : Interrupt enabled

Fix this bit to “0.”

AD conversion interrupt

enable bit

INT

4

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

4 0

0 : Interrupt disabled

1 : Interrupt enabled

INT

3

interrupt enable bit

0

0

APPENDIX

3.6 Mask ROM ordering method

3-53

3806 GROUP USER’S MANUAL

GZZ-SH03-63B<07B0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M3-XXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name :

27256 27512

000016

000F16

001016

507F16

508016

7FFD16

7FFE16

7FFF16

M38062M3-XXXFP M38062M3-XXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address D08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38062M3–”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘2’ = 3216

‘M’ = 4D16

‘3’ = 3316

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘ – ’ = 2D16

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

D07F16

D08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38062M3–’

data

ROM 12158 bytes

Product name

ASCII code :

‘M38062M3–’

data

ROM 12158 bytes

3.6 Mask ROM ordering method

APPENDIX

3.6 Mask ROM ordering method

3-54 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M3-XXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH03-63B<07B0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38062M3–’ *= $0000

.BYTE ‘M38062M3–’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38062M3-XXXFP, 80P6S for M38062M3-XXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-55

3806 GROUP USER’S MANUAL

GZZ-SH04-80B<16A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M3DXXXFP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

27256 27512

000016

000F16

001016

507F16

508016

7FFD16

7FFE16

7FFF16

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address D08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38062M3D”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘2’ = 3216

‘M’ = 4D16

‘3’ = 3316

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘D’ = 4416

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

D07F16

D08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38062M3D’

data

ROM 12158 bytes

Product name

ASCII code :

‘M38062M3D’

data

ROM 12158 bytes

APPENDIX

3.6 Mask ROM ordering method

3-56 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M3DXXXFP

MITSUBISHI ELECTRIC

GZZ-SH04-80B<16A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38062M3D’ *= $0000

.BYTE ‘M38062M3D’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38062M3DXXXFP) and attach it to the mask ROM confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-57

3806 GROUP USER’S MANUAL

GZZ-SH04-26B<13B0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M4-XXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name :

27256 27512

000016

000F16

001016

407F16

408016

7FFD16

7FFE16

7FFF16

M38062M4-XXXFP M38062M4-XXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address C08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38062M4–”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘2’ = 3216

‘M’ = 4D16

‘4’ = 3416

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘ – ’ = 2D16

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

C07F16

C08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38062M4–’

data

ROM 16254 bytes

Product name

ASCII code :

‘M38062M4–’

data

ROM 16254 bytes

APPENDIX

3.6 Mask ROM ordering method

3-58 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M4-XXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH04-26B<13B0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38062M4–’ *= $0000

.BYTE ‘M38062M4–’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38062M4-XXXFP, 80P6S for M38062M4-XXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-59

3806 GROUP USER’S MANUAL

GZZ-SH04-81B<16A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M4DXXXFP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

27256 27512

000016

000F16

001016

407F16

408016

7FFD16

7FFE16

7FFF16

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address C08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38062M4D”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘2’ = 3216

‘M’ = 4D16

‘4’ = 3416

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘D’ = 4416

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

C07F16

C08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38062M4D’

data

ROM 16254 bytes

Product name

ASCII code :

‘M38062M4D’

data

ROM 16254 bytes

APPENDIX

3.6 Mask ROM ordering method

3-60 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38062M4DXXXFP

MITSUBISHI ELECTRIC

GZZ-SH04-81B<16A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38062M4D’ *= $0000

.BYTE ‘M38062M4D’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38062M4DXXXFP) and attach it to the mask ROM confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-61

3806 GROUP USER’S MANUAL

GZZ-SH03-26B<9ZC0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38063M6-XXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name :

27256 27512

000016

000F16

001016

207F16

208016

7FFD16

7FFE16

7FFF16

M38063M6-XXXFP M38063M6-XXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address A08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38063M6–”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘3’ = 3316

‘M’ = 4D16

‘6’ = 3616

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘ – ’ = 2D16

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

A07F16

A08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38063M6–’

data

ROM 24446 bytes

Product name

ASCII code :

‘M38063M6–’

data

ROM 24446 bytes

APPENDIX

3.6 Mask ROM ordering method

3-62 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38063M6-XXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH03-26B<9ZC0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38063M6–’ *= $0000

.BYTE ‘M38063M6–’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38063M6-XXXFP, 80P6S for M38063M6-XXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-63

3806 GROUP USER’S MANUAL

GZZ-SH07-64B<36B0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38063M6AXXXFP/GP/HP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name :

27256 27512

000016

000F16

001016

207F16

208016

7FFD16

7FFE16

7FFF16

M38063M6AXXXFP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address A08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38063M6A”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘3’ = 3316

‘M’ = 4D16

‘6’ = 3616

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘A’ = 4116

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

A07F16

A08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38063M6A’

data

ROM 24446 bytes

Product name

ASCII code :

‘M38063M6A’

data

ROM 24446 bytes

M38063M6AXXXGP M38063M6AXXXHP

APPENDIX

3.6 Mask ROM ordering method

3-64 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38063M6AXXXFP/GP/HP

MITSUBISHI ELECTRIC

GZZ-SH07-64B<36B0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38063M6A’ *= $0000

.BYTE ‘M38063M6A’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38063M6AXXXFP, 80P6S for M38063M6AXXXGP, 80P6D for M38063M6AXXXHP) and

attach it to the mask ROM confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-65

3806 GROUP USER’S MANUAL

GZZ-SH04-72B<15A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38063M6DXXXFP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

27256 27512

000016

000F16

001016

207F16

208016

7FFD16

7FFE16

7FFF16

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address A08016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38063M6D”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘3’ = 3316

‘M’ = 4D16

‘6’ = 3616

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘D’ = 4416

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM address EPROM address

EPROM type (indicate the type used)

000016

000F16

001016

A07F16

A08016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38063M6D’

data

ROM 24446 bytes

Product name

ASCII code :

‘M38063M6D’

data

ROM 24446 bytes

APPENDIX

3.6 Mask ROM ordering method

3-66 3806 GROUP USER’S MANUAL

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38063M6DXXXFP

MITSUBISHI ELECTRIC

GZZ-SH04-72B<15A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

27256 27512

EPROM type

The pseudo-command *= $8000

.BYTE ‘M38063M6D’ *= $0000

.BYTE ‘M38063M6D’

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38063M6DXXXFP) and attach it to the mask ROM confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-67

3806 GROUP USER’S MANUAL

GZZ-SH04-87B<17B0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067M8-XXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name : M38067M8-XXXFP M38067M8-XXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address 808016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38067M8–”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘7’ = 3716

‘M’ = 4D16

‘8’ = 3816

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘ – ’ = 2D16

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM type (indicate the type used)

27512

EPROM address

000016

000F16

001016

807F16

808016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38067M8–’

data

ROM 32638 bytes

APPENDIX

3.6 Mask ROM ordering method

3-68 3806 GROUP USER’S MANUAL

27512

*= $0000

.BYTE ‘M38067M8–’

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067M8-XXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH04-87B<17B0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembier source program.

EPROM type

The pseudo-command

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38067M8-XXXFP, 80P6S for M38067M8-XXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-69

3806 GROUP USER’S MANUAL

GZZ-SH07-63B<36B0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067M8AXXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name : M38067M8AXXXFP M38067M8AXXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address 808016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38067M8A”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘7’ = 3716

‘M’ = 4D16

‘8’ = 3816

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘A’ = 4116

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM type (indicate the type used)

27512

EPROM address

000016

000F16

001016

807F16

808016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38067M8A’

data

ROM 32638 bytes

APPENDIX

3.6 Mask ROM ordering method

3-70 3806 GROUP USER’S MANUAL

27512

*= $0000

.BYTE ‘M38067M8A’

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067M8AXXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH07-63B<36B0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembier source program.

EPROM type

The pseudo-command

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38067M8AXXXFP, 80P6S for M38067M8AXXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-71

3806 GROUP USER’S MANUAL

GZZ-SH04-89B<17A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067M8DXXXFP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address 808016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38067M8D”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘7’ = 3716

‘M’ = 4D16

‘8’ = 3816

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘D’ = 4416

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM type (indicate the type used)

27512

EPROM address

000016

000F16

001016

807F16

808016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38067M8D’

data

ROM 32638 bytes

APPENDIX

3.6 Mask ROM ordering method

3-72 3806 GROUP USER’S MANUAL

27512

*= $0000

.BYTE ‘M38067M8D’

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067M8DXXXFP

MITSUBISHI ELECTRIC

GZZ-SH04-89B<17A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembier source program.

EPROM type

The pseudo-command

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38067M8DXXXFP) and attach it to the mask ROM confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-73

3806 GROUP USER’S MANUAL

GZZ-SH07-53B<35A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067MC-XXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name : M38067MC-XXXFP M38067MC-XXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address 408016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38067MC–”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16. The

ASCII codes and addresses are listed to the right in

hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘7’ = 3716

‘M’ = 4D16

‘C’ = 4316

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘ – ’ = 2D16

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM type (indicate the type used)

27512

EPROM address

000016

000F16

001016

407F16

408016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38067MC–’

data

ROM 49022 bytes

APPENDIX

3.6 Mask ROM ordering method

3-74 3806 GROUP USER’S MANUAL

27512

*= $0000

.BYTE ‘M38067MC–’

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067MC-XXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH07-53B<35A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembier source program.

EPROM type

The pseudo-command

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38067MC-XXXFP, 80P6S for M38067MC-XXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-75

3806 GROUP USER’S MANUAL

GZZ-SH07-66B<36A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067MCAXXXFP/GP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name : M38067MCAXXXFP M38067MCAXXXGP

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address 408016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38067MCA”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘7’ = 3716

‘M’ = 4D16

‘C’ = 4316

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘A’ = 4116

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM type (indicate the type used)

27512

EPROM address

000016

000F16

001016

407F16

408016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38067MCA’

data

ROM 49022 bytes

APPENDIX

3.6 Mask ROM ordering method

3-76 3806 GROUP USER’S MANUAL

27512

*= $0000

.BYTE ‘M38067MCA’

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067MCAXXXFP/GP

MITSUBISHI ELECTRIC

GZZ-SH07-66B<36A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembier source program.

EPROM type

The pseudo-command

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38067MCAXXXFP, 80P6S for M38067MCAXXXGP) and attach it to the mask ROM

confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.6 Mask ROM ordering method

3-77

3806 GROUP USER’S MANUAL

GZZ-SH07-54B<35A0>

Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067MCDXXXFP

MITSUBISHI ELECTRIC

Mask ROM number

Date:

Section head

signature Supervisor

signature

Company

name

Note : Please fill in all items marked ❈.

Customer

❈

Issuance

signature

Date

issued

Submitted by

TEL

()

Date:

Supervisor

❈ 1. Confirmation

Specify the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We

shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.

Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Checksum code for entire EPROM (hexadecimal notation)

In the address space of the microcomputer, the internal ROM

area is from address 408016 to FFFD16. The reset vector is

stored in addresses FFFC16 and FFFD16.

(1) Set the data in the unused area (the shaded area of

the diagram) to “FF16”.

(2) The ASCII codes of the product name “M38067MCD”

must be entered in addresses 000016 to 000816. And

set the data “FF16” in addresses 000916 to 000F16.

The ASCII codes and addresses are listed to the right

in hexadecimal notation.

Address

000016

000116

000216

000316

000416

000516

000616

000716

‘M’ = 4D16

‘3’ = 3316

‘8’ = 3816

‘0’ = 3016

‘6’ = 3616

‘7’ = 3716

‘M’ = 4D16

‘C’ = 4316

Address

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

‘D’ = 4416

FF16

FF16

FF16

FF16

FF16

FF16

FF16

(1/2)

EPROM type (indicate the type used)

27512

EPROM address

000016

000F16

001016

407F16

408016

FFFD16

FFFE16

FFFF16

Product name

ASCII code :

‘M38067MCD’

data

ROM 49022 bytes

APPENDIX

3.6 Mask ROM ordering method

3-78 3806 GROUP USER’S MANUAL

27512

*= $0000

.BYTE ‘M38067MCD’

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38067MCDXXXFP

MITSUBISHI ELECTRIC

GZZ-SH07-54B<35A0> Mask ROM number

We recommend the use of the following pseudo-command to set the start address of the assembier source program.

EPROM type

The pseudo-command

Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will

not be processed.

We recommend the use of the following pseudo-command to set the start address of the assembler source program.

(2/2)

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark

specification form (80P6N for M38067MCDXXXFP) and attach it to the mask ROM confirmation form.

❈ 3. Usage conditions

Please answer the following questions about usage for use in our product inspection :

(1) How will you use the XIN-XOUT oscillator?

At what frequency? f(XIN) =

(2) In which operation mode will you use your microcomputer?

❈ 4. Comments

Ceramic resonator

External clock input

Single-chip mode

Microprocessor mode

Quartz crystal

Other ( )

Memory expansion mode

MHz

APPENDIX

3.7 Mark specification form

3-79

3806 GROUP USER’S MANUAL

3.7 Mark specification form

APPENDIX

3.7 Mark specification form

3-80 3806 GROUP USER’S MANUAL

APPENDIX

3.8 Package outline

3-81

3806 GROUP USER’S MANUAL

3.8 Package outline

APPENDIX

3.8 Package outline

3-82 3806 GROUP USER’S MANUAL

3806 GROUP USER’S MANUAL

APPENDIX

3.9 List of instruction codes

3-83

3.9 List of instruction codes

3-byte instruction

2-byte instruction

1-byte instruction

D7 – D4

D3 – D0

Hexadecimal

notation

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0000

0

BRK

BPL

JSR

ABS

BMI

RTI

BVC

RTS

BVS

BRA

BCC

LDY

IMM

BCS

CPY

IMM

BNE

CPX

IMM

BEQ

0001

1

ORA

IND, X

ORA

IND, Y

AND

IND, X

AND

IND, Y

EOR

IND, X

EOR

IND, Y

ADC

IND, X

ADC

IND, Y

STA

IND, X

STA

IND, Y

LDA

IND, X

LDA

IND, Y

CMP

IND, X

CMP

IND, Y

SBC

IND, X

SBC

IND, Y

0010

2

JSR

ZP, IND

CLT

JSR

SP

SET

STP

—

MUL

ZP, X

—

RRF

ZP

—

LDX

IMM

JMP

ZP, IND

WIT

—

DIV

ZP, X

—

0011

3

BBS

0, A

BBC

0, A

BBS

1, A

BBC

1, A

BBS

2, A

BBC

2, A

BBS

3, A

BBC

3, A

BBS

4, A

BBC

4, A

BBS

5, A

BBC

5, A

BBS

6, A

BBC

6, A

BBS

7, A

BBC

7, A

0100

4

—

—

BIT

ZP

—

COM

ZP

—

TST

ZP

—

STY

ZP

STY

ZP, X

LDY

ZP

LDY

ZP, X

CPY

ZP

—

CPX

ZP

—

0101

5

ORA

ZP

ORA

ZP, X

AND

ZP

AND

ZP, X

EOR

ZP

EOR

ZP, X

ADC

ZP

ADC

ZP, X

STA

ZP

STA

ZP, X

LDA

ZP

LDA

ZP, X

CMP

ZP

CMP

ZP, X

SBC

ZP

SBC

ZP, X

0110

6

ASL

ZP

ASL

ZP, X

ROL

ZP

ROL

ZP, X

LSR

ZP

LSR

ZP, X

ROR

ZP

ROR

ZP, X

STX

ZP

STX

ZP, Y

LDX

ZP

LDX

ZP, Y

DEC

ZP

DEC

ZP, X

INC

ZP

INC

ZP, X

0111

7

BBS

0, ZP

BBC

0, ZP

BBS

1, ZP

BBC

1, ZP

BBS

2, ZP

BBC

2, ZP

BBS

3, ZP

BBC

3, ZP

BBS

4, ZP

BBC

4, ZP

BBS

5, ZP

BBC

5, ZP

BBS

6, ZP

BBC

6, ZP

BBS

7, ZP

BBC

7, ZP

1000

8

PHP

CLC

PLP

SEC

PHA

CLI

PLA

SEI

DEY

TYA

TAY

CLV

INY

CLD

INX

SED

1001

9

ORA

IMM

ORA

ABS, Y

AND

IMM

AND

ABS, Y

EOR

IMM

EOR

ABS, Y

ADC

IMM

ADC

ABS, Y

—

STA

ABS, Y

LDA

IMM

LDA

ABS, Y

CMP

IMM

CMP

ABS, Y

SBC

IMM

SBC

ABS, Y

1010

A

ASL

A

DEC

A

ROL

A

INC

A

LSR

A

—

ROR

A

—

TXA

TXS

TAX

TSX

DEX

—

NOP

—

1011

B

SEB

0, A

CLB

0, A

SEB

1, A

CLB

1, A

SEB

2, A

CLB

2, A

SEB

3, A

CLB

3, A

SEB

4, A

CLB

4, A

SEB

5, A

CLB

5, A

SEB

6, A

CLB

6, A

SEB

7, A

CLB

7, A

1100

C

—

—

BIT

ABS

LDM

ZP

JMP

ABS

—

JMP

IND

—

STY

ABS

—

LDY

ABS

LDY

ABS, X

CPY

ABS

—

CPX

ABS

—

1101

D

ORA

ABS

ORA

ABS, X

AND

ABS

AND

ABS, X

EOR

ABS

EOR

ABS, X

ADC

ABS

ADC

ABS, X

STA

ABS

STA

ABS, X

LDA

ABS

LDA

ABS, X

CMP

ABS

CMP

ABS, X

SBC

ABS

SBC

ABS, X

1110

E

ASL

ABS

ASL

ABS, X

ROL

ABS

ROL

ABS, X

LSR

ABS

LSR

ABS, X

ROR

ABS

ROR

ABS, X

STX

ABS

—

LDX

ABS

LDX

ABS, Y

DEC

ABS

DEC

ABS, X

INC

ABS

INC

ABS, X

1111

F

SEB

0, ZP

CLB

0, ZP

SEB

1, ZP

CLB

1, ZP

SEB

2, ZP

CLB

2, ZP

SEB

3, ZP

CLB

3, ZP

SEB

4, ZP

CLB

4, ZP

SEB

5, ZP

CLB

5, ZP

SEB

6, ZP

CLB

6, ZP

SEB

7, ZP

CLB

7, ZP

APPENDIX

3.10 Machine instructions

3-84 3806 GROUP USER’S MANUAL

Addressing mode

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP

OPn#OPn#OPn#OPn#OPn#OP n #

3.10 Machine instructions

Adds the carry, accumulator and memory con-

tents. The results are entered into the

accumulator.

Adds the contents of the memory in the ad-

dress indicated by index register X, the

contents of the memory specified by the ad-

dressing mode and the carry. The results are

entered into the memory at the address indi-

cated by index register X.

“AND’s” the accumulator and memory con-

tents.

The results are entered into the accumulator.

“AND’s” the contents of the memory of the ad-

dress indicated by index register X and the

contents of the memory specified by the ad-

dressing mode. The results are entered into

the memory at the address indicated by index

register X.

Shifts the contents of accumulator or contents

of memory one bit to the left. The low order bit

of the accumulator or memory is cleared and

the high order bit is shifted into the carry flag.

Branches when the contents of the bit speci-

fied in the accumulator or memory is “0”.

Branches when the contents of the bit speci-

fied in the accumulator or memory is “1”.

Branches when the contents of carry flag is

“0”.

Branches when the contents of carry flag is

“1”.

Branches when the contents of zero flag is “1”.

“AND’s” the contents of accumulator and

memory. The results are not entered any-

where.

Branches when the contents of negative flag is

“1”.

Branches when the contents of zero flag is “0”.

Branches when the contents of negative flag is

“0”.

Jumps to address specified by adding offset to

the program counter.

Executes a software interrupt.

ADC

(Note 1)

(Note 5)

AND

(Note 1)

ASL

BBC

(Note 4)

BBS

(Note 4)

BCC

(Note 4)

BCS

(Note 4)

BEQ

(Note 4)

BIT

BMI

(Note 4)

BNE

(Note 4)

BPL

(Note 4)

BRA

BRK 00

7 0

C

←

←

0

71

29 2 2

0A 2 1

03

+

2i

17

+

2i

07

+

2i

06 5 2

25 3 2

3

65 3 269 2 2

4

4

2

2

13

+

2i 5

5

3

3

24

When T = 0

A ← A + M + C

When T = 1

M(X) ← M(X) + M + C

When T = 0

A ← A M

When T = 1

M(X) ← M(X) M

Ab or Mb = 0?

Ab or Mb = 1?

C = 0?

C = 1?

Z = 1?

A M

N = 1?

Z = 0?

N = 0?

PC ← PC ± offset

B ← 1

M(S) ← PCH

S ← S – 1

M(S) ← PCL

S ← S – 1

M(S) ← PS

S ← S – 1

PCL ← ADL

PCH ← ADH

V

V

V

2

APPENDIX

3.10 Machine instructions

3-85

3806 GROUP USER’S MANUAL

Addressing mode

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0

Processor status register

NVTBDI ZC

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #

75

35

16

4

4

6

2

2

2

6D

2D

0E

2C

4

4

6

4

3

3

3

3

7D

3D

1E

5

5

7

3

3

3

79

39

5

5

3

3

61

21

6

6

2

2

90

B0

F0

30

D0

10

80

2

2

2

2

2

2

4

2

2

2

2

2

2

2

71

31

6

6

2

2

N

N

N

•

•

•

•

•

M7

•

•

•

•

•

V

•

•

•

•

•

•

•

M6

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

Z

Z

Z

•

•

•

•

•

Z

•

•

•

•

•

C

•

C

•

•

•

•

•

•

•

•

•

•

•

APPENDIX

3.10 Machine instructions

3-86 3806 GROUP USER’S MANUAL

Addressing mode

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP

OPn#OPn#OPn#OPn#OPn#OP n #

Branches when the contents of overflow flag is

“0”.

Branches when the contents of overflow flag is

“1”.

Clears the contents of the bit specified in the

accumulator or memory to “0”.

Clears the contents of the carry flag to “0”.

Clears the contents of decimal mode flag to

“0”.

Clears the contents of interrupt disable flag to

“0”.

Clears the contents of index X mode flag to

“0”.

Clears the contents of overflow flag to “0”.

Compares the contents of accumulator and

memory.

Compares the contents of the memory speci-

fied by the addressing mode with the contents

of the address indicated by index register X.

Forms a one’s complement of the contents of

memory, and stores it into memory.

Compares the contents of index register X and

memory.

Compares the contents of index register Y and

memory.

Decrements the contents of the accumulator

or memory by 1.

Decrements the contents of index register X

by 1.

Decrements the contents of index register Y

by 1.

Divides the 16-bit data that is the contents of

M (zz + x + 1) for high byte and the contents of

M (zz + x) for low byte by the accumulator.

Stores the quotient in the accumulator and the

1’s complement of the remainder on the stack.

“Exclusive-ORs” the contents of accumulator

and memory. The results are stored in the ac-

cumulator.

“Exclusive-ORs” the contents of the memory

specified by the addressing mode and the

contents of the memory at the address indi-

cated by index register X. The results are

stored into the memory at the address indi-

cated by index register X.

Increments the contents of accumulator or

memory by 1.

Increments the contents of index register X by

1.

Increments the contents of index register Y by

1.

BVC

(Note 4)

BVS

(Note 4)

CLB

CLC

CLD

CLI

CLT

CLV

CMP

(Note 3)

COM

CPX

CPY

DEC

DEX

DEY

DIV

EOR

(Note 1)

INC

INX

INY

V = 0?

V = 1?

Ab or Mb ← 0

C ← 0

D ← 0

I ← 0

T ← 0

V ← 0

When T = 0

A – M

When T = 1

M(X) – M

__

M ← M

X – M

Y – M

A ← A – 1 or

M ← M – 1

X ← X – 1

Y ← Y – 1

A ← (M(zz + X + 1),

M(zz + X)) / A

M(S) ← 1’s complememt

of Remainder

S ← S – 1

When T = 0

A ← A V

– M

When T = 1

M(X) ← M(X) V

– M

A ← A + 1 or

M ← M + 1

X ← X + 1

Y ← Y + 1

18

D8

58

12

B8

CA

88

E8

C8

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

1

C9

E0

C0

49

2

2

2

2

2

2

2

2

1A

3A

2

2

1

1

1B

+

2i

C5

44

E4

C4

C6

45

E6

3

5

3

3

5

3

5

2

2

2

2

2

2

2

1F

+

2i

21 52

APPENDIX

3.10 Machine instructions

3-87

3806 GROUP USER’S MANUAL

Addressing mode

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0

Processor status register

NVTBDI ZC

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #

D5

D6

E2

55

F6

CD

EC

CC

CE

4D

EE

50

70

2

2

2

2

•

•

•

•

•

•

•

•

N

N

N

N

N

N

N

•

N

N

N

N

•

•

•

•

•

•

•

0

•

•

•

•

•

•

•

•

•

•

•

•

4

6

16

4

6

4

4

4

6

4

6

3

3

3

3

3

3

DD

DE

5D

FE

5

7

5

7

3

3

3

3

D9

59

5

5

3

3

C1

41

6

6

2

2

D1

51

6

6

2

2

•

•

•

•

•

•

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Z

Z

Z

Z

Z

Z

Z

•

Z

Z

Z

Z

•

•

•

0

•

•

•

•

C

•

C

C

•

•

•

•

•

•

•

•

2

2

2

2

2

APPENDIX

3.10 Machine instructions

3-88 3806 GROUP USER’S MANUAL

Addressing mode

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP

OPn#OPn#OPn#OPn#OPn#OP n #

Jumps to the specified address.

After storing contents of program counter in

stack, and jumps to the specified address.

Load accumulator with contents of memory.

Load memory indicated by index register X

with contents of memory specified by the ad-

dressing mode.

Load memory with immediate value.

Load index register X with contents of

memory.

Load index register Y with contents of

memory.

Shift the contents of accumulator or memory

to the right by one bit.

The low order bit of accumulator or memory is

stored in carry, 7th bit is cleared.

Multiplies the accumulator with the contents of

memory specified by the zero page X address-

ing mode and stores the high byte of the result

on the stack and the low byte in the accumula-

tor.

No operation.

“Logical OR’s” the contents of memory and ac-

cumulator. The result is stored in the

accumulator.

“Logical OR’s” the contents of memory indi-

cated by index register X and contents of

memory specified by the addressing mode.

The result is stored in the memory specified by

index register X.

JMP

JSR

LDA

(Note 2)

LDM

LDX

LDY

LSR

MUL

NOP

ORA

(Note 1)

If addressing mode is ABS

PCL ← ADL

PCH ← ADH

If addressing mode is IND

PCL ← M (ADH, ADL)

PC

H

← M (AD

H

, AD

L

+ 1)

If addressing mode is ZP, IND

PCL ← M(00, ADL)

PCH ← M(00, ADL + 1)

M(S) ← PCH

S ← S – 1

M(S) ← PCL

S ← S – 1

After executing the above,

if addressing mode is ABS,

PCL ← ADL

PCH ← ADH

if addressing mode is SP,

PCL ← ADL

PCH ← FF

If addressing mode is ZP, IND,

PCL ← M(00, ADL)

PCH ← M(00, ADL + 1)

When T = 0

A ← M

When T = 1

M(X) ← M

M ← nn

X ← M

Y ← M

M(S) · A ← A ✕ M(zz + X)

S ← S – 1

PC ← PC + 1

When T = 0

A ← A V M

When T = 1

M(X) ← M(X) V M

A9

A2

A0

09

4A 2 1

A5

3C

A6

A4

46

05

3

4

3

3

5

3

2

3

2

2

2

2

EA 2 1

2

2

2

2

2

2

2

2

7 0

0

→

→

C

APPENDIX

3.10 Machine instructions

3-89

3806 GROUP USER’S MANUAL

Addressing mode

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0

Processor status register

NVTBDI ZC

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #

B5

B4

56

62

15

4C

20

AD

AE

AC

4E

0D

6C

A1

01

•

•

N

•

N

N

0

•

•

N

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Z

•

Z

Z

Z

•

•

Z

•

•

•

•

•

•

C

•

•

•

4

4

6

15

4

2

2

2

2

2

B6 4 2

3

6

4

4

4

6

4

3

3

3

3

3

3

3

BD

BC

5E

1D

5

5

7

5

B9

BE

19

5

5

5

3

3

3

3

3

3

3

53B2

02

4

7

2

2

6

6

2

2

B1

11

6

6

2

2

22 5 2

APPENDIX

3.10 Machine instructions

3-90 3806 GROUP USER’S MANUAL

Addressing mode

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP

OPn#OPn#OPn#OPn#OPn#OP n #

Saves the contents of the accumulator in

memory at the address indicated by the stack

pointer and decrements the contents of stack

pointer by 1.

Saves the contents of the processor status

register in memory at the address indicated by

the stack pointer and decrements the contents

of the stack pointer by 1.

Increments the contents of the stack pointer

by 1 and restores the accumulator from the

memory at the address indicated by the stack

pointer.

Increments the contents of stack pointer by 1

and restores the processor status register

from the memory at the address indicated by

the stack pointer.

Shifts the contents of the memory or accumu-

lator to the left by one bit. The high order bit is

shifted into the carry flag and the carry flag is

shifted into the low order bit.

Shifts the contents of the memory or accumu-

lator to the right by one bit. The low order bit is

shifted into the carry flag and the carry flag is

shifted into the high order bit.

Rotates the contents of memory to the right by

4 bits.

Returns from an interrupt routine to the main

routine.

Returns from a subroutine to the main routine.

Subtracts the contents of memory and

complement of carry flag from the contents of

accumulator. The results are stored into the

accumulator.

Subtracts contents of complement of carry flag

and contents of the memory indicated by the

addressing mode from the memory at the ad-

dress indicated by index register X. The

results are stored into the memory of the ad-

dress indicated by index register X.

Sets the specified bit in the accumulator or

memory to “1”.

Sets the contents of the carry flag to “1”.

Sets the contents of the decimal mode flag to

“1”.

Sets the contents of the interrupt disable flag

to “1”.

Sets the contents of the index X mode flag to

“1”.

PHA

PHP

PLA

PLP

ROL

ROR

RRF

RTI

RTS

SBC

(Note 1)

(Note 5)

SEB

SEC

SED

SEI

SET

M(S) ← A

S ← S – 1

M(S) ← PS

S ← S – 1

S ← S + 1

A ← M(S)

S ← S + 1

PS ← M(S)

S ← S + 1

PS ← M(S)

S ← S + 1

PCL ← M(S)

S ← S + 1

PCH ← M(S)

S ← S + 1

PCL ← M(S)

S ← S + 1

PCH ← M(S)

When T = 0

_

A ← A – M – C

When T = 1

_

M(X) ← M(X) – M – C

Ab or Mb ← 1

C ← 1

D ← 1

I ← 1

T ← 1

E9

2A

6A

26

66

82

E5

48

08

68

28

40

60

38

F8

78

32

7 0

←

←

C

←

7 0

→

→

3

3

4

4

6

6

2

2

2

2

1

1

1

1

1

1

1

1

1

1

22

2

2

1

1

0B

+

2i

5

5

8

3

2

2

2

2

0F

+

2i

21 52

7 0

C

→

→

APPENDIX

3.10 Machine instructions

3-91

3806 GROUP USER’S MANUAL

Addressing mode

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0

Processor status register

NVTBDI ZC

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #

36

76

F5

2E

6E

ED

•

•

N

N

N

•

•

N

•

•

•

•

•

•

•

•

•

•

•

•

V

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

•

•

•

•

•

•

•

•

•

•

•

•

•

1

•

•

•

Z

Z

Z

•

•

Z

•

•

•

•

•

•

•

•

C

C

•

•

C

•

1

•

•

•

6

6

4

2

2

2

6

6

4

3

3

3

3E

7E

FD

7

7

5

3

3

3F95 3 E16 2F16 2

(Value saved in stack)

(Value saved in stack)

APPENDIX

3.10 Machine instructions

3-92 3806 GROUP USER’S MANUAL

Addressing mode

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP

OPn#OPn#OPn#OPn#OPn#OP n #

Stores the contents of accumulator in memory.

Stops the oscillator.

Stores the contents of index register X in

memory.

Stores the contents of index register Y in

memory.

Transfers the contents of the accumulator to

index register X.

Transfers the contents of the accumulator to

index register Y.

Tests whether the contents of memory are “0”

or not.

Transfers the contents of the stack pointer to

index register X.

Transfers the contents of index register X to

the accumulator.

Transfers the contents of index register X to

the stack pointer.

Transfers the contents of index register Y to

the accumulator.

Stops the internal clock.

STA

STP

STX

STY

TAX

TAY

TST

TSX

TXA

TXS

TYA

WIT

M ← A

M ← X

M ← Y

X ← A

Y ← A

M = 0?

X ← S

A ← X

S ← X

A ← Y

42

AA

A8

BA

8A

9A

98

C2

85

86

84

64

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

4

4

4

3

2

2

2

2

Notes 1 : The number of cycles “n” is increased by 3 when T is 1.

2 : The number of cycles “n” is increased by 2 when T is 1.

3 : The number of cycles “n” is increased by 1 when T is 1.

4 : The number of cycles “n” is increased by 2 when branching has occurred.

5 : N, V, and Z flags are invalid in decimal operation mode.

APPENDIX

3.10 Machine instructions

3-93

3806 GROUP USER’S MANUAL

Addressing mode

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0

Processor status register

NVTBDI ZC

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #

95

94

•

•

•

•

N

N

N

N

N

•

N

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Z

Z

Z

Z

Z

•

Z

•

•

•

•

•

•

•

•

•

•

•

•

•

Addition

Subtraction

Logical OR

Logical AND

Logical exclusive OR

Negation

Shows direction of data flow

Index register X

Index register Y

Stack pointer

Program counter

Processor status register

8 high-order bits of program counter

8 low-order bits of program counter

8 high-order bits of address

8 low-order bits of address

FF in Hexadecimal notation

Immediate value

Memory specified by address designation of any ad-

dressing mode

Memory of address indicated by contents of index

register X

Memory of address indicated by contents of stack

pointer

Contents of memory at address indicated by ADH and

ADL, in ADH is 8 high-order bits and ADL is 8 low-or-

der bits.

Contents of address indicated by zero page ADL

1 bit of accumulator

1 bit of memory

Opcode

Number of cycles

Number of bytes

5

5

2

2

96 5 2

8D

8E

8C

5

5

5

3

3

3

9D639963 81729172

Implied addressing mode

Immediate addressing mode

Accumulator or Accumulator addressing mode

Accumulator bit relative addressing mode

Zero page addressing mode

Zero page bit relative addressing mode

Zero page X addressing mode

Zero page Y addressing mode

Absolute addressing mode

Absolute X addressing mode

Absolute Y addressing mode

Indirect absolute addressing mode

Zero page indirect absolute addressing mode

Indirect X addressing mode

Indirect Y addressing mode

Relative addressing mode

Special page addressing mode

Carry flag

Zero flag

Interrupt disable flag

Decimal mode flag

Break flag

X-modified arithmetic mode flag

Overflow flag

Negative flag

IMP

IMM

A

BIT, A

ZP

BIT, ZP

ZP, X

ZP, Y

ABS

ABS, X

ABS, Y

IND

ZP, IND

IND, X

IND, Y

REL

SP

C

Z

I

D

B

T

V

N

Symbol Contents Symbol Contents

+

–

V

V

–

–

←

X

Y

S

PC

PS

PCH

PCL

ADH

ADL

FF

nn

M

M(X)

M(S)

M(ADH, ADL)

M(00, ADL)

Ab

Mb

OP

n

#

V

APPENDIX

3.11 SFR memory map

3-94 3806 GROUP USER’S MANUAL

3.11 SFR memory map

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Port P8 (P8)

Port P8 direction register (P8D)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Serial I/O2 control register (SIO2CON)

Serial I/O2 register (SIO2)

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Prescaler 12 (PRE12)

Timer 1 (T1)

Timer 2 (T2)

Timer XY mode register (TM)

Prescaler X (PREX)

Timer X (TX)

Prescaler Y (PREY)

Timer Y (TY)

AD/DA control register (ADCON)

A-D conversion register (AD)

D-A1 conversion register (DA1)

D-A2 conversion register (DA2)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Interrupt control register 2 (ICON2)

APPENDIX

3.12 Pin configuration

3-95

3806 GROUP USER’S MANUAL

3.12 Pin configuration

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6N-A

80-pin plastic-molded QFP

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24 41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

P3

0

P3

1

P3

4

/φ

P3

5

/SYNC

P0

0

/AD

0

P0

3

/AD

3

P0

4

/AD

4

P0

5

/AD

5

P0

6

/AD

6

P0

7

/AD

7

P1

1

/AD

9

P1

2

/AD

10

P1

3

/AD

11

P1

4

/AD

12

P1

5

/AD

13

P1

6

/AD

14

P1

7

/AD

15

P6

2

/AN

2

P6

1

/AN

1

P6

0

/AN

0

P7

7

M38063M6-XXXFP

P7

6

P7

5

P7

4

P7

2

/S

CLK2

P7

1

/S

OUT2

P7

0

/S

IN2

P5

7

/DA

2

P5

0

P4

6

/S

CLK1

P4

5

/T

X

D

P4

4

/R

X

D

P4

3

/INT

1

P6

3

/AN

3

P6

4

/AN

4

P6

5

/AN

5

AV

SS

V

REF

V

CC

P8

0

P8

1

P8

2

P8

3

P8

4

P8

5

P8

6

P8

7

P4

2

/INT

0

CNV

SS

X

IN

X

OUT

V

SS

P2

7

/DB

7

P2

6

/DB

6

P2

5

/DB

5

P2

4

/DB

4

P2

3

/DB

3

P2

2

/DB

2

P2

1

/DB

1

P2

0

/DB

0

RESET

P7

3

/S

RDY2

P5

1

/INT

2

P5

5

/CNTR

1

P5

4

/CNTR

0

P5

3

/INT

4

P5

2

/INT

3

P5

6

/DA

1

P1

0

/AD

8

P0

1

/AD

1

P0

2

/AD

2

P4

7

/S

RDY1

P3

2

/ONW

P3

3

/RESET

OUT

P3

6

/WR

P3

7

/RD

P4

0

P4

1

P6

7

/AN

7

P6

6

/AN

6

APPENDIX

3.12 Pin configuration

3-96 3806 GROUP USER’S MANUAL

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6S-A/80P6D-A

80-pin plastic-molded QFP

P36/WR

P37/RD

P00/AD0

P01/AD1

P02/AD2

P03/AD3

P04/AD4

P05/AD5

P06/AD6

P07/AD7

P10/AD8

P11/AD9

P12/AD10

P13/AD11

P14/AD12

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41 P15/AD13

6

P60/AN0

P77

P76

P75

P74

P73/SRDY2

P72/SCLK2

P71/SOUT2

P70/SIN2

P57/DA2

P56/DA1

P55/CNTR1

P54/CNTR0

P53/INT4

P52/INT3

P51/INT2

P50

1

4

3

2

5

7

8

9

10

11

12

13

14

15

16

17

18

19

20

P47/SRDY1

P46/SCLK1

P45/TXD

68

80

79

78

77

76

75

74

73

72

71

69

67

66

65

70

P64/AN4

P63/AN3

P65/AN5

P66/AN6

AVSS

VREF

VCC

P85

63

62

61

P87

P31

64

21

23

22

24

30

25

27

28

29

31

34

35

36

Vss

P27/DB7

P26/DB6

33

32

26

P25/DB5

38

39

40

P24/DB4

P23/DB3

P22/DB2

37

P44/RXD

P43/INT1

XIN

P42/INT0

RESET

XOUT

CNVSS

P41

P30

P86

P84

P62/AN2

P61/AN1

M38063M6-XXXGP

M38063M6AXXXHP

P21/DB1

P20/DB0

P17/AD15

P16/AD14

P40

P32/ONW

P33/RESETOUT

P34/φ

P35/SYNC

P67/AN7

P83

P82

P81

P80

MITSUBISHI SEMICONDUCTORS

USER’S MANUAL

3806Group

Mar. First Edition 1996

Editioned by

Committee of editing of Mitsubishi Semiconductor USER’S MANUAL

Published by

Mitsubishi Electric Corp., Semiconductor Marketing Division

This book, or parts thereof, may not be reproduced in any form without permission

of Mitsubishi Electric Corporation.

©1996 MITSUBISHI ELECTRIC CORPORATION

1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan

3806 Group

User’s Manual