PIC18F6X2X/8X2X FLASH Microcontroller Programming Specification 1.0 DEVICE OVERVIEW 2.1 In High Voltage ICSP mode, PIC18F6X2X/8X2X devices require two programmable power supplies: one for VDD and one for MCLR/VPP. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 for additional hardware parameters. This document includes the programming specifications for the following devices: * * * * PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621 2.0 2.1.1 PROGRAMMING OVERVIEW OF THE PIC18F6X2X/8X2X LOW VOLTAGE ICSP PROGRAMMING In Low Voltage ICSP mode, PIC18F6X2X/8X2X devices can be programmed using a VDD source in the operating range. This only means that MCLR/VPP does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 for additional hardware parameters. PIC18F6X2X/8X2X devices can be programmed using either the high voltage In-Circuit Serial ProgrammingTM (ICSPTM) method, or the low voltage ICSP method. Both of these can be done with the device in the users' system. The low voltage ICSP method is slightly different than the high voltage method, and these differences are noted where applicable. This programming specification applies to PIC18F6X2X/8X2X devices in all package types. TABLE 2-1: Hardware Requirements 2.2 Pin Diagrams The pin diagrams for the PIC18F6X2X/8X2X family are shown in Figure 2-1 and Figure 2-2. The pin descriptions of these diagrams do not represent the complete functionality of the device types. Users should refer to the appropriate device data sheet for complete pin descriptions. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F6X2X/8X2X During Programming Pin Name Pin Name Pin Type Pin Description MCLR/VPP/RG5 VPP P Programming Enable VDD(2) VDD P Power Supply VSS(2) VSS P Ground AVDD(2) AVDD P Analog Power Supply AVSS(2) AVSS P Analog Ground RB5 PGM I Low Voltage ICSP Input when LVP Configuration bit equals `1'(1) RB6 PGC I Serial Clock RB7 PGD I/O Serial Data Legend: Note 1: 2: I = Input, O = Output, P = Power See Section 5.3 for more detail. All power supply (VDD/AVDD) and ground (VSS/AVSS) must be connected. 2003 Microchip Technology Inc. DS30499B-page 1 PIC18F6X2X/8X2X RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RD3/PSP3 RD2/PSP2 RD1/PSP1 VSS VDD RE6/P1B RE5/P1C RE4/P3B RE3/P3C RE2/CS/P2B 64-Pin TQFP RD0/PSP0 PIC18F6X2X FAMILY PIN DIAGRAM RE7/CCP2(1)/P2A(1) FIGURE 2-1: 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR/P2C RE0/RD/P2D RG0/CCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 1 2 3 4 RF4/AN9/C2IN- 5 6 7 8 9 10 11 12 13 14 RF3/AN8/C2IN+ RF2/AN7/C1OUT 15 16 RG3/CCP4/P3D RG5/MCLR/VPP RG4/CCP5/P1D VSS VDD RF7/SS RF6/AN11/C1INRF5/AN10/C1IN+/CVREF 48 47 RB0/INT0 RB1/INT1 46 45 RB2/INT2 44 43 42 PIC18F6525 PIC18F6621 41 40 39 38 37 36 35 34 33 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/P1A Note 1: RC7/RX1/DT1 RC6/TX1/CK1 RC0/T1OSO/T13CKI RA4/T0CKI RC1/T1OSI/CCP2(1)/P2A(1) RA5/AN4/LVDIN VDD VSS RA0/AN0 RA1/AN1 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD RF0/AN5 RF1/AN6/C2OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 The CCP2 pin placement depends on the CCP2MX fuse setting. DS30499B-page 2 2003 Microchip Technology Inc. PIC18F6X2X/8X2X FIGURE 2-2: PIC18F8X2X FAMILY PIN DIAGRAM RJ1/OE RJ0/ALE RD7/AD7/PSP7 RD6/AD6/PSP6 RD5/AD5/PSP5 RD4/AD4/PSP4 RD3/AD3/PSP3 RD2/AD2/PSP2 RD1/AD1/PSP1 VSS VDD RD0/AD0/PSP0 RE7/AD15/CCP2(1)/P2A(1) RE6/AD14/P1B(2) RE5/AD13/P1C(2) RE4/AD12/P3B(2) RE2/AD10/CS/P2B RE3/AD11/P3C(2) RH0/A16 RH1/A17 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18 RH3/A19 1 60 2 RE1/AD9/WR/P2C RE0/AD8/RD/P2D 3 59 58 RG0/CCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR/VPP RG4/CCP5/P1D VSS VDD RF7/SS RF6/AN11/C1INRF5/AN10/C1IN+/CVREF RF4/AN9/C2INRF3/AN8/C2IN+ RF2/AN7/C1OUT RH7/AN15/P1B(2) RH6/AN14/P1C(2) 57 56 55 4 5 6 7 8 9 10 11 12 13 14 15 16 54 53 52 PIC18F8525 PIC18F8621 51 50 49 48 47 46 45 44 43 42 41 17 18 19 20 RJ2/WRL RJ3/WRH RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2(1)/P2A(1) RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/P1A RJ7/UB RJ6/LB 2: RJ5/CE RJ4/BA0 RC7/RX1/DT1 RC6/TX1/CK1 RC0/T1OSO/T13CKI RA4/T0CKI RC1/T1OSI/CCP2(1)/P2A(1) RA5/AN4/LVDIN VDD VSS RA0/AN0 RA1/AN1 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD RF0/AN5 RF1/AN6/C2OUT RH5/AN13/P3B(2) Note 1: RH4/AN12/P3C(2) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 The CCP2 pin placement depends on the CCP2MX fuse and Processor mode settings. P1B, P1C, P3B, and P3C pin placement depends on the ECCPMUX fuse setting. 2003 Microchip Technology Inc. DS30499B-page 3 PIC18F6X2X/8X2X 2.3 Memory Map The code memory space extends from 0000h to 0FFFFh (64 Kbytes) in four 16-Kbyte blocks. Addresses 0000h through 07FFh, however, define a "Boot Block" region that is treated separately from Block 1. All of these blocks define code protection boundaries within the code memory space. In contrast, code memory panels are defined in 8-Kbyte boundaries. Panels are discussed in greater detail in Section 3.2. FIGURE 2-3: TABLE 2-2: Device PIC18F6525 PIC18F8525 PIC18F6621 PIC18F8621 IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) 000000h - 00BFFFh (48K) 000000h - 00FFFFh (64K) MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18F6X2X/8X2X DEVICES 000000h Code Memory 01FFFFh MEMORY SIZE/DEVICE Unimplemented Read as `0' 64 Kbytes (PIC18FX621) 48 Kbytes (PIC18FX525) Address Range Boot Block Boot Block 000000h 0007FFh Block 1 Block 1 000800h 003FFFh Block 2 Block 2 004000h 007FFFh 008000h Block 3 Block 3 00BFFFh 00C000h 1FFFFFh Block 4 00FFFFh Configuration and ID Space Unimplemented Read `0's Unimplemented Read `0's 01FFFFh 3FFFFFh Note: Sizes of memory areas not to scale. DS30499B-page 4 2003 Microchip Technology Inc. PIC18F6X2X/8X2X In addition to the code memory space, there are three blocks in the configuration and ID space that are accessible to the user through table reads and table writes. Their locations in the memory map are shown in Figure 2-4. Users may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses 200000h through 200007h. The ID locations read out normally, even after code protection is applied. Locations 300000h through 30000Dh are reserved for the configuration bits. These bits select various device options and are described in Section 5.0. These configuration bits read out normally, even after code protection. Locations 3FFFFEh and 3FFFFFh are reserved for the device ID bits. These bits may be used by the programmer to identify what device type is being programmed and are described in Section 5.0. These device ID bits read out normally, even after code protection. FIGURE 2-4: 2.3.1 MEMORY ADDRESS POINTER Memory in the address space 0000000h to 3FFFFFh is addressed via the Table Pointer register, which is comprised of three Pointer registers: * TBLPTRU, at RAM address 0FF8h * TBLPTRH, at RAM address 0FF7h * TBLPTRL, at RAM address 0FF6h TBLPTRU TBLPTRH TBLPTRL Addr[21:16] Addr[15:8] Addr[7:0] The 4-bit command, `0000' (Core Instruction), is used to load the Table Pointer prior to using many read or write operations. CONFIGURATION AND ID LOCATIONS FOR PIC18F6X2X/8X2X DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as `0' 1FFFFFh Configuration and ID Space 2FFFFFh ID Location 1 200000h ID Location 2 200001h ID Location 3 200002h ID Location 4 200003h ID Location 5 200004h ID Location 6 200005h ID Location 7 200006h ID Location 8 200007h CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h CONFIG3L 300004h CONFIG3H 300005h CONFIG4L 300006h CONFIG4H 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. 2003 Microchip Technology Inc. DS30499B-page 5 PIC18F6X2X/8X2X 2.4 High Level Overview of the Programming Process FIGURE 2-6: Figure 2-6 shows the high level overview of the programming process. First, a bulk erase is performed. Next, the code memory, ID locations, and data EEPROM are programmed. These memories are then verified to ensure that programming was successful. If no errors are detected, the configuration bits are then programmed and verified. HIGH LEVEL PROGRAMMING FLOW Start Perform Bulk Erase Program Memory 2.5 Entering High Voltage ICSP Program/Verify Mode Program IDs The High Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/VPP to VIHH (high voltage). Once in this mode, the code memory, data EEPROM, ID locations, and configuration bits can be accessed and programmed in serial fashion. Program Data The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. 2.5.1 Verify Program Verify IDs ENTERING LOW VOLTAGE ICSP PROGRAM/VERIFY MODE When the LVP configuration bit is `1' (see Section 5.3), the Low Voltage ICSP mode is enabled. Low Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic high on PGM, and then raising MCLR/VPP to VIH. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. Verify Data Program Configuration Bits Verify Configuration Bits The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. Done FIGURE 2-5: ENTERING HIGH VOLTAGE PROGRAM/VERIFY MODE P13 FIGURE 2-7: P15 P12 P1 ENTERING LOW VOLTAGE PROGRAM/ VERIFY MODE P12 VIH MCLR/VPP D110 MCLR/VPP VDD VIH VDD PGM PGD PGD PGC PGC PGD = Input DS30499B-page 6 PGD = Input 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 2.6 TABLE 2-3: Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC, and are Least Significant bit (LSb) first. 2.6.1 4-BIT COMMANDS Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command is shown MSb first. The command operand, or "Data Payload", is shown <MSB><LSB>. Figure 2-8 demonstrates how to serially present a 20-bit command/operand to the device. Core Instruction (Shift in16-bit instruction) 0000 Shift out TABLAT register 0010 Table Read 1000 Table Read, post-increment 1001 Table Read, post-decrement 1010 Table Read, pre-increment 1011 Table Write 1100 Table Write, post-increment by 2 1101 Table Write, post-decrement by 2 1110 Table Write, start programming 1111 TABLE 2-4: CORE INSTRUCTION SAMPLE COMMAND SEQUENCE 4-bit Command Data Payload 1101 3C 40 The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to setup registers as appropriate for use with other commands. FIGURE 2-8: 4-bit Command Description All instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-3. 2.6.2 COMMANDS FOR PROGRAMMING Core Instruction Table Write, post-increment by 2 TABLE WRITE, POST-INCREMENT TIMING (1101) P2 1 2 3 4 P2A P2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5A P5 P4 P3 PGD 1 0 1 1 0 0 0 0 4-bit Command 0 0 0 1 0 0 0 4 C 16-bit Data Payload 1 1 1 1 0 0 n n n n 3 Fetch Next 4-bit Command PGD = Input 2003 Microchip Technology Inc. DS30499B-page 7 PIC18F6X2X/8X2X 3.0 DEVICE PROGRAMMING 3.1 High Voltage ICSP Bulk Erase TABLE 3-2: 4-bit Data Command Payload Erasing code or data EEPROM is accomplished by writing an "erase option" to address 3C0004h. Code memory may be erased portions at a time, or the user may erase the entire device in one action. "Bulk Erase" operations will also clear any code protect settings associated with the memory block erased. Erase options are detailed in Table 3-1. TABLE 3-1: BULK ERASE COMMAND SEQUENCE 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 0000 0000 00 00 00 00 Core Instruction 3C F8 00 F7 04 F6 80 MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 80h TO 3C0004h to erase entire device. NOP Hold PGD low until erase completes. BULK ERASE OPTIONS Description Data Chip Erase 80h Erase Data EEPROM 81h Erase Boot Block 83h Erase Block 1 88h Erase Block 2 89h Erase Block 3 8Ah Erase Block 4 8Bh Erase Block 5 8Ch Erase Block 6 8Dh Erase Block 7 8Eh Erase Block 8 8Fh FIGURE 3-1: BULK ERASE FLOW Start Load Address Pointer to 3C0004h Write 80h To Erase Entire Device The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the NOP command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle but PGD must be held low. Delay P11+P10 Time Done The code sequence to erase the entire device is shown in Figure 3-2 and the flow chart is shown in Figure 3-1. Note: A bulk erase is the only way to reprogram code protect bits from an on-state to an off-state. FIGURE 3-2: BULK ERASE TIMING P10 1 2 3 4 2 1 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2 n n PGC PGD 0 0 1 1 4-bit Command P5 P5A P5 0 0 0 0 16-bit Data Payload 0 0 0 0 4-bit Command P5A 0 0 0 16-bit Data Payload 0 P11 0 0 0 0 4-bit Command Erase Time 16-bit Data Payload PGD = Input DS30499B-page 8 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 3.1.1 LOW VOLTAGE ICSP BULK ERASE When using low voltage ICSP, the part must be supplied by the voltage specified in parameter #D111 if a bulk erase is to be executed. All other bulk erase details as described above apply. If it is determined that a program memory erase must be performed at a supply voltage below the bulk erase limit, refer to the erase methodology described in Sections 3.1.2 and 3.2.2. If it is determined that a data EEPROM erase must be performed at a supply voltage below the bulk erase limit, follow the methodology described in Section 3.3 and write `1's to the array. 3.1.2 ICSP MULTI-PANEL SINGLE ROW ERASE Regardless of whether high or low voltage ICSP is used, it is possible to erase a single row (64 bytes of data) in all panels at once. For example, in the case of a 64-Kbyte device (8 panels), 512 bytes through 64 bytes in each panel can be erased simultaneously during each erase sequence. In this case, the offset of the erase within each panel is the same (see Figure 3-5). Multipanel single row erase is enabled by appropriately configuring the Programming Control register located at 3C0006h. The multi-panel single row erase duration is externally timed and is controlled by PGC. After a "Start Programming" command is issued (4-bit command, `1111'), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. The code sequence to erase a PIC18F6X2X/8X2X device is shown in Table 3-3. The flow chart shown in Figure 3-3 depicts the logic necessary to completely erase a PIC18F6X2X/8X2X device. The timing diagram that details the "Start Programming" command, and parameters P9 and P10 is shown in Figure 3-6. Note: 2003 Microchip Technology Inc. The TBLPTR register must contain the same offset value when initiating the programming sequence as it did when the write buffers were loaded. DS30499B-page 9 PIC18F6X2X/8X2X TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Direct access to config memory. 0000 0000 0000 8E A6 8C A6 84 A6 BSF BSF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN Step 2: Configure device for multi-panel writes. 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 3C F8 00 F7 06 F6 40 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write 3Ch TBLPTRU 00h TBLPTRH 06h TBLPTRL 40h to 3C0006h to enable multi-panel erase. BSF BCF CLRF CLRF CLRF EECON1, EEPGD EECON1, CFGS TBLPTRU TBLPTRH TBLPTRL Step 3: Direct access to code memory. 0000 0000 0000 0000 0000 8E 9C 6A 6A 6A A6 A6 F8 F7 F6 Step 4: Enable erase and erase single row of all panels at an offset. 0000 1111 0000 88 A6 <DummyLSB> <DummyMSB> 00 00 BSF EECON1, FREE Write 2 dummy bytes and start programming. NOP - hold PGC high for time P9. Step 5: Repeat step 4, with address pointer incremented by 64 until all panels are erased. FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW Start Addr = 0 Configure Device for Multi-Panel Erase Start Erase Sequence and hold PGC High Until Done Addr = Addr + 64 Delay P9 + P10 Time for Erase to Occur No All Panels Done? Yes Done DS30499B-page 10 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 3.2 Code Memory Programming Programming code memory is accomplished by first loading data into the appropriate write buffers and then initiating a programming sequence. Each panel in the code memory space (see Figure 2-3) has an 8-byte deep write buffer that must be loaded prior to initiating a write sequence. The actual memory write sequence takes the contents of these buffers and programs the associated EEPROM code memory. Typically, all of the program buffers are written in parallel (Multi-Panel Write mode). In other words, in the case of a 64-Kbyte device (8 panels with an 8-byte buffer per panel), 64 bytes will be simultaneously programmed during each programming sequence. In this case, the offset of the write within each panel is the same (see Figure 3-4). Multi-Panel Write mode is enabled by appropriately configuring the Programming Control register located at 3C0006h. 2003 Microchip Technology Inc. The programming duration is externally timed and is controlled by PGC. After a "Start Programming" command is issued (4-bit command, `1111'), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. The code sequence to program a PIC18F6X2X/8X2X device is shown in Table 3-4. The flow chart shown in Figure 3-5 depicts the logic necessary to completely write a PIC18F6X2X/8X2X device. The timing diagram that details the "Start Programming" command, and parameters P9 and P10, is shown in Figure 3-6. Note: The TBLPTR register must contain the same offset value when initiating the programming sequence as it did when the write buffers were loaded. DS30499B-page 11 PIC18F6X2X/8X2X FIGURE 3-4: ERASE AND WRITE BOUNDARIES Panel n 8-Byte Write Buffer TBLPTR<21:13> = (n - 1) TBLPTR<2:0> = 7 TBLPTR<2:0> = 6 TBLPTR<2:0> = 5 TBLPTR<2:0> = 4 TBLPTR<2:0> = 3 TBLPTR<2:0> = 2 TBLPTR<2:0> = 1 TBLPTR<2:0> = 0 Erase Region (64 bytes) Offset = TBLPTR<12:3> Offset = TBLPTR<12:6> Panel 3 8-Byte Write Buffer TBLPTR<21:13> = 2 TBLPTR<2:0> = 7 TBLPTR<2:0> = 6 TBLPTR<2:0> = 5 TBLPTR<2:0> = 4 TBLPTR<2:0> = 3 TBLPTR<2:0> = 2 TBLPTR<2:0> = 1 TBLPTR<2:0> = 0 Erase Region (64 bytes) Offset = TBLPTR<12:3> Offset = TBLPTR<12:6> Panel 2 8-Byte Write Buffer TBLPTR<21:13> = 1 TBLPTR<2:0> = 7 TBLPTR<2:0> = 6 TBLPTR<2:0> = 5 TBLPTR<2:0> = 4 TBLPTR<2:0> = 3 TBLPTR<2:0> = 2 TBLPTR<2:0> = 1 TBLPTR<2:0> = 0 Erase Region (64 bytes) Offset = TBLPTR<12:3> Offset = TBLPTR<12:6> Panel 1 8-Byte Write Buffer TBLPTR<21:13> = 0 TBLPTR<2:0> = 7 TBLPTR<2:0> = 6 TBLPTR<2:0> = 5 TBLPTR<2:0> = 4 TBLPTR<2:0> = 3 TBLPTR<2:0> = 2 TBLPTR<2:0> = 1 TBLPTR<2:0> = 0 Erase Region (64 bytes) Offset = TBLPTR<12:3> Offset = TBLPTR<12:6> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS30499B-page 12 2003 Microchip Technology Inc. PIC18F6X2X/8X2X TABLE 3-4: WRITE CODE MEMORY CODE SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Direct access to config memory. 0000 0000 0000 8E A6 8C A6 84 A6 BSF BSF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN Step 2: Configure device for multi-panel writes. 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 3C F8 00 F7 06 F6 40 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write 3Ch TBLPTRU 00h TBLPTRH 06h TBLPTRL 40h to 3C0006h to enable multi-panel writes. BSF BCF EECON1, EEPGD EECON1, CFGS MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes Step 3: Direct access to code memory. 0000 0000 8E A6 9C A6 Step 4: Load write buffer for Panel 1. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1100 0E <Addr[21:16]> 6E F8 0E <Addr[15:8]> 6E F7 0E <Addr[7:0]> 6E F6 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> Step 5: Repeat for Panel 2. Step 6: Repeat for all but the last panel (N - 1). Step 7: Load write buffer for last panel. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[15:8]> 6E F7 0E <Addr[7:0]> 6E F6 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 To continue writing data, repeat steps 2 through 5, where the address pointer is incremented by 8 in each panel at each iteration of the loop. 2003 Microchip Technology Inc. DS30499B-page 13 PIC18F6X2X/8X2X FIGURE 3-5: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Multi-Panel Writes Panel Base Address = (N - 1) x 2000h Addr = Panel Base Address + (8 x LoopCount) Load 8 Bytes to Panel N Write Buffer at <Addr> N=N+1 All Panel Buffers Written? No Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Hold PGC High Until Done Delay P9+P10 Time for Write to Occur All Locations Done? No Yes Done FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P10 1 2 3 4 1 3 2 4 5 6 15 16 1 2 3 4 PGC 3 2 P9 P5A P5 PGD 1 1 1 1 1 4-bit Command n n n n n n n n 16-bit Data Payload 0 0 0 0 4-bit Command 0 Programming Time 0 0 16-bit Data Payload PGD = Input DS30499B-page 14 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 3.2.1 SINGLE PANEL PROGRAMMING The programming example presented in Section 3.2 utilizes multi-panel programming. This technique greatly decreases the total amount of time necessary to completely program a device and is the recommended method of completely programming a device. There may be situations, however, where it is advantageous to limit writes to a single panel. In such cases, the user only needs to disable the multi-panel write feature of the device by appropriately configuring the Programming Control register located at 3C0006h. The single panel that will be written will automatically be enabled based on the value of the Table Pointer. Note: 3.2.2 Even though multi-panel writes are disabled, the user must still fill the 8-byte write buffer for the given panel. MODIFYING CODE MEMORY All of the programming examples up to this point have assumed that the device has been bulk erased prior to programming (see Section 3.1). It may be the case, however, that the user wishes to modify only a section of an already programmed device. The minimum amount of data that can be written to the device is 8 bytes. This is accomplished by placing the device in Single Panel Write mode (see Section 3.2.1), loading the 8-byte write buffer for the panel, and then initiating a write sequence. In this case, however, it is assumed that the address space to be written already has data in it (i.e., it is not blank). 2003 Microchip Technology Inc. The minimum amount of code memory that may be erased at a given time is 64 bytes. Again, the device must be placed in Single Panel Write mode. The EECON1 register must then be used to erase the 64-byte target space prior to writing the data. When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g., erases), and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order to erase the program space being pointed to by the Table Pointer. The erase sequence is initiated by the setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit be set only when absolutely necessary. To help prevent inadvertent writes when using the EECON1 register, EECON2 is used to "enable" the WR bit. This register must be sequentially loaded with 55h and then AAh, immediately prior to asserting the WR bit in order for the write to occur. The erase will begin on the falling edge of the 4th PGC after the WR bit is set. After the erase sequence terminates, PGC must still be held low for the time specified by parameter #P10 to allow high voltage discharge of the memory array. DS30499B-page 15 PIC18F6X2X/8X2X TABLE 3-5: MODIFYING CODE MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to config memory. 0000 0000 8E A6 8C A6 BSF BSF EECON1, EEPGD EECON1, CFGS Step 2: Configure device for single panel writes. 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 3C F8 00 F7 06 F6 00 MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 06h MOVWF TBLPTRL Write 00h to 3C0006h to enable single-panel writes. Step 3: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS Step 4: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[8:15]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL Step 5: Enable memory writes and setup an erase. 0000 0000 84 A6 88 A6 BSF BSF EECON1, WREN EECON1, FREE MOVLW MOVWF MOVLW MOVWF 55h EECON2 0AAh EECON2 BSF NOP EECON1, WR Step 6: Perform required sequence. 0000 0000 0000 0000 0E 6E 0E 6E 55 A7 AA A7 Step 7: Initiate erase. 0000 0000 82 A6 00 00 Step 8: Wait for P11+P10. Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 To continue writing data, repeat Step 9, where the address pointer is incremented by 8 at each iteration of the loop. Step 10: Disable writes. 0000 94 A6 DS30499B-page 16 BCF EECON1, WREN 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 3.3 FIGURE 3-7: Data EEPROM Programming PROGRAM DATA FLOW Data EEPROM is accessed one byte at a time via an address pointer (register pair EEADR:EEADRH) and a data latch (EEDATA). Data EEPROM is written by loading EEADR:EEADRH with the desired memory location, EEDATA with the data to be written, and initiating a memory write by appropriately configuring the EECON1 and EECON2 registers. A byte write automatically erases the location and writes the new data (erase-before-write). Start Set Address Set Data Enable Write When using the EECON1 register to perform a data EEPROM write, both the EEPGD and CFGS bits must be cleared (EECON1<7:6> = 00). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort, and this must be done prior to initiating a write sequence. The write sequence is initiated by setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit be set only when absolutely necessary. Unlock Sequence 55h - EECON2 AAh - EECON2 Start Write Sequence To help prevent inadvertent writes when using the EECON1 register, EECON2 is used to "enable" the WR bit. This register must be sequentially loaded with 55h and then AAh immediately prior to asserting the WR bit in order for the write to occur. Yes No Done ? The write begins on the falling edge of the 4th PGC after the WR bit is set. It ends when the WR bit is cleared by hardware. Yes Done After the programming sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. FIGURE 3-8: No WR bit Clear? DATA EEPROM WRITE TIMING P10 1 2 3 4 2 1 1 15 16 2 PGC P5A P5 PGD 0 0 0 P11A 0 4-bit Command n 16-bit Data Payload Poll WR bit, Repeat Until Clear (see below) BSF EECON1, WR n PGD = Input 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 PGC P5 P5 P5A P5A Poll WR bit PGD 0 0 0 0 4-bit Command 0 MOVF EECON1, W, 0 PGD = Input 2003 Microchip Technology Inc. 0 0 0 4-bit Command MOVWF TABLAT Shift Out Data (see Figure 4-6) PGD = Output DS30499B-page 17 PIC18F6X2X/8X2X TABLE 3-6: PROGRAMMING DATA MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM address pointer. 0000 0000 0000 0000 0E 6E OE 6E <Addr> A9 <AddrH> AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH MOVLW MOVWF <Data> EEDATA BSF EECON1, WREN MOVLW MOVWF MOVLW MOVWF 0X55 EECON2 0XAA EECON2 BSF EECON1, WR Step 3: Load the data to be written. 0000 0000 0E <Data> 6E A8 Step 4: Enable memory writes. 0000 84 A6 Step 5: Perform required sequence. 0000 0000 0000 0000 0E 6E 0E 6E 55 A7 AA A7 Step 6: Initiate write. 0000 82 A6 Step 7: Poll WR bit, repeat until the bit is clear. 0000 0000 0010 50 A6 6E F5 <LSB><MSB> MOVF EECON1, W, 0 MOVWF TABLAT Shift out data(1) Step 8: Disable writes. 0000 94 A6 BCF EECON1, WREN Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. DS30499B-page 18 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 3.4 ID Location Programming Note: The ID locations are programmed much like the code memory, except that multi-panel writes must be disabled. The single panel that will be written will automatically be enabled, based on the value of the Table Pointer. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally even after code protection. TABLE 3-7: Even though multi-panel writes are disabled, the user must still fill the 8-byte data buffer for the panel. Table 3-7 demonstrates the code sequence required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.2, "Modifying Code Memory". As with code memory, the ID locations must be erased before modified. WRITE ID SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Direct access to config memory. 0000 0000 8E A6 8C A6 BSF BSF EECON1, EEPGD EECON1, CFGS Step 2: Configure device for single panel writes. 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 3C F8 00 F7 06 F6 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write 3Ch TBLPTRU 00h TBLPTRH 06h TBLPTRL 00h to 3C0006h to enable single panel writes. BSF BCF EECON1, EEPGD EECON1, CFGS Step 3: Direct access to code memory. 0000 0000 8E A6 9C A6 Step 4: Load write buffer. Panel will be automatically determined by address. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> 00 00 2003 Microchip Technology Inc. MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 DS30499B-page 19 PIC18F6X2X/8X2X 3.5 Boot Block Programming 3.6 The Boot Block segment is programmed in exactly the same manner as the ID locations (see Section 3.4). Multi-panel writes must be disabled so that only addresses in the range 0000h to 07FFh will be written. The code sequence detailed in Table 3-7 should be used, except that the address data used in "Step 2" will be in the range 000000h to 0007FFh. Configuration Bits Programming Unlike code memory, the configuration bits are programmed a byte at a time. The "Table Write, Begin Programming" 4-bit command (1111) is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive configuration locations is shown in Table 3-8. Note: TABLE 3-8: Execute four NOPs between configuration byte programming. every SET ADDRESS POINTER TO CONFIGURATION LOCATION 4-bit Command Data Payload Core Instruction Step 1: Direct access to config memory. 0000 0000 8E A6 8C A6 BSF BSF EECON1, EEPGD EECON1, CFGS GOTO 100000h Step 2: Position the program counter(1). 0000 0000 EF 00 F8 00 Step 3(2): Set Table Pointer for config byte to be written. Write even/odd addresses. 0000 0000 0000 0000 0000 0000 1111 0000 0000 1111 0000 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 <LSB><MSB ignored> 00 00 2A F6 <LSB ignored><MSB> 00 00 MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 Step 4: Execute four NOPs. 0000 0000 0000 0000 Note 1: 2: 00 00 00 00 00 00 00 00 If the code protection bits are programmed while the program counter resides in the same block, then the interaction of code protection logic may prevent further table write. To avoid this situation, move the program counter outside the code protection area (e.g., GOTO 100000h). Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration bits. Always write all the configuration bits before enabling the write protection for configuration bits. DS30499B-page 20 2003 Microchip Technology Inc. PIC18F6X2X/8X2X FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9 Time for Write Delay P9 Time for Write Execute four NOPs Execute four NOPs Done Done 2003 Microchip Technology Inc. DS30499B-page 21 PIC18F6X2X/8X2X 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations, and Configuration Bits The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer pointer by one, pointing to the next byte in code memory for the next read. Code memory is accessed one byte at a time via the 4-bit command, `1001' (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) is loaded into the Table Latch and then serially output on PGD. TABLE 4-1: This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the ID and Configuration registers. READ CODE MEMORY SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Set Table Pointer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory into Table Latch and then shift out on PGD, LSb to MSb. 1001 00 00 FIGURE 4-1: TBLRD *+ TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001) 1 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 1 16 2 3 4 PGC P5 P5A P6 P14 PGD 1 0 0 LSb 1 1 2 3 4 5 Shift Data Out PGD = Input DS30499B-page 22 PGD = Output 6 MSb n n n n Fetch Next 4-bit Command PGD = Input 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 4.2 Verify Code Memory and ID locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer's buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer's buffer. Refer to Section 4.1 for implementation details of reading code memory. FIGURE 4-2: The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer beyond the code memory space. In a 64-Kbyte device, for example, a postincrement read of address FFFFh will wrap the Table Pointer back to 0000h, rather than point to unimplemented address 10000h. VERIFY CODE MEMORY FLOW Start Set Pointer = 0 Set Pointer = 200000h Read Low Byte Read Low Byte Read High Byte Read High byte Does Word = Expect Data? Does No Word = Expect Data? Failure, Report Error Yes No All Code Memory Verified? Yes No Failure, Report Error Yes No All ID Locations Verified? Yes Done 2003 Microchip Technology Inc. DS30499B-page 23 PIC18F6X2X/8X2X 4.3 FIGURE 4-3: Verify Configuration Bits READ DATA EEPROM FLOW A configuration address may be read and output on PGD via the 4-bit command, `1001'. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer's memory for verification. Refer to Section 4.1 for implementation details of reading configuration data. 4.4 Start Set Address Read Byte Read Data EEPROM Memory Data EEPROM is accessed one byte at a time via an address pointer (register pair EEADR:EEADRH) and a data latch (EEDATA). Data EEPROM is read by loading EEADR:EEADRH with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register. The data will be loaded into EEDATA, where it may be serially output on PGD via the 4-bit command, `0010' (Shift Out Data Holding register). A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-4). Move to TABLAT Shift Out Data No Done ? Yes Done The command sequence to read a single byte of data is shown in Table 4-2. TABLE 4-2: READ DATA EEPROM MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM address pointer. 0000 0000 0000 0000 0E 6E OE 6E <Addr> A9 <AddrH> AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH BSF EECON1, RD Step 3: Initiate a memory read. 0000 80 A6 Step 4: Load data into the Serial Data Holding register. 0000 0000 0010 Note 1: 50 A8 6E F5 <LSB><MSB> MOVF EEDATA, W, 0 MOVWF TABLAT Shift Out Data(1) The <LSB> is undefined. The <MSB> is the data. DS30499B-page 24 2003 Microchip Technology Inc. PIC18F6X2X/8X2X FIGURE 4-4: 1 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 1 2 3 4 PGC P5 P5A P6 P14 PGD 0 1 0 LSb 1 0 2 3 4 5 6 Shift Data Out PGD = Input 4.5 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command, `0000') and then output on PGD via the 4-bit command, `0010' (Shift Out Data Holding register). The result may then be immediately compared to the appropriate data in the programmer's memory for verification. Refer to Section 4.4 for implementation details of reading data EEPROM. 4.6 Blank Check The term "Blank Check" means to verify that the device has no programmed memory cells. All memories must be verified: code memory, data EEPROM, ID locations, and configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. n MSb n n Fetch Next 4-bit Command PGD = Output FIGURE 4-5: n PGD = Input BLANK CHECK FLOW Start Blank Check Device Is Device Blank? Yes Continue No Abort A "blank" or "erased" memory cell will read as a `1'. So, "Blank Checking" a device merely means to verify that all bytes read as FFh except the configuration bits. Unused (reserved) configuration bits will read `0' (programmed). Refer to Table 5-2 for blank configuration expect data for the various PIC18F6X2X/8X2X devices. Given that "Blank Checking" is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 and Section 4.2 for implementation details. 2003 Microchip Technology Inc. DS30499B-page 25 PIC18F6X2X/8X2X 5.0 CONFIGURATION WORD 5.3 The PIC18F6X2X/8X2X devices have several configuration words. These bits can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting configuration words. These bits may be read out normally even after read or code protected. 5.1 The LVP bit in Configuration register, CONFIG4L, enables low voltage ICSP programming. The LVP bit defaults to a `1' from the factory. If Low Voltage Programming mode is not used, the LVP bit can be programmed to a `0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed by entering the High Voltage ICSP mode, where MCLR/VPP is raised to VIHH. Once the LVP bit is programmed to a `0', only the high voltage ICSP mode is available and only the high voltage ICSP mode can be used to program the device. ID Locations A user may store identification information (ID) in eight ID locations mapped in 200000h:200007h. It is recommended that the Most Significant nibble of each ID be 0Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. 5.2 Low Voltage Programming (LVP) Bit Note 1: The normal ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP pin. Device ID Word The device ID word for the PIC18F6X2X/8X2X is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally even after code or read protected. 2: While in Low Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O. 3: If the device Master Clear is disabled, verify that either of the following is done to ensure proper entry into ICSP mode: a) disable Low Voltage Programming (CONFIG4L<2> = 0); or b) make certain that RB5/PGM is held low during entry into ICSP. TABLE 5-1: DEVICE ID VALUE Device ID Value Device Note: DEVID2 DEVID1 18F6525 0Ah 111x xxxx 18F6621 0Ah 101x xxxx 18F8525 0Ah 110x xxxx 18F8621 0Ah 100x xxxx The `x's in DEVID1 contain the device revision code. DS30499B-page 26 2003 Microchip Technology Inc. PIC18F6X2X/8X2X TABLE 5-2: PIC18F6X2X/8X2X CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 0010 1111 300001h CONFIG1H -- -- OSCSEN -- FOSC3 FOSC2 FOSC1 FOSC0 300002h CONFIG2L -- -- -- -- BORV1 BORV0 BODEN PWRTEN 0000 1111 300003h CONFIG2H -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 0001 1111 PM1 PM0 1000 0011 300004h(1) CONFIG3L WAIT -- -- -- -- -- 300005h CONFIG3H MCLRE(3) -- -- -- -- -- 300006h CONFIG4L DEBUG -- -- -- -- LVP -- STVREN 1000 0101 300008h CONFIG5L -- -- -- -- CP3(2) CP2 CP1 CP0 0000 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 1100 0000 30000Ah CONFIG6L -- -- -- -- WRT3(2) WRT2 WRT1 WRT0 0000 1111 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 1110 0000 EBTR2 EBTR1 EBTR0 0000 1111 -- -- -- 0100 0000 30000Ch CONFIG7L -- -- -- -- EBTR3(2) 30000Dh CONFIG7H -- EBTRB -- -- -- ECCPMUX(1) CCP2MX 1000 0011 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1 3FFFFFh DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1 Legend: Note 1: 2: 3: DEVID2 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Unimplemented in PIC18F6X2X devices; maintain this bit set. Unimplemented in PIC18FX525 devices; maintain this bit set. If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2003 Microchip Technology Inc. DS30499B-page 27 PIC18F6X2X/8X2X TABLE 5-3: Bit Name PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS Configuration Words Description OSCEN CONFIG1H Low Power System Clock Option (Timer1) Enable bit 1 = Disabled 0 = Timer1 oscillator system clock option enabled FOSC3:FOSC0 CONFIG1H Oscillator Selection bits 1111 = RC oscillator w/ OSC2 configured as RA6 1110 = HS oscillator w/ s/w enabled PLL 1101 = EC w/ OSC2 configured as RA6 and s/w enabled PLL 1100 = EC w/ OSC2 configured as RA6 and PLL enabled 1011 = Reserved; do not use 1010 = Reserved; do not use 1001 = Reserved; do not use 1000 = Reserved; do not use 0111 = RC oscillator w/ OSC2 configured as RA6 0110 = HS oscillator w/ PLL enabled 0101 = EC w/ OSC2 configured as RA6 0100 = EC w/ OSC2 configured as `divide-by-4 clock output' 0011 = RC oscillator w/ OSC2 configured as `divide-by-4 clock output' 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOREN CONFIG2L Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRTEN CONFIG2L Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: 2: 3: Unimplemented in PIC18F6X2X devices; maintain this bit set. Unimplemented in PIC18FX525 devices; maintain this bit set. If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. DS30499B-page 28 2003 Microchip Technology Inc. PIC18F6X2X/8X2X TABLE 5-3: PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Bit Name Configuration Words Description WDTPS3:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4,096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN CONFIG2H Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) WAIT(1) CONFIG3L External Bus Data Wait Enable bit 1 = Wait selections unavailable 0 = Wait selections determined by WAIT1:WAIT0 bits of MEMCON register PM1:PM0(1) CONFIG3L Processor Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode MCLRE(3) CONFIG3H MCLR Enable bit 1 = MCLR pin enabled, RG5 disabled 0 = RG5 input pin enabled, MCLR disabled ECCPMUX(1) CONFIG3H ECCP Mux bit 1 = Enhanced CCP1 (P1B/P1C) and enhanced CCP3 (P3B/P3C) PWM outputs are multiplexed onto RE6 through RE3 0 = Enhanced CCP1 (P1B/P1C) and enhanced CCP3 (P3B/P3C) PWM outputs are multiplexed onto RH7 through RH4 CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RE7 in Microcontroller mode; CCP2 input/output is multiplexed with RB3 in Extended Microcontroller mode, Microprocessor or Microprocessor w/ Boot Block mode Note 1: 2: 3: Unimplemented in PIC18F6X2X devices; maintain this bit set. Unimplemented in PIC18FX525 devices; maintain this bit set. If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2003 Microchip Technology Inc. DS30499B-page 29 PIC18F6X2X/8X2X TABLE 5-3: Bit Name PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Configuration Words Description DEBUG CONFIG4L Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger enabled LVP CONFIG4L Low Voltage Programming Enable bit 1 = Low voltage programming enabled 0 = Low voltage programming disabled STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit 1 = Stack overflow/underflow will cause RESET 0 = Stack overflow/underflow will not cause RESET CP0 CONFIG5L Code Protection bits (code memory area 0800h - 3FFFh) 1 = Code memory not code protected 0 = Code memory code protected CP1 CONFIG5L Code Protection bits (code memory area 4000h - 7FFFh) 1 = Code memory not code protected 0 = Code memory code protected CP2 CONFIG5L Code Protection bits (code memory area 8000h - BFFFh) 1 = Code memory not code protected 0 = Code memory code protected CP3(2) CONFIG5L Code Protection bits (code memory area C000h - FFFFh) 1 = Code memory not code protected 0 = Code memory code protected CPD CONFIG5H Code Protection bits (data EEPROM) 1 = Data EEPROM not code protected 0 = Data EEPROM code protected CPB CONFIG5H Code Protection bits (boot block, memory area 0000h - 07FFh) 1 = Boot block not code protected 0 = Boot block code protected WRT0 CONFIG6L Table Write Protection bit (code memory area 0800h - 3FFFh) 1 = Code memory not write protected 0 = Code memory write protected WRT1 CONFIG6L Table Write Protection bit (code memory area 4000h - 7FFFh) 1 = Code memory not write protected 0 = Code memory write protected WRT2 CONFIG6L Table Write Protection bit (code memory area 8000h - BFFFh) 1 = Code memory not write protected 0 = Code memory write protected WRT3(2) CONFIG6L Table Write Protection bit (code memory area C000h - FFFFh) 1 = Code memory not write protected 0 = Code memory write protected Note 1: 2: 3: Unimplemented in PIC18F6X2X devices; maintain this bit set. Unimplemented in PIC18FX525 devices; maintain this bit set. If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. DS30499B-page 30 2003 Microchip Technology Inc. PIC18F6X2X/8X2X TABLE 5-3: Bit Name PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Configuration Words Description WRTD CONFIG6H Table Write Protection bit (data EEPROM) 1 = Data EEPROM not write protected 0 = Data EEPROM write protected WRTB CONFIG6H Table Write Protection bit (boot block, memory area 0000h - 07FFh) 1 = Boot block not write protected 0 = Boot block write protected WRTC CONFIG6H Table Write Protection bit (Configuration registers) 1 = Configuration registers not write protected 0 = Configuration registers write protected EBTR0 CONFIG7L Table Read Protection bit (code memory area 0800h - 3FFFh) 1 = Code memory not protected from table reads executed in other blocks 0 = Code memory protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (code memory area 4000h - 7FFFh) 1 = Code memory not protected from table reads executed in other blocks 0 = Code memory protected from table reads executed in other blocks EBTR2 CONFIG7L Table Read Protection bit (code memory area 8000h - BFFFh) 1 = Code memory not protected from table reads executed in other blocks 0 = Code memory protected from table reads executed in other blocks EBTR3(2) CONFIG7L Table Read Protection bit (code memory area C000h - FFFFh) 1 = Code memory not protected from table reads executed in other blocks 0 = Code memory protected from table reads executed in other blocks EBTRB CONFIG7H Table Read Protection bit (boot block, memory area 0000h - 07FFh) 1 = Boot block not protected from table reads executed in other blocks 0 = Boot block protected from table reads executed in other blocks DEV10:DEV3 DEVID2 Device ID bits These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. DEV2:DEV0 DEVID1 Device ID bits These bits are used with the DEV10:DEV3 bits in the DEVID2 register to identify part number. REV4:REV0 DEVID1 These bits are used to indicate the revision of the device. Note 1: 2: 3: Unimplemented in PIC18F6X2X devices; maintain this bit set. Unimplemented in PIC18FX525 devices; maintain this bit set. If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2003 Microchip Technology Inc. DS30499B-page 31 PIC18F6X2X/8X2X 5.4 Embedding Configuration Word Information in the HEX File To allow portability of code, a PIC18F6X2X/8X2X programmer is required to read the configuration word locations from the HEX file. If configuration word information is not present in the HEX file, then a simple warning message should be issued. Similarly, while saving a HEX file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 5.5 Embedding Data EEPROM Information In the HEX File To allow portability of code, a PIC18F6X2X/8X2X programmer is required to read the data EEPROM information from the HEX file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a HEX file, all data EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. 5.6 Checksum Computation The checksum is calculated by summing the following: * The contents of all code memory locations * The configuration word, appropriately masked * ID locations The Least Significant 16 bits of this sum are the checksum. Table 5-4 (pages 33 through 34) describes how to calculate the checksum for each device. Note: The checksum calculation differs depending on the code protect setting. Since the code memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire code memory can simply be read and summed. The configuration word and ID locations can always be read. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. DS30499B-page 32 2003 Microchip Technology Inc. PIC18F6X2X/8X2X TABLE 5-4: CHECKSUM COMPUTATION Code Protect Device Checksum None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+ SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0000)+ (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040) 4642 4598 Boot Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) 4E12 4DC7 C60F C5C4 (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) 060B 615 None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ SUM(C000:FFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0000)+ (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040) 0642 0598 Boot Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+SUM(C000:FFFF)+ (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) 0E0E 0DC3 860B 85C0 05FF 0609 PIC18F6525 Boot/ SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ Block1/ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0000)+ Block2 (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)+ SUM(IDs) All PIC18F6621 Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+(CONFIG1L & 0000)+ Block1/ (CONFIG1H & 002F)+(CONFIG2L & 000F)+(CONFIG2H & 001F)+ Block2 (CONFIG3L & 0000)+(CONFIG3H & 0083)+(CONFIG4L & 0085)+ (CONFIG4H & 0000)+(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+ (CONFIG6L & 00FF)+(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+ (CONFIG7H & 0040)+SUM(IDs) All Legend: 0xAA at 0 Blank and Max Value Address Item CFGW SUM[a:b] SUM_ID + & (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2003 Microchip Technology Inc. DS30499B-page 33 PIC18F6X2X/8X2X TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED) Code Protect Device 0xAA at 0 Blank and Max Value Address Checksum None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+ SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+ (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040) 46C5 461B Boot Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0083)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) 4EA0 4E46 Boot/ SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ C69D Block1/ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+ Block2 (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) C643 PIC18F8525 All (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0083)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) 0699 0694 None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ SUM(C000:FFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+ (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040) 06C5 061B Boot Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+ SUM(C000:FFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ (CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+ (CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+ (CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+ (CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)+ SUM(IDs) 0E9C 0E42 8699 863F 068D 0688 PIC18F8621 Boot/ SUM(8000:BFFF)+SUM(C000:FFFF)+(CONFIG1L & 0000)+ Block1/ (CONFIG1H & 002F)+(CONFIG2L & 000F)+(CONFIG2H & 001F)+ Block2 (CONFIG3L & 0083)+(CONFIG3H & 0083)+(CONFIG4L & 0085)+ (CONFIG4H & 0000)+(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+ (CONFIG6L & 00FF)+(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+ (CONFIG7H & 0040)+SUM(IDs) All Legend: Item CFGW SUM[a:b] SUM_ID + & DS30499B-page 34 (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+ (CONFIG2H & 001F)+(CONFIG3L & 0083)+(CONFIG3H & 0083)+ (CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+ (CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+ (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25C is recommended Param No. D110 Sym VIHH D110A VIHL D111 VDD Characteristic High Voltage Programming Voltage on MCLR/ VPP Low Voltage Programming Voltage on MCLR/ VPP Supply Voltage During Programming Programming Current on MCLR/VPP Supply Current During Programming Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Capacitive Loading on I/O pin (PGD) D112 D113 D031 D041 D080 D090 IPP IDDP VIL VIH VOL VOH D012 CIO P1 TR P2 TPGC P2A TPGCL Serial Clock (PGC) Low Time P2B TPGCH Serial Clock (PGC) High Time Units 9.00 13.25 V 2.00 5.50 V 2.00 5.50 V Normal programming 4.50 5.50 V Bulk erase operations -- -- VSS 0.8 VDD -- VDD - 0.7 -- 300 10 0.2 VDD VDD 0.6 -- 50 A mA V V V V pF IOL = 8.5 mA @ 4.5V IOH = -3.0 mA @ 4.5V To meet AC specifications -- 1.0 s (Note 1) 100 1 -- -- ns s VDD = 5.0V VDD = 2.0V 40 400 40 400 -- -- -- -- ns ns ns ns VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V 15 -- ns Input Data Hold Time from PGC Delay between 4-bit Command and Command Operand Tdly1a Delay between 4-bit Command Operand and next 4-bit Command 15 40 -- -- ns ns 40 -- ns 20 -- ns 1 5 -- -- ms s 5 -- ms 4 -- ms 2 -- s 100 -- ns 10 -- ns 2 -- s Tset1 Thld1 Tdly1 P11A Tdrwt Delay between Last PGC of Command Byte to First PGC of Read of Data Word PGC High Time (minimum programming time) PGC Low Time after Programming (high voltage discharge time) Delay to allow Self-Timed Data Write or Bulk Erase to occur Data Write Polling Time P12 Thld2 Input Data Hold Time from MCLR/VPP P13 Tset2 VDD Setup Time to MCLR/VPP P14 Tvalid Data Out Valid from PGC P15 Tset3 P6 Tdly2 P9 P10 Tdly5 Tdly6 P11 Tdly7 Note 1: Max Input Data Setup Time to Serial Clock P3 P4 P5 P5A MCLR/VPP Rise Time to enter Program/Verify mode Serial Clock (PGC) Period Min PGM Setup Time to MCLR/VPP Conditions Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL, and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period, and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2003 Microchip Technology Inc. DS30499B-page 35 PIC18F6X2X/8X2X NOTES: DS30499B-page 36 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. 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