2003 Microchip Technology Inc. DS30499B-page 1
PIC18F6X2X/8X2X
1.0 DEVICE OVERVIEW
This docume nt includes the program ming sp ecifica t ions
for the following devices :
• PIC18F6525
• PIC18F6621
• PIC18F8525
• PIC18F8621
2.0 PROGRAMMING OVERVIEW
OF THE PIC18F6 X2X /8X 2X
PIC18F6 X2X/8 X2X dev ic es c an be p rogra mm ed u sin g
either th e high vo lt a ge In-C irc ui t Ser ial Prog ram mi ngTM
(ICSPTM) method, or the low voltage ICSP method.
Both of these c an be d one w i th the de vi ce in t he us ers ’
system. The low voltage ICSP m etho d is sli ght ly dif f er-
ent than the high voltage method, and these differ-
ences are noted where applicable. This programming
specification applies to PIC18F6X2X/8X2X devices in
all package types.
2.1 Hardware Requirements
In High Voltage ICSP mode, PIC18F6X2X/8X2X
devices require two programmable power supplies:
one for VDD and one for MCLR/VPP. Both supplies
should have a minimum resolution of 0.25V. Refer to
Section 6.0 for additional hardware parameters.
2.1.1 LOW VOLTAGE ICSP
PROGRAMMING
In Low Voltage ICSP mode, PIC18F6X2X/8X2X
device s can be prog ramme d using a VDD source in the
operat ing range. This only means that MCL R/VPP does
not have to be brought to a different voltage, but can
instead be lef t at the norm al operati ng volt age. Refer to
Section 6.0 for additional hardware parameters.
2.2 Pin Diagrams
The pin di agrams for the PIC 18F6X2X/8 X2X family are
shown in Figure 2-1 and Figure 2-2. The pin descrip-
tions of these diagrams do not represent the complete
functionality of the device types. Users should refer to
the appropriate device data sheet for complete pin
descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F6X2X/8X2X
Pin Name During Programming
Pin Name Pin Type Pin Description
MCLR/VPP/RG5 VPP P Programming Enable
VDD(2) VDD P Power Supply
VSS(2) VSS PGround
AVDD(2) AVDD P Analog Power Supply
AVSS(2) AVSS P Analog Ground
RB5 PGM I Low Voltage ICSP Input when LVP Conf iguration bit equ als ‘1’(1)
RB6 PGC I Serial Clock
RB7 PGD I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.
2: All power supply (VDD/AVDD) and ground (VSS/AVSS) m ust be connec ted.
FLASH Microcontroller Pr ogramming Specification
PIC18F6X2X/8X2X
DS30499B-page 2 2003 Microchip Technology Inc.
FIGURE 2-1: PIC18F6X2X FAMILY PIN DIAGRAM
PIC18F6525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2/CS/P2B
RE3/P3C
RE4/P3B
RE5/P1C
RE6/P1B
RE7/CCP2(1)/P2A(1)
RD0/PSP0
VDD
VSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE1/WR/P2C
RE0/RD/P2D
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
VDD
RF7/SS
RF6/AN11/C1IN-
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RF0/AN5
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4/LVDIN
RC1/T1OSI/CCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
64-Pin TQFP
Note 1: The CCP2 pin placement depends on the CCP2MX fuse setting.
PIC18F6621
2003 Microchip Technology Inc. DS30499B-page 3
PIC18F6X2X/8X2X
FIGURE 2-2: PIC18F8X2X FAMILY PIN DIAGRAM
PIC18F8525
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2/AD10/CS/P2B
RE3/AD11/P3C(2)
RE4/AD12/P3B(2)
RE5/AD13/P1C(2)
RE6/AD14/P1B(2)
RE7/AD15/CCP2(1)/P2A(1)
RD0/AD0/PSP0
VDD
VSS
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4
RD5/AD5/PSP5
RD6/AD6/PSP6
RD7/AD7/PSP7
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
VDD
RF7/SS
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2(1)/P2A(1)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RF0/AN5
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4/LVDIN
RC1/T1OSI/CCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO
RJ0/ALE
RJ1/OE
RH1/A17
RH0/A16
1
2
RH2/A18
RH3/A19
17
18
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)
RJ5/CE
RJ4/BA0
37
RJ7/UB
RJ6/LB
50
49
RJ2/WRL
RJ3/WRH
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 73
78 77 76 75
79
80
80-Pin TQFP
Note 1: The CCP2 pin placement depends on the CCP2MX fuse and Processor mode settings.
2: P1B, P1C, P3B, and P3C pin placement depends on the ECCPMUX fuse setting.
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RF6/AN11/C1IN-
PIC18F8621
PIC18F6X2X/8X2X
DS30499B-page 4 2003 Microchip Technology Inc.
2.3 Memory Map
The code memory space extends from 0000h to
0FFFFh (64 Kbytes) in four 16-Kbyte blocks.
Addresses 0000h through 07FFh, however, define a
“Boot Block” region that is treated separately from
Block 1. All of these blocks define code protection
boundaries within the code memory space.
In contra st, code memory panel s are defined in 8-Kbyte
boundaries. Panels are discussed in greater detail in
Section 3.2.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-3: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F6X2X/8X2X DEVICES
Device Code Memory Size (Bytes)
PIC18F6525 000000h - 00BFFFh (48K)
PIC18F8525
PIC18F6621 000000h - 00FFFFh (64K)
PIC18F8621
000000h
1FFFFFh
3FFFFFh
01FFFFh
Note: Sizes of memory areas not to scale.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE / DEVICE
64 Kbytes
(PIC18FX621) 48 Kbytes
(PIC18FX525) Address
Range
Boot Block Boot Block 000000h
0007FFh
Block 1 Block 1 000800h
003FFFh
Block 2 Block 2 004000h
007FFFh
Block 3 Block 3 008000h
00BFFFh
Block 4
Unimplemented
Read ‘0’s
00C000h
00FFFFh
Unimplemented
Read ‘0’s
01FFFFh
2003 Microchip Technology Inc. DS30499B-page 5
PIC18F6X2X/8X2X
In addition to the code memory space, there are three
blocks in the configurat ion and ID space that are acce s-
sible to the user through table reads and table writes.
Their locations in the memory map are shown in
Figure 2-4.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally , even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the configuration bits. These bits select various device
options and are described in Section 5.0. These
configuration bits read out normally, even after code
protection.
Locatio ns 3FFFF Eh and 3FFF FFh are res erved for the
device ID bits. Thes e bits may be us ed by the program-
mer to identify what device type is being programmed
and are described in Section 5.0. These device ID bits
read out normal ly, eve n after co de prote cti on .
2.3.1 MEMORY ADDRESS POINTER
Memory in the add ress space 000 0000h to 3FFFFFh is
addressed via the Table Pointer register, which is
comprised of three Pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (Cor e Instr uction ), is used
to load the Table Pointer prior to using many read or
write operations.
FIGURE 2-4: CONFIGURATION AND ID LOCATIONS FOR PIC18F6X2X/8X2X DEVICES
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
ID Location 7 200006h
ID Location 8 200007h
CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
CONFIG3L 300004h
CONFIG3H 300005h
CONFIG4L 300006h
CONFIG4H 300007h
CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh
Device ID1 3FFFFEh
Device ID2 3FFFFFh
Note: Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
2FFFFFh
PIC18F6X2X/8X2X
DS30499B-page 6 2003 Microchip Technology Inc.
2.4 High Level Overview of the
Programming Process
Figure 2-6 shows the high level overview of the pro-
gramming process. First, a bulk erase is performed.
Next, the code memory, ID locations, and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the configuration bits are then
programmed and verified.
2.5 Entering High Voltage ICSP
Program/Verify Mode
The High Voltage ICSP Program/Verify mode is
enter ed by holdi ng PGC and PGD low and the n raising
MCLR/VPP to VIHH (high voltage). Once in this mode,
the code memory, data EEPROM, ID locations, and
configu rati on b its can be acce ssed and p rogramm ed i n
serial fashion.
The sequence that enters the device into the Program/
V erify mode places all unused I/Os in the high-impedance
state.
2.5.1 ENTERING LOW VOLTAGE ICSP
PROGRAM/VERIFY MODE
When the LVP configurati on bit is ‘1’ (s ee Sec tion 5.3),
the Low Voltage ICSP mode is enabled. Low Voltage
ICSP Program/Verify mode is entered by holding PGC
and PGD low, placing a logic high on PGM, and then
raising MCLR/VPP to VIH. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the Program/
V erify mode places all unused I/Os in the high-impedance
state.
FIGUR E 2 - 5 : ENTERING HIGH VOLTAGE
PROGRAM/VERIFY MOD E
FIGURE 2-6: HIGH LEVEL
PROGRAMMING FLOW
FIGURE 2-7: EN T ER I NG LO W V O LTAG E
PROGRAM/ VERIFY MODE
MCLR/VPP
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
Start
Program Memory
Program IDs
Program Data
Verify Program
Veri fy IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP
P12
PGD
PGD = Input
PGC
PGM
P15
VDD
VIH
VIH
2003 Microchip Technology Inc. DS30499B-page 7
PIC18F6X2X/8X2X
2.6 Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial oper ation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of P GC, and are Le ast Signi fican t bit (L Sb)
first.
2.6.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
comma nd follo wed by a 16 -bit opera nd whi ch dep ends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-4. The 4-bit com-
mand is shown MSb first. The command operand, or
“Data Payload”, is shown <MSB><LSB>. Figure 2-8
demonstrates how to serially present a 20-bit
command/operand to the device.
2.6.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to setup
register s as ap propria te for use with oth er comm ands.
TABLE 2-3: COMMANDS FOR
PROGRAMMING
TABLE 2-4: SAMPLE COMMAND
SEQUENCE
FIGURE 2-8: TABLE WRITE, POST-INCREMENT TIMING (1101)
Description 4-bit
Command
Core Instruction
(Shift in16-bit instruction) 0000
Shift out TABLAT register 0010
Tab le Read 1000
Table R ead , post-i nc rem en t 1001
Table R ead , post-d ec rem ent 1010
Table R ead , pre-in cre men t 1011
Table Write 1100
Table Write, post-increment by 2 1101
Table W r i te, pos t-de cre me nt by 2 1110
Table Write, start programming 1111
4-bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
1234
PGC P5
PGD
PGD = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-bit Command 16- bit Data Payload
P2B
PIC18F6X2X/8X2X
DS30499B-page 8 2003 Microchip Technology Inc.
3.0 DEVICE PR OGRAMMING
3.1 High Voltage ICSP Bulk Erase
Erasing code or data EEPROM is accomplished by
writing an “erase option” to address 3C0004h. Code
memory may be erased portions at a time, or the user
may era se th e entir e devi ce in one a ction . “Bulk Erase”
operations will also clear any code protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed opera-
tion. Once the era se has st arted (fal ling edge o f the 4th
PGC after the NOP command), serial execution will
cease until the erase completes (parameter P11). Dur-
ing this time, PGC may continue to toggle but PGD
must be held low.
The code sequence to er ase the entire devic e is shown
in Figure 3-2 and the fl ow c hart i s s hown in Figure 3-1.
TABLE 3-2: BULK ERASE COMMAND
SEQUENCE
FIGURE 3-1: BULK ERASE FLOW
FIGURE 3-2: BULK ERASE TIMING
Description Data
Chip Erase 80h
Erase Data EEPROM 81h
Erase Boot Block 83h
Erase Block 1 88h
Erase Block 2 89h
Erase Block 3 8Ah
Erase Block 4 8Bh
Erase Block 5 8Ch
Erase Block 6 8Dh
Erase Block 7 8Eh
Erase Block 8 8Fh
Note: A bulk erase is the only way to reprogram
code protect bits from an on-state to an
off-state.
4-bit
Command Data
Payload Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
00 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold PGD low until
erase completes.
Start
Done
Write 80h
To Erase
Entire Devi ce
Load Address
Poi n te r to
3C0004h
Delay P11+P10
Time
n
1234 121516 123
PGC
P5 P5A
PGD
PGD = Input
00011
P11
P10
Erase Time
00 0 000 0 0
12
00
4
0
12 1516
P5
123
P5A
4
0000
n
4-bit Command 4-bit Command 4-b it Command16-bit
Data Payload
16-bit
Data Payload 16-bit
Data Payload
2003 Microchip Technology Inc. DS30499B-page 9
PIC18F6X2X/8X2X
3.1.1 LOW VO LTAGE ICSP BULK ERASE
When using low voltage ICSP, the part must be sup-
plied by the voltage specified in parameter #D111 if a
bulk erase is to be e xecuted. All other bul k erase deta ils
as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Sections 3.1.2 and 3.2.2.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.3
and write ‘1’s to the array.
3.1.2 ICSP MULTI-PANEL SINGLE ROW
ERASE
Regardless of whether high or low volt age ICSP is used,
it is possible to erase a single row (64 bytes of data) in
all panels at once. For example, in the case of a
64-Kbyte device (8 panels), 512 bytes through 64 bytes
in each p anel can be erased simult aneously during e ach
erase sequence. In this case, the offset of the erase
within each panel is the same (see Figure 3-5). Multi-
panel single row erase is enabled by appropriately con-
figuring the Programming Control register located at
3C0006h.
The multi-panel single row erase duration is externally
timed a nd is control led by PGC. After a “S t art Program -
ming” command is issued (4-bit command, ‘1111’), a
NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is termin ated. PGC mus t be held lo w for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to erase a PIC18F6X2X/8X2X
device is shown in Table 3-3. The flow chart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18F6X2X/8X2X device. The timing dia-
gram that details the “Start Programming” command,
and parameters P9 and P10 is shown in Figure 3-6.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
PIC18F6X2X/8X2X
DS30499B-page 10 2003 Microchip Technology Inc.
TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE
FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
0000
8E A6
8C A6
84 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel erase.
Step 3: Direct access to code memory.
0000
0000
0000
0000
0000
8E A6
9C A6
6A F8
6A F7
6A F6
BSF EECON1, EEPGD
BCF EECON1, CFGS
CLRF TBLPTRU
CLRF TBLPTRH
CLRF TBLPTRL
Step 4: Enable erase and erase single row of all panels at an offset.
0000
1111
0000
88 A6
<DummyLSB>
<DummyMSB>
00 00
BSF EECON1, FREE
Write 2 dummy bytes and start programming.
NOP - hold PGC high for time P9.
Step 5: Repeat step 4, with address pointer incremented by 64 until all panels are erased.
Done
Start
Delay P9 + P10
Time for Erase
to Occur
All
Panels
Done?
No
Yes
Addr = 0
Configure
Device for
Multi-Panel Erase
Addr = Addr + 64
Start Erase Sequence
and hold PGC High
Until Done
2003 Microchip Technology Inc. DS30499B-page 11
PIC18F6X2X/8X2X
3.2 Code Memory Programming
Programming code memory is accomplished by first
loading dat a int o the appro priate wr ite bu ffe rs an d then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-3) has an 8-byte
deep w rite buffer that mu st be load ed pri or to init iati ng
a write sequence. The actual memory write sequence
takes the contents of these buffers and programs the
associated EEPROM code memory.
Typically, all of the pro gram buf fe rs are w ritten in para l-
lel (Multi-Panel W rite mode). In other words, in the case
of a 64-Kbyte device (8 panels with an 8-byte buffer per
panel), 64 bytes will be simultaneously programmed
during each programming sequence. In this case, the
offset of the write within each panel is the same (see
Figure 3-4). Multi-Panel Write mode is enabled by
appropriately configuring the Programming Control
register located at 3C0006h.
The programming duration is externally timed and is
controlled by PGC. After a “Start Programming” com-
mand is issued (4-bit command, ‘1111’), a NOP is
issued , where th e 4th PG C is he ld hig h for the duratio n
of the programming time, P9.
After PGC is brought low, the programming sequence
is termin ated. PGC mus t be held lo w for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18F6X2X/8X2X
device is shown in Table 3-4. The flow chart shown in
Figure 3-5 depicts the logic necessary to completely
write a PIC 18F 6X2X/ 8X2X de vi ce . The tim in g dia gram
that details the “Start Programming” command, and
parameters P9 and P10, is shown in Figure 3-6.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
PIC18F6X2X/8X2X
DS30499B-page 12 2003 Microchip Technology Inc.
FIGURE 3-4: ERASE AND WRITE BOUNDARIES
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 0
Offset = TBLPTR<12:6>
Panel 1
Erase Region
(64 bytes)
8-Byte Write Buffe r
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 1
Offset = TBLPTR<12:6>
Panel 2
Erase Region
(64 bytes)
8-Byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 2
Offset = TBLPTR<12:6>
Panel 3
Erase Region
(64 bytes)
8-Byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = (n – 1)
Offset = TBLPTR<12:6>
Panel n
Erase Region
(64 bytes)
8-Byte Write Buffer
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
2003 Microchip Technology Inc. DS30499B-page 13
PIC18F6X2X/8X2X
TABLE 3-4: WRITE CODE MEMORY CODE SEQUENCE
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
0000
8E A6
8C A6
84 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel writes.
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Load write buffer for Panel 1.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1100
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes
Step 5: Repeat for Panel 2.
Step 6: Repeat for all but the last panel (N – 1).
Step 7: Load write buffer for last panel.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold PGC high for time P9
To continue writing data, repeat steps 2 through 5, where the address pointer is incremented by 8 in each panel at each iteration of
the loop.
PIC18F6X2X/8X2X
DS30499B-page 14 2003 Microchip Technology Inc.
FIGURE 3-5: PROGRAM CODE MEMORY FLOW
FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
Start Write Sequence
All
Locations
Done?
No
Done
Start
Yes
Delay P9+P10 Time
for Write to Occur
Load 8 Bytes
to Panel N Write
Buffer at <Addr>
All
Panel Buffers
Written?
No
Yes
and Hold PGC
High Until Done
N = 1
LoopCount = 0
Configure
Device for
Multi-Panel Writes
N = 1
LoopCount =
LoopCount + 1
N = N + 1
Panel Base Address =
(N – 1) x 2000h
Addr = Panel Base Address
+ (8 x LoopCount)
1234 1 2 15 16 123 4
PGC
P5A
PGD
PGD = Input
n
1111
34 65
P9
P10
Programming Time
nnn nn n n 00
12
0
00
16-bit
Data Payload
0
3
0
P5
4-bit Command 16-bit Data Payload 4-bit Comm an d
2003 Microchip Technology Inc. DS30499B-page 15
PIC18F6X2X/8X2X
3.2.1 SINGLE PANEL PROGRAMMING
The programming example presented in Section 3.2
utilizes multi-panel programming. This technique
greatly decreases the total amoun t of time necessary to
completely program a device and is the recommended
method of com pl etel y prog ram mi ng a devi ce .
There m ay be situa tio ns , h ow ev er, wher e i t is adv an t a-
geous to limit writes to a single panel. In such cases,
the user only needs to disable the m ulti-pan el write fea-
ture of the device by appropriately configuring the
Programming Control register located at 3C0006h.
The single panel that will be written will automatically
be enabled based on the value of the Table Pointer.
3.2.2 MODIFYING CODE MEMORY
All of the programming examples up to this point have
assum ed tha t the dev ic e has bee n bulk er ased prior to
programming (see Section 3.1). It may be the case,
however, that the user wishes to modify only a section
of an already programmed device.
The minim um am ount of dat a that c an be wri tten to the
device is 8 bytes. This is accomplished by placing the
device i n Single Pan el Write mode (see Sec ti on 3.2.1),
loadi ng the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte t arg et sp a ce prio r to writi ng the data.
When usi ng the EECON1 register to ac t on code mem-
ory, the EEPGD bit must be set (E ECON1<7> = 1) an d
the CFGS bit must be cleared (EECON1<6> = 0). The
WREN bit must be set (EECON1<2> = 1) to enable
writes of an y so rt (e.g., erase s), a nd th is mu st be don e
prior to initiating a write sequence. The FREE bit must
be set (EECON1<4> = 1) in order to erase the program
spac e bei ng pointed t o b y t he Table Poi nte r. The erase
sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is str ongly recomm ended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 is used to “ena ble” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR b it
in order for the write to occur.
The eras e w il l b eg in on th e falling e dge o f the 4th PG C
after the WR bi t is set. After th e era se seq uen ce term i-
nates, PG C mus t s t il l b e h eld lo w for the tim e sp eci fied
by parameter #P10 to allow high voltage discharge of
the memory array.
Note: Even though multi-panel writes are dis-
abled, the user must still fill the 8-byte
write buffer for the given panel.
PIC18F6X2X/8X2X
DS30499B-page 16 2003 Microchip Technology Inc.
TABLE 3-5: MODIFYING CODE MEMORY
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
8E A6
8C A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single-panel writes.
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 5: Enable memory writes and setup an erase.
0000
0000
84 A6
88 A6
BSF EECON1, WREN
BSF EECON1, FREE
Step 6: Perform required sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 55h
MOVWF EECON2
MOVLW 0AAh
MOVWF EECON2
Step 7: Initiate erase.
0000
0000
82 A6
00 00
BSF EECON1, WR
NOP
Step 8: Wait for P11+P10.
Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold PGC high for time P9
To continue writing data, repeat Step 9, where the address pointer is incremented by 8 at each iteration of the loop.
Step 10: Disable writes.
0000 94 A6 BCF EECON1, WREN
2003 Microchip Technology Inc. DS30499B-page 17
PIC18F6X2X/8X2X
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
address pointer (register pair EEADR:EEADRH) and a
data latch (EEDA TA). Data EEPROM is wri tten by load-
ing EEADR:EEADRH with the desired memory loca-
tion, EEDATA with the data to be written, and initiating
a memory write by appropriately configuring the
EECON1 and EECON2 registers. A byte write auto-
matically erases the location and writes the new data
(erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EEC ON1< 2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequen ce. The write sequence i s initiated by setting the
WR bit (EECON1 <1> = 1). It is strongly rec om mende d
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 i s used to “enable ” the WR
bit. This register must be sequentially loaded with 55h
and then AAh i mmediate ly prior to asse rting the WR b it
in order for the write to occur.
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must still be held low for the time specified by parame-
ter P 10 to al low hi gh vo ltage disc harg e of t he mem ory
array.
FIGURE 3-7: PROGRAM DAT A FL OW
FIGURE 3-8: DATA EEPROM WRITE TIMING
Start
St ar t Write
Set Data
Done
No
Yes
Done
?
Enable Write
Unlock Sequence
55h - EECON2
AAh - EECON2
Sequence
Set Address
WR bit
Clear? No
Yes
n
PGC
PGD
PGD = Input
0000
BSF EECON1, WR4-bit Command
1234 121516
P5 P5A
P10 12
n
Poll WR bit, Repeat Until Clear
16-bit Dat a
Payload
1234 121516 123
P5 P5A
41 2 15 16
P5 P5A
0000
MOVF EECON1, W, 04-bit Command
0000
4-bit Command Shift Out Data
MOVWF TABLAT
PGC
PGD
(see below)
(see Figure 4-6)
PGD = Input PGD = Output
Poll WR bit
P11A
PIC18F6X2X/8X2X
DS30499B-page 18 2003 Microchip Technology Inc.
TABLE 3-6: PROGRAMMING DATA MEMORY
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM address pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Load the data to be written.
0000
0000
0E <Data>
6E A8
MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Perform required sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 6: Initiate write.
0000 82 A6 BSF EECON1, WR
Step 7: Poll WR bit, repeat until the bit is clear.
0000
0000
0010
50 A6
6E F5
<LSB><MSB>
MOVF EECON1, W, 0
MOVWF TABLAT
Shift out data(1)
Step 8: Disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat steps 2 through 8 to write more data.
Note 1: See Figure 4-4 for details on shift out data timing.
2003 Microchip Technology Inc. DS30499B-page 19
PIC18F6X2X/8X2X
3.4 ID Location Programming
The ID locations are programmed much like the code
memory, except that multi-panel writes must be dis-
abled. The single panel that will be written will auto-
matically be enabled, based on the value of the Table
Pointer. The ID registers are mapped in addresses
200000h through 200007h. These locations read out
normally even after c ode protection.
Table 3 -7 demonst rates the code se quence requ ired to
write the ID locations.
In order to modif y the ID l ocations , refer to the me thod-
ology described in Section 3.2.2, “Modifying Code
Memory”. As with code memory, the ID locations must
be e rased befo re mod i fied.
TABLE 3-7: WRITE ID SEQUENCE
Note: Even though multi-panel writes are dis-
abled, the us er must st ill fill the 8-by te data
buffer for the panel.
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
8E A6
8C A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Load write buffer. Panel will be automatically determined by address.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold PGC high for time P9
PIC18F6X2X/8X2X
DS30499B-page 20 2003 Microchip Technology Inc.
3.5 Boot Block Programming
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4).
Multi-panel writes must be disabled so that only
address es in the rang e 000 0h to 07 FFh wil l be wr itte n.
The code sequence detailed in Table 3-7 should be
used, ex cept t hat the addres s dat a use d in “Step 2” will
be in the range 000000h to 0007FFh.
3.6 Configuration Bits Programming
Unlike code memory, the configuration bits are pro-
grammed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (1111) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in Table 3-8.
TABLE 3-8: SET ADDRESS POINTER TO CONFIGURATION LOCATION
Note: Execute four NOPs between every
configu r ati on byt e pr ogra mmin g.
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
8E A6
8C A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Position the program counter(1).
0000
0000
EF 00
F8 00
GOTO 100000h
Step 3(2): Set Table Pointer for config byte to be written. Write even/odd addresses.
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
Step 4: Execute four NOPs.
0000
0000
0000
0000
00 00
00 00
00 00
00 00
Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table write. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.
2003 Microchip Technology Inc. DS30499B-page 21
PIC18F6X2X/8X2X
FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW
Load Even
Configuration
Start
Program Program
MSB
Delay P9 Time
for Wr i te
LSB
Load Odd
Configuration
Address Address
Done
Start
Execute four
NOPs
Delay P9 Time
for Wr i te
Done
Execute four
NOPs
PIC18F6X2X/8X2X
DS30499B-page 22 2003 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Code Memory, ID Locations,
and Configurati on Bits
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The co ntents of memory p ointed to by the Table Po inter
(TBLPTRU:TBLPTRH:TBLPTRL) is loaded into the
Table Latch and then serially output on P GD.
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the op eran d to allow PGD to transiti on fr om an
input to an output. During this time, PGC must be held
low (see Figure 4-1). This operation also increments
the Table Pointer pointer by one, pointing to the next
byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFF h a ddress sp a ce, so i t a ls o a ppl ie s
to the reading of the ID and Configuration registers.
TABLE 4-1: READ CODE MEMORY SEQUENCE
FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4-bit
Command Data Payload Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory into Table Latch and then shift out on PGD, LSb to MSb.
1001 00 00 TBLRD *+
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4- bit Command
1001
PGD = Input
LSb MSb
123456
1234
nnnn
P14
2003 Microchip Technology Inc. DS30499B-page 23
PIC18F6X2X/8X2X
4.2 Verify Code Memory and ID
locations
The veri fy step invo lves reading back the code memo ry
space and comparing it against the copy held in the
programmer’s buffer. Memory reads occur a single byte
at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 4.1 for implementation details of reading code
memory.
The Table Pointer must be manually set to 200000h
(base add ress of the ID loc ations) on ce the code mem-
ory has been verified. The post-increment feature of
the t able read 4-b it command ma y not be used to incre-
ment the Table Pointer beyond the code memory
space. In a 64-Kbyte device, for example, a post-
increment read of address FFFFh will wrap the Table
Pointer back to 0000h, rather than point to
unimplemented address 10000h.
FIGURE 4-2: VERIFY CODE MEMORY FLOW
Read Low Byte
Read High Byte
Does
Word = Expect
Data? Failure,
Report
Error
All
Code Memory
Verified?
No
Yes
No
Set Pointer = 0
Start
Set Pointer = 200000h
Yes
Read Low Byte
Read High byte
Does
Word = Expect
Data? Failure,
Report
Error
All
ID Locations
Verified?
No
Yes
Done
Yes
No
PIC18F6X2X/8X2X
DS30499B-page 24 2003 Microchip Technology Inc.
4.3 Verify Configuration Bits
A configuration address may be read and output on
PGD via the 4 -bit comm and, ‘1001’. Config uration dat a
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately com-
pared to the appropriate configuration data in the pro-
grammer’s memory for verification. Refer to
Section 4.1 for implementation details of reading
configu r ati on data.
4.4 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
address pointer (register pair EEADR:EEADRH) and a
data latch (EEDAT A). Dat a EEPROM is read by loading
EEADR:EEADRH with the desired memory location
and initi ating a m emory read by approp riat ely con figur-
ing the EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on PGD via
the 4-bi t com mand, ‘ 0010’ (Shift Ou t Data Hold ing reg-
ister). A delay of P6 must be introd uced after the fal ling
edge of the 8th PGC of the operand to allow PGD to
transition from an input to an output. During this time,
PGC must be held low (see Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.
FIGURE 4-3: READ DAT A E EPR OM
FLOW
TABLE 4-2: READ DATA EEPROM MEMORY
Start
Set
Address
Read
Byte
Done
No
Yes
Done
?
Mov e to TABLAT
Shift Out Data
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM address pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the Serial Data Holding register.
0000
0000
0010
50 A8
6E F5
<LSB><MSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
Shift Out Data(1)
Note 1: The <LSB> is undefined. The <MSB> is the data.
2003 Microchip Technology Inc. DS30499B-page 25
PIC18F6X2X/8X2X
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TI MING (0010)
4.5 Verify Data EEPROM
A data EEPROM add res s may b e re ad via a se qu enc e
of core instructions (4-bit command, ‘0000’) and then
output on PGD vi a the 4-bit command, ‘0010’ (Shift Out
Dat a Holding reg ister). The re sult may then be immed i-
ately co mp ared to th e app ropriate dat a in the pro gram-
mer ’s memory for verification. Refer to Section 4.4 for
implementation details of reading data EEPROM.
4.6 Blank Check
The t erm “Blank C heck” me ans to ve rify that the device
has no p ro gr amm ed m em ory ce l ls. A ll me mo rie s mu st
be verif ied: code memo ry, data EEPROM, ID locations ,
and configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “bla nk” or “eras ed” me mory c ell wi ll r ead as a ‘1’. So,
“Blank Checking” a device merely means to verify that
all bytes read as FFh except the configuration bits.
Unus ed (res erved ) conf igura tion b its wil l read ‘ 0’ (pro-
grammed). Refer to Table 5-2 for blank configuration
expect data for the various PIC18F6X2X/8X2X
devices.
Given that “Blank Checking” is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 and Sect ion 4.2 for implemen t ation det ails .
FIGURE 4-5: BLANK CHECK FLOW
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-bit Command
0100
PGD = Input
LSb MSb
123456
1234
nnnn
P14
Yes
No
Start
Blank Check Device
Is
Device
Blank? Continue
Abort
PIC18F6X2X/8X2X
DS30499B-page 26 2003 Microchip Technology Inc.
5.0 CONFIGURATION WORD
The PIC18F6X2X/8X2X devices have several configu-
ration wo rds. Thes e bit s can be set or cl eared to se lect
various device configurations. All other memory areas
should be programmed and verified prior to setting con-
figuration words. These bits may be read out normally
even after read or code protected.
5.1 ID Locations
A user may sto re ide ntif ic atio n inf orm atio n (ID ) in eig ht
ID locations mapped in 200000h:200007h. It is recom-
mended that the Most Significant nibble of each ID be
0Fh. In doing so, if the user code inadvertently tries to
execute from the ID space, the ID data will execute as
a NOP.
5.2 Device ID W ord
The device ID word for the PIC18F6X2X/8X2X is
located at 3FFFFEh:3 FFFFFh. These b its may b e used
by the programmer to identify what device type is being
programmed and read out normally even after code or
read protect ed.
5.3 Low Voltage Progr amming (LVP)
Bit
The LVP bit in Configuration register, CONFIG4L,
enables low voltage ICSP programming. The LVP bit
defaults to a ‘1’ from the factory.
If Low V ol tage Program ming mode is not us ed, the L V P
bit can be programmed to a ‘0’ and RB5/ PGM becomes
a digital I/O pin. How ev er, the LVP bit may only b e p ro-
grammed by entering the High Voltage ICSP mode,
where M CLR/VPP is raised to VIHH. On ce the LVP bit is
programmed to a ‘0’, only the high voltage IC SP mode
is available and only the high voltage ICSP mode can
be used to program the device.
TABLE 5-1: DEVICE ID VALUE
Note 1: The normal ICSP mode is always avail-
able, regardless of the state of the LVP
bit, by applying VIHH to the MCLR/VPP
pin.
2: While in Low Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purp os e I/O.
3: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low Voltage Programming
(CONFIG4L<2> = 0); or
b) make certain that RB5/PGM is held
low during entry into ICSP.
Device Device ID Value
DEVID2 DEVID1
18F6525 0Ah 111x xxxx
18F6621 0Ah 101x xxxx
18F8525 0Ah 110x xxxx
18F8621 0Ah 100x xxxx
Note: The ‘x’s in DEVID1 contain the device revision code.
2003 Microchip Technology Inc. DS30499B-page 27
PIC18F6X2X/8X2X
TABLE 5-2: PIC18F6X2X/8X2X CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
Unprogrammed
Value
300001h CONFIG1H ——OSCSEN—FOSC3FOSC2FOSC1FOSC00010 1111
300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN 0000 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 0001 1111
300004h(1) CONFIG3L WAIT — — — — —PM1PM01000 0011
300005h CONFIG3H MCLRE(3) — — — — — ECCPMUX(1) CCP2MX 1000 0011
300006h CONFIG4L DEBUG — — — —LVP —STVREN1000 0101
300008h CONFIG5L — — — —CP3
(2) CP2 CP1 CP0 0000 1111
300009h CONFIG5H CPD CPB — — — — — — 1100 0000
30000Ah CONFIG6L — — — —WRT3
(2) WRT2 WRT1 WRT0 0000 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000
30000Ch CONFIG7L — — — —EBTR3
(2) EBTR2 EBTR1 EBTR0 0000 1111
30000Dh CONFIG7H — EBTRB — — — — — — 0100 0000
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on conditio n.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18 F6X2X devices; main tain this bit set.
2: Unimplemented in PIC18FX525 devices; main tain this bit set.
3: If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode.
PIC18F6X2X/8X2X
DS30499B-page 28 2003 Microchip Technology Inc.
TABLE 5-3: PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS
Bit Name Configuration
Words Description
OSCEN CONFIG1H Low Power System Clock Option (Timer1) Enable bit
1 =Disabled
0 = Timer1 oscillator system clock option enabled
FOSC3:FOSC0 CONFIG1H Oscillator Selection bits
1111 = RC oscillator w/ OSC2 configured as RA6
1110 = HS oscillator w/ s/w enabled PLL
1101 = EC w/ OSC2 configured as RA6 and s/w enabled PLL
1100 = EC w/ OSC2 configured as RA6 and PLL enabled
1011 = Reserved; do not use
1010 = Reserved; do not use
1001 = Reserved; do not use
1000 = Reserved; do not use
0111 = RC oscillator w/ OSC2 configured as RA6
0110 = HS oscillator w/ PLL enabled
0101 = EC w/ OSC2 configured as RA6
0100 = EC w/ OSC2 configured as ‘divide-by-4 clock output’
0011 = RC oscillator w/ OSC2 configured as ‘divide-by-4 clock output’
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits
11 = VBOR set to 2.0V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
BOREN CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
Note 1: Unimplemented in PIC18F6X2X devices; maintain this bit set.
2: Unimplemented in PIC18FX525 devices; maintain this bit set.
3: If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into
ICSP mode.
2003 Microchip Technology Inc. DS30499B-page 29
PIC18F6X2X/8X2X
WDTPS3:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits
1111 = 1:32768
1110 = 1:16384
1101 =1:8192
1100 = 1:4,096
1011 =1:2048
1010 =1:1024
1001 =1:512
1000 =1:256
0111 =1:128
0110 =1:64
0101 =1:32
0100 =1:16
0011 =1:8
0010 =1:4
0001 =1:2
0000 =1:1
WDTEN C ONFI G2H Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
WAIT(1) CONFIG3L External Bus Data Wait Enable bit
1 = Wait selections unavailable
0 = Wait selections determined by WAIT1:WAIT0 bits of MEMCON
register
PM1:PM0(1) CONFIG3L Processor Mode Select bits
11 = Mic roc on trol ler mode
10 = Mic rop r oc es sor mode
01 = Microprocessor with Boot Block mode
00 = Extended Microcontroller mode
MCLRE(3) CONFIG3H MCLR Enable bit
1 =MCLR
pin enabled, RG5 disabled
0 = RG5 input pin enabled, MCLR disabled
ECCPMUX(1) CONFIG3H ECCP Mux bit
1 = Enhanced CCP1 (P1B/P1C) and enhanced CCP3 (P3B/P3C)
PWM outputs are multiplexed onto RE6 through RE3
0 = Enhanced CCP1 (P1B/P1C) and enhanced CCP3 (P3B/P3C)
PWM outputs are multiplexed onto RH7 through RH4
CCP2MX CONFI G3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RE7 in Microcontroller mode;
CCP2 input/output is multiplexed with RB3 in Extended
Microcontroller mode, Microprocessor or Microprocessor w/ Boot
Block mode
TABLE 5-3: PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Unimplemented in PIC18F6X2X devices; maintain this bit set.
2: Unimplemented in PIC18FX525 devices; maintain this bit set.
3: If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into
ICSP mode.
PIC18F6X2X/8X2X
DS30499B-page 30 2003 Microchip Technology Inc.
DEBUG CONFIG4L Background Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
LVP CONFIG4L Low Voltage Programming Enable bit
1 = Low voltage programming enabled
0 = Low voltage programming disabled
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/underflow will cause RESET
0 = Stack overflow/underflow will not cause RESET
CP0 CONFIG5L Code Protection bits (code memory area 0800h - 3FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP1 CONFIG5L Code Protection bits (code memory area 4000h - 7FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP2 CONFIG5L Code Protection bits (code memory area 8000h - BFFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP3(2) CONFIG5L Code Protection bits (code memory area C000h - FFFFh)
1 = Code memory not code protected
0 = Code memory code protected
CPD CONFIG5H Code Protection bits (data EEPROM)
1 = Data EEPROM not code protected
0 = Data EEPROM code protected
CPB CONFIG5H Code Protection bits (boot block, memory area 0000h - 07FFh)
1 = Boot block not code protected
0 = Boot block code protected
WRT0 CONFIG6L Table Write Protection bit (code memory area 0800h - 3FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT1 CONFIG6L Table Write Protection bit (code memory area 4000h - 7FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT2 CONFIG6L Table Write Protection bit (code memory area 8000h - BFFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT3(2) CONFIG6L Table Write Protection bit (code memory area C000h - FFFFh)
1 = Code memory not write protected
0 = Code memory write protected
TABLE 5-3: PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Unimplemented in PIC18F6X2X devices; maintain this bit set.
2: Unimplemented in PIC18FX525 devices; maintain this bit set.
3: If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into
ICSP mode.
2003 Microchip Technology Inc. DS30499B-page 31
PIC18F6X2X/8X2X
WRTD CONFIG6H Table Write Protection bit (data EEPROM)
1 = Data EEPROM not write protected
0 = Data EEPROM write protected
WRTB CONFIG6H Table Write Protection bit (boot block, memory area 0000h - 07FFh)
1 = Boot block not write p rotected
0 = Boot block write protected
WRTC CONFIG6H Table Write Protection bit (Configuration registers)
1 = Configuration registers not write protected
0 = Configuration registers write protected
EBTR0 CONFIG7L Table Read Protecti on bit (co de mem ory area 0800h - 3FFFh)
1 = Code memory not pro tected from tabl e reads ex ecuted in other bl ocks
0 = Code memory protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protecti on bit (co de mem ory area 400 0h - 7FFFh)
1 = Code memory not pro tected from tabl e reads ex ecuted in other bl ocks
0 = Code memory protected from table reads executed in other blocks
EBTR2 CONFIG7L Table Read Prote cti on bit (co de memory area 800 0h - BFFFh)
1 = Code memory not pro tected from tabl e reads ex ecuted in other bl ocks
0 = Code memory protected from table reads executed in other blocks
EBTR3(2) CONFIG7 L Table Read Protection bit (code mem ory ar ea C000 h - FFFFh)
1 = Code memory not pro tected from tabl e reads ex ecuted in other bl ocks
0 = Code memory protected from table reads executed in other blocks
EBTRB CONFIG7 H Table Read Protection bit (boo t bloc k, me mo ry ar ea 0000h - 07FFh)
1 = Boot block not protected from table reads executed in other blocks
0 = Boot block protected from table reads executed in other blocks
DEV10:DEV3 DEVID2 Device ID bits
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0 DEVID1 Device ID bits
These bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0 DEVID1 These bits are used to indicate the revision of the device.
TABLE 5-3: PIC18F6X2X/8X2X CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Unimplemented in PIC18F6X2X devices; maintain this bit set.
2: Unimplemented in PIC18FX525 devices; maintain this bit set.
3: If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into
ICSP mode.
PIC18F6X2X/8X2X
DS30499B-page 32 2003 Microchip Technology Inc.
5.4 Embedding Configuration Word
Information in the HEX File
To allow portability of code, a PIC18F6X2X/8X2X pro-
grammer is required to read the configuration word
locations from the HEX file. If configuration word infor-
mation is not present in the HEX file, then a simple
warning message should be issued. Similarly, while
saving a HEX file, all configuration word information
must be included. An option to not include the configu-
ration word information may be provided. When
embedding configuration word information in the HEX
file, it should start at address 300000h.
Microchip Technology Inc. feels strongly that this
featur e is imp orta nt for th e bene fit of t he end cu stomer.
5.5 Embedding Data EEPROM
Information In the HEX File
To allow portability of code, a PIC18F6X2X/8X2X pro-
grammer is required to read the data EEPROM infor-
mation from the HEX file. If data EEPROM information
is not present, a simple warning message should be
issued. Similarly, when saving a HEX file, all data
EEPROM information must be included. An option to
not inc lu de the da t a EEPROM i nfo rmatio n m ay b e p ro-
vided. When embedding data EEPROM information in
the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
5.6 Checksum Comput ation
The check s um is cal cu lat ed by sum mi ng the foll ow in g:
• The conte nts of all code me mory locatio ns
• The configuration word, appropriately masked
• ID locations
The Least Significant 16 bits of this sum are the
checksum.
Table 5-4 (pages 33 through 34) describes how to
calculate the checksum for each device.
Note: The checksum calculation differs depend-
ing on the code protect setting. Since the
code memory locations read out differently
dependi ng on the c ode prot ect s etting, the
table describes how to manipulate the
actual code memory values to simulate
the values that would be read from a pro-
tected device. When calculating a check-
sum by reading a device, the entire code
memory can simply be read and summed.
The configuration word and ID locations
can always be read.
2003 Microchip Technology Inc. DS30499B-page 33
PIC18F6X2X/8X2X
TABLE 5-4: CHECKSUM COMPUTATION
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
PIC18F6525
None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+
SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0000)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)
4642 4598
Boot
Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
(CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
4E12 4DC7
Boot/
Block1/
Block2
SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0000)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)+
SUM(IDs)
C60F C5C4
All (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
060B 615
PIC18F6621
None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0000)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)
0642 0598
Boot
Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+SUM(C000:FFFF)+
(CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
0E0E 0DC3
Boot/
Block1/
Block2
SUM(8000:BFFF)+SUM(C000:FFFF)+(CONFIG1L & 0000)+
(CONFIG1H & 002F)+(CONFIG2L & 000F)+(CONFIG2H & 001F)+
(CONFIG3L & 0000)+(CONFIG3H & 0083)+(CONFIG4L & 0085)+
(CONFIG4H & 0000)+(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+
(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+
(CONFIG7H & 0040)+SUM(IDs)
860B 85C0
All (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0000)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
05FF 0609
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
PIC18F6X2X/8X2X
DS30499B-page 34 2003 Microchip Technology Inc.
PIC18F8525
None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+
SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)
46C5 461B
Boot
Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
(CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0083)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
4EA0 4E46
Boot/
Block1/
Block2
SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
C69D C643
All (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0083)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
0699 0694
PIC18F8621
None SUM(0000:07FF)+SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)
06C5 061B
Boot
Block SUM(0800:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+
(CONFIG2L & 000F)+(CONFIG2H & 001F)+(CONFIG3L & 0083)+
(CONFIG3H & 0083)+(CONFIG4L & 0085)+(CONFIG4H & 0000)+
(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+
(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+(CONFIG7H & 0040)+
SUM(IDs)
0E9C 0E42
Boot/
Block1/
Block2
SUM(8000:BFFF)+SUM(C000:FFFF)+(CONFIG1L & 0000)+
(CONFIG1H & 002F)+(CONFIG2L & 000F)+(CONFIG2H & 001F)+
(CONFIG3L & 0083)+(CONFIG3H & 0083)+(CONFIG4L & 0085)+
(CONFIG4H & 0000)+(CONFIG5L & 00FF)+(CONFIG5H & 00C0)+
(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+(CONFIG7L & 00FF)+
(CONFIG7H & 0040)+SUM(IDs)
8699 863F
All (CONFIG1L & 0000)+(CONFIG1H & 002F)+(CONFIG2L & 000F)+
(CONFIG2H & 001F)+(CONFIG3L & 0083)+(CONFIG3H & 0083)+
(CONFIG4L & 0085)+(CONFIG4H & 0000)+(CONFIG5L & 00FF)+
(CONFIG5H & 00C0)+(CONFIG6L & 00FF)+(CONFIG6H & 00E0)+
(CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs)
068D 0688
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
2003 Microchip Technology Inc. DS30499B-page 35
PIC18F6X2X/8X2X
6.0 AC/DC CHA RACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious pro gram
executions to occur. The ma xi m um transitio n t ime is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL, and XT m odes only)
+ 2 ms (for HS/PLL mo de only) + 1.5 µs (for EC m ode onl y)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period, and TOSC is the oscilla to r period.
For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.
Standard Opera ting Condition s
Operat i ng Tempe ra tu re : 25°C i s re commend ed
Param
No. Sym Characteristic Min Max Units Conditions
D110 VIHH High Voltage Programmin g Voltage on M CLR/
VPP 9.00 13.25 V
D110A VIHL Low Volt age Programming Volt age on MCLR/
VPP 2.00 5.50 V
D111 VDD Supply Voltage During Programm i ng 2.00 5.50 V N or m al pro gr am m i ng
4.50 5.50 V Bulk eras e operations
D112 IPP Programming Current on MCLR/VPP —300µA
D113 IDDP Supply Current Dur ing Programm i ng — 10 mA
D031 VIL I npu t L ow Voltage V SS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 4.5V
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V
D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specificatio ns
P1 TRMCLR/VPP Rise Time to enter
Program/ Verify mode —1.0µs(N ote 1)
P2 TPGC Serial Clock (PGC) Period 100 — ns VDD = 5.0V
1—µsV
DD = 2.0V
P2A TPGCL Serial Clock (PGC) Low Time 40 — ns VDD = 5.0 V
400 — ns VDD = 2.0V
P2B TPGCH Serial Clock (PGC) High Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P3 Tset1 Input Data Setup Time to Serial Clock ↓15 — ns
P4 Thld1 Input Data Hold Time from PGC ↓ 15 — ns
P5 Tdly1 D elay between 4- bi t Command an d C om m and
Operand 40 — ns
P5A Tdly1a Delay between 4- bit C om m and Opera nd and
next 4-bi t Comm and 40 — ns
P6 Tdl y2 Delay betw een La st PGC ↓ of Command Byte to
First PGC ↑ of R ead of Data Word 20 — ns
P9 Tdly5 PGC High Time (minimum programming time) 1 — ms
P10 Tdly6 PGC Low Time after Programming
(high vol tage discharge time) 5—µs
P11 Tdly7 Delay to allow Self-Timed Data Write or Bulk
Erase to occ ur 5—ms
P11A Tdrwt Data Write Polling Time 4 — ms
P12 Thld2 Input Data Hold T ime from MCLR/VPP ↑2—µs
P13 Tset2 VDD ↑ Setup Time to MCLR/VPP ↑100 — ns
P14 Tvalid Data Out Valid from PGC ↑10 — ns
P15 Tset3 PGM ↑ Setup Time to MCLR/VPP ↑2—µs
PIC18F6X2X/8X2X
DS30499B-page 36 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS30499B-page 37
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICST ART, PRO MA TE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB , PICMASTER, SE EVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-
Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPA SM , MP LIB, MP LINK, MPSI M,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, Powe rTool, rfLAB , rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporat ed in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach t he code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002 .
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS30499B-page 38 2003 Microchip Technology Inc.
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