OPA551 OPA552 OPA 551 O PA OPA 551 551 SBOS100A - JULY 1999 - REVISED OCTOBER 2003 High-Voltage, High-Current OPERATIONAL AMPLIFIERS FEATURES DESCRIPTION WIDE SUPPLY RANGE: 4V to 30V HIGH OUTPUT CURRENT: 200mA Continuous LOW NOISE: 14nV/Hz FULLY PROTECTED: Thermal Shutdown Output Current-Limited THERMAL SHUTDOWN INDICATOR WIDE OUTPUT SWING: 2V From Rail FAST SLEW RATE: OPA551: 15V/s OPA552: 24V/s WIDE BANDWIDTH: OPA551: 3MHz OPA552: 12MHz PACKAGES: DIP-8, SO-8, or DDPAK-7 APPLICATIONS The OPA551 and OPA552 are low cost op amps with highvoltage (60V) and high-current (200mA) capability. The OPA551 is unity-gain stable and features high slew rate (15Vs) and wide bandwidth (3MHz). The OPA552 is optimized for gains of 5 or greater, and offers higher speed with a slew rate of 24V/s and a bandwidth of 12MHz. Both are suitable for telephony, audio, servo, and test applications. These laser-trimmed, monolithic integrated circuits provide excellent low-level accuracy along with high output swing. High performance is maintained as the amplifier swings to its specified limits. The OPA551 and OPA552 are internally protected against over-temperature conditions and current overloads. The thermal shutdown indicator "flag" provides a current output to alert the user when thermal shutdown has occurred. The OPA551 and OPA552 are available in DIP-8 and SO-8 packages, as well as a DDPAK-7 surface-mount plastic power package. They are specified for operation over the extended industrial temperature range, -40C to +125C. TELEPHONY TEST EQUIPMENT AUDIO AMPLIFIERS TRANSDUCER EXCITATION SERVO DRIVERS OPA551, OPA552 OPA551, OPA552 OPA551, OPA552 NC 1 8 Flag V- 1 8 Flag -In 2 7 V+ -In 2 7 V+ +In 3 6 Out +In 3 6 Out V- 4 5 NC V- 4 5 V- DIP-8 (P) SO-8 (U) 1 2 3 4 5 6 7 NOTE: Tab is connected to V- supply. +In NC V+ Flag -In V- Out DDPAK-7 Surface-Mount (F) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright (c) 1999-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com SPECIFICATIONS: VS = 30V OPA551 At TJ = +25C(1), RL = 3k connected to ground and VOUT = 0V, unless otherwise noted. Boldface limits apply over the specified junction temperature range, TJ = -40C to +125C. OPA551UA, PA, FA PARAMETER OFFSET VOLTAGE Input Offset Voltage TJ = -40C to +125C vs Temperature vs Power Supply CONDITION VOS MIN TYP 1 UNITS 3 10 30 mV mV V/C V/V IB IOS 20 3 100 100 pA pA en in 14 3.5 dVOS /dT PSRR VCM = 0V, IO = 0 MAX 7 VS = 4V to 30V, VCM = 0V 5 INPUT BIAS CURRENT Input Bias Current Input Offset Current NOISE Input Voltage Noise Density, f = 1kHz Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio VCM CMRR -27.5V < VCM < +27.5V (V-) + 2.5 92 INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain TJ = -40C to +125C FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.1% 0.01% Total Harmonic Distortion + Noise, f = 1kHz AOL GBW SR THD+N Overload Recovery Time OUTPUT Voltage Output TJ = -40C to +125C VOUT TJ = -40C to +125C Maximum Continuous Current Output: dc IO Short-Circuit Current ISC Capacitive Load Drive CLOAD SHUTDOWN FLAG Thermal Shutdown Status Output Normal Operation Thermally Shutdown Voltage Compliance Range Junction Temperature Shutdown Reset from Shutdown POWER SUPPLY Specified Voltage Operating Voltage Range Quiescent Current TJ = -40C to +125C TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SO-8 Surface Mount DIP-8 DDPak-7 DDPak-7 RL = 3k, -28V < VO < +28V RL = 3k, -28V < VO < +28V RL = 300, -27V < VO < +27V 110 100 G=1 G = 1, CL = 100pF, 10V Step G = 1, CL = 100pF, 10V Step VO = 15Vrms, RL = 3k, G = 3 VO = 15Vrms, RL = 300, G = 3 VIN * Gain = VS IO = 200mA IO = 200mA IO = 10mA IO = 10mA Package Dependent--See Text (V-) + 3.0 (V-) + 3.5 (V-) + 2.0 (V-) + 2.5 200 Stable Operation Sourcing Sourcing 80 V- nV/Hz fA/Hz 102 (V+) - 2.5 V dB 1013 || 2 1013 || 6 || pF || pF 126 120 dB dB dB 3 15 1.3 2 0.0005 0.0005 1 MHz V/s s s % % s (V+) (V+) (V+) (V+) - - - - 3.0 3.5 2.0 2.7 V V V V mA mA 1 160 (V+) - 1.5 A A V 380 See Typical Curve 0.05 120 C C 160 140 VS IQ 4 IO = 0 TJ TJ TA 30 7 -40 -55 -65 JA JA JA JC 30 8.5 10 V V mA mA +125 +125 +150 C C C C/W C/W C/W C/W 90 100 65 3 NOTES: (1) All tests are high-speed tested at +25C ambient temperature. Effective junction temperature is +25C unless otherwise noted. 2 OPA551, OPA552 www.ti.com SBOS100A SPECIFICATIONS: VS = 30V OPA552 At TJ = +25C(1), RL = 3k connected to Ground and VOUT = 0V, unless otherwise noted. Boldface limits apply over the specified junciton temperature range, TJ = -40C to +125C. OPA552UA, PA, FA PARAMETER OFFSET VOLTAGE Input Offset Voltage TJ = -40C to +125C vs Temperature vs Power Supply CONDITION VOS MIN TYP 1 UNITS 3 10 30 mV mV V/C V/V IB IOS 20 3 100 100 pA pA en in 14 3.5 dVOS /dT PSRR VCM = 0V, IO = 0 MAX 7 VS = 4V to 30V, VCM = 0V 5 INPUT BIAS CURRENT Input Bias Current Input Offset Current NOISE Input Voltage Noise Density, f = 1kHz Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio VCM CMRR 102 V dB 1013 || 2 1013 || 6 || pF || pF 126 120 dB dB dB G=5 G = 5, CL = 100pF, 10V Step G = 5, CL = 100pF, 10V Step VO = 15Vrms, RL = 3k, G = 5 VO = 15Vrms, RL = 300, G = 5 12 24 2.2 3 0.0005 0.0005 MHz V/s s s % % VIN * Gain = VS 1 s -27.5V < VCM < +27.5V (V-) + 2.5 92 INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain TJ = -40C to +125C FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.1% 0.01% Total Harmonic Distortion + Noise, f = 1kHz AOL GBW SR THD+N Overload Recovery Time OUTPUT Voltage Output TJ = -40C to +125C VOUT TJ = -40C to +125C Maximum Continuous Current Output: dc IO Short-Circuit Current ISC Capacitive Load Drive CLOAD SHUTDOWN FLAG Thermal Shutdown Status Output Normal Operation Thermally Shutdown Voltage Compliance Range Junction Temperature Shutdown Reset from Shutdown POWER SUPPLY Specified Voltage Operating Voltage Range Quiescent Current TJ = -40C to +125C TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SO-8 Surface Mount DIP-8 DDPak-7 DDPak-7 nV/Hz fA/Hz RL = 3k, -28V < VO < +28V RL = 3k, -28V < VO < +28V RL = 300, -27V < VO < +27V IO = 200mA IO = 200mA IO = 10mA IO = 10mA Package Dependent--See Text 110 100 (V-) + 3.0 (V-) + 3.5 (V-) + 2.0 (V-) + 2.5 200 Stable Operation Sourcing Sourcing 80 V- (V+) - 2.5 (V+) (V+) (V+) (V+) - - - - 3.0 3.5 2.0 2.7 V V V V mA mA 1 160 (V+) - 1.5 A A V 380 See Typical Curve 0.05 120 C C 160 140 VS IQ 4 IO = 0 TJ TJ TA 30 7 -40 -55 -65 JA JA JA JC 30 8.5 10 V V mA mA +125 +125 +150 C C C 90 100 65 3 C/W C/W C/W C/W NOTES: (1) All tests are high-speed tested at +25C ambient temperature. Effective junction temperature is +25C unless otherwise noted. OPA551, OPA552 SBOS100A www.ti.com 3 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Output Current ................................................................. See SOA Curve Supply Voltage, V+ to V- ................................................................... 60V Input Voltage Range ....................................... (V-) - 0.5V to (V+) + 0.5V Operating Temperature .................................................. -55C to +125C Storage Temperature ..................................................... -65C to +150C Junction Temperature .................................................................... +150C Lead Temperature (soldering 10s, DIP-8) ...................................... 300C (soldering 3s, SO-8 and DDPAK) .................... 240C ESD Capability (Human Body Model) ............................................. 3000V NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet. 4 OPA551, OPA552 www.ti.com SBOS100A TYPICAL PERFORMANCE CURVES At TJ = +25C, VS = 30V and RL = 3k, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPA551 OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPA552 140 0 140 0 OPA552 OPA551 120 -40 100 -40 -60 80 -60 Phase 60 -80 40 -100 20 -120 0 -20 -40 1 10 100 1k 10k 100k 1M -20 Gain 60 -80 Phase 40 -100 20 -120 -140 0 -140 -160 -20 -160 -180 10M -40 1 10 100 Frequency (Hz) 1k 10k 100k 1M -180 10M Frequency (Hz) POWER SUPPLY REJECTION RATIO vs FREQUENCY COMMON-MODE REJECTION RATIO vs FREQUENCY 120 120 100 100 80 80 PSRR (dB) CMRR (dB) -PSRR 60 +PSRR 40 40 20 20 0 0 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10k 10M 0.1 VO = 15Vrms RL = 3k, 300 G = 3 (OPA551) G = 5 (OPA552) 1k in 100 10 0.01 THD+N (%) Voltage Noise (nV/Hz) Current Noise (fA/Hz) 60 0.001 en 1 0.0001 10 100 1k 10k 100k 1M 1 Frequency (Hz) 1k 10k 100k Frequency (Hz) OPA551, OPA552 SBOS100A 100 www.ti.com 5 Phase () Gain (dB) 80 -20 Gain (dB) Gain 100 Phase () 120 TYPICAL PERFORMANCE CURVES (Cont.) At TJ = +25C, VS = 30V and RL = 3k, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 30 (V+) 25 (V+)-1 Output Voltage Swing (V) Maximum Output Voltage (V) MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY 20 OPA552 15 OPA551 10 5 Without Slew-Induced Distortion +85C +25C (V+)-2 -55C (V+)-3 (V-)+3 +25C -55C (V-)+2 (V-)+1 0 +85C (V-) 1 10 100 1k 10k 100k 1M 10M 0 50 100 150 200 250 300 350 400 Frequency (Hz) Output Current (mA) OPEN-LOOP GAIN, POWER SUPPLY REJECTION RATIO, AND COMMON-MODE REJECTION RATIO vs TEMPERATURE INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs TEMPERATURE 100k 130 125 AOL 10k 120 110 Current (pA) Gain (dB) 115 PSRR 105 100 CMRR 1k +IB 100 95 -IB 10 90 85 -IOS 80 -75 -25 25 75 1 -75 125 QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE 8 430 IQ 390 370 +ISC 4 350 3 330 2 310 1 290 0 -75 ISC (mA) IQ (mA) 410 -ISC 5 270 -50 -25 0 25 50 75 100 125 150 25 50 75 100 125 OPA552 10 OPA551 1 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Temperature (C) 6 0 100 Gain Bandwidth Product (MHz) 450 6 -25 GAIN BANDWIDTH PRODUCT vs TEMPERATURE 9 7 -50 Ambient Temperature (C) Ambient Temperature (C) OPA551, OPA552 www.ti.com SBOS100A TYPICAL PERFORMANCE CURVES (Cont.) At TJ = +25C, VS = 30V and RL = 3k, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE 35 30 30 25 25 Current (pA) 20 OPA551 15 10 5 5 0 40 60 80 100 120 -5 -30 140 -20 -10 0 10 20 Junction Temperature (C) Common-Mode Voltage (V) QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE OFFSET VOLTAGE PRODUCTION DISTRIBUTION 18 405 -ISC 395 IQ 6.8 385 +ISC 375 6.0 Supply Voltage (V) < 1.8 35 < 1.2 30 < 0.6 25 < 0.0 20 < -0.6 15 < -1.2 10 3 < -3.0 5 6 0 365 0 9 < -1.8 6.4 12 < -2.4 7.2 Typical production distribution of packaged units. 15 Percent of Amplifiers (%) 7.6 30 < 3.0 20 IOS < 2.4 0 -IB 15 10 0 -60 -40 -20 Quiescent Current (mA) +IB 20 OPA552 Short-Circuit Current (mA) Slew Rate (V/s) SLEW RATE vs TEMPERATURE Offset Voltage (mV) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION SETTLING TIME vs CLOSED-LOOP GAIN 18 Typical production distribution of packaged units. 16 14 OPA551 0.01% Settling Time (s) Percent of Amplifiers (%) 100 12 10 8 6 OPA551 0.1% 10 OPA552 0.01% OPA552 0.1% 4 2 0 1 < 15.0 < 13.5 < 12.0 < 10.5 < 9.0 < 7.5 < 6.0 < 4.50 < 3.0 < 1.5 < 0.0 1 10 100 Gain (V/V) Offset Drift V/C OPA551, OPA552 SBOS100A www.ti.com 7 TYPICAL PERFORMANCE CURVES (Cont.) At TJ = +25C, VS = 30V and RL = 3, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. LARGE-SIGNAL STEP RESPONSE OPA551, G = 1, CL = 100pF SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 60 OPA551 G = -1 40 30 OPA551 OPA552 G = -6 5V/div Overshoot (%) 50 OPA551, G = 1 OPA552 G = -4 20 OPA551 G = -2 10 OPA552, G = -8 0 0.01 0.1 1 10 Time (1s/div) Load Capacitance (nF) LARGE-SIGNAL STEP RESPONSE OPA552, G = 5, CL = 100pF SMALL-SIGNAL STEP RESPONSE OPA551, G = 1, CL = 100pF OPA551 5V/div 25mV/div OPA552 Time (1s/div) Time (1s/div) SMALL-SIGNAL STEP RESPONSE OPA552, G = 5, CL = 100pF SMALL-SIGNAL STEP RESPONSE OPA551, G = -1, CL = 1000pF OPA551 5V/div 100mV/div OPA552 Time (1s/div) 8 Time (1s/div) OPA551, OPA552 www.ti.com SBOS100A APPLICATIONS INFORMATION Figure 1 shows the OPA551 connected as a basic noninverting amplifier. The OPA551 can be used in virtually any op amp configuration. OPA552 is designed for use in configurations with gains of 5 or greater. Power supply terminals should be bypassed with 0.1F capacitors, or greater, near the power supply pins. Be sure that the capacitors are appropriately rated for the power supply voltage used. The OPA551 and OPA552 can supply output currents up to 200mA with excellent performance. G = 1+ + R2 R1 0.1F R2 R1 VO OPA551 VIN The OPA551 and OPA552 are designed with internal current-limiting circuitry that limits the output current to approximately 380mA. The current limit varies with increasing junction temperature as shown in the typical curve "Current Limit vs Temperature." This, in combination with the thermal protection circuitry, provides protection from many types of overload conditions including short circuit to ground. THERMAL PROTECTION The OPA551 and OPA552 have thermal shutdown circuitry that protects the amplifier from damage caused by overload conditions. The thermal protection circuitry disables the output when the junction temperature reaches approximately 160C, allowing the device to cool. When the junction temperature cools to approximately 140C, the output circuitry is automatically re-enabled. V+ 10F CURRENT LIMIT ZL Flag The thermal shutdown function is not intended to replace proper heat sinking. Activation of the thermal shutdown circuitry is an indication of excessive power dissipation or an inadequate heat sink. Continuously running the amplifier into thermal shutdown can degrade reliability. The Thermal Shutdown Indicator ("flag") pin can be monitored to determine if shutdown is occurring. During normal operation, the current output from the flag pin is typically 50nA. During shutdown, the current output from the flag pin increases to 120A (typical). This current output allows for easy interfacing to external logic. See Figure 2 for two examples implementing this function. (optional) 0.1F 10F + V- FIGURE 1. Basic Circuit Connections. VOUT OPA551 Flag 80A to 160A HCT logic has relatively wellcontrolled logic level. A properly chosen resistor value can guarantee proper logic high level throughout the full range of flag output current. VLOGIC +5V HCT 27k Logic Ground VOUT OPA551 HP5082-2835 Interface to virtually any CMOS logic gate by choosing resistor value that provides a guaranteed logic high voltage with the minimum (80A) flag current. A diode clamp to the logic supply voltage assures that the CMOS is not damaged by overdrive. Interfacing with HCT Logic CMOS 47k Logic Ground Interfacing with CMOS Logic FIGURE 2. Thermal Shutdown Indicator. OPA551, OPA552 SBOS100A www.ti.com 9 POWER SUPPLIES The OPA551 and OPA552 may be operated from power supplies of 4V to 30V, or a total of 60V with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Performance Curves. For applications that do not require symmetrical output voltage swing, power supply voltages do not need to be equal. The OPA551 and OPA552 can operate with as little as 8V between the supplies or with up to 60V between the supplies. For example, the positive supply could be set to 50V with the negative supply at -10V or vice-versa. The SO-8 package outline shows three negative supply (V-) pins. These pins are internally connected for improved thermal performance. Pin 4 is to be used as the primary current carrier for the negative supply. It is recommended that pins 1 and 5 not be directly connected to V- but, instead be connected to a thermal mass. DO NOT lay out the PC board to use pins 1 and 5 as feedthroughs to the negative supply. Doing so can result in a reduction of performance. The tab of the DDPAK-7 package is electrically connected to the negative supply (V-), however, this connection should not be used to carry current. For best thermal performance, the tab should be soldered directly to the circuit board copper area (see heat sink text). POWER DISSIPATION Internal power dissipation of these op amps can be quite large. Many of the specifications for the OPA551 and OPA552 are for a specified junction temperature. If the device is not subjected to internal self-heating, the junction temperature will be the same as the ambient. However, in practical applications, the device will self-heat and the junction temperature will be significantly higher than ambient. After junction temperature has been established, performance parameters that vary with junction temperature can be determined from the performance curves. The following calculation can be performed to establish junction temperature as a function of ambient temperature and the conditions of the application. Consider the OPA551 in a circuit configuration where the load is 600 and the output voltage is 15V. The supplies are at 30V and the ambient temperature (TA) is 40C. The JA for the 8-pin DIP package is 100C/W. First, the internal heating of the op amp is as follows: PD(internal) = IQ * VS = 7.2mA * 60V = 432mW The output current (IO) can be calculated: IO = VOUT /RL = 15V /600 = 25mA 10 The power being dissipated (PD) in the output transistor of the amplifier can be calculated: PD(output stage) = IO * (VS - VO) = 25mA * (30 - 15) = 375mW PD(total) = PD(internal) + PD(output stage) = 432mW + 375mW = 807mW The resulting junction temperature can be calculated: TJ = TA + PD JA TJ = 40C + 807mW * 100C/W = 120.7C Where, TJ = junction temperature (C) TA = ambient temperature (C) JA = junction-to-air thermal resistance (C/W) For the DDPAK package, the JA is 65C/W with no heat sinking, resulting in a junction temperature of 92.5C. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the thermal protection should trigger more than +35C above the maximum expected ambient condition of your application. This ensures a maximum junction temperature of +125C at the maximum expected ambient condition. If the OPA551 or OPA552 is to be used in an application requiring more than 0.5W continuous power dissipation, it is recommended that the DDPAK package option be used. The DDPAK has superior thermal dissipation characteristics and is more easily adapted to a heat sink. Operation from a single power supply (or unbalanced power supplies) can produce even larger power dissipation since a larger voltage can be impressed across the conducting output transistor. Consult Application Bulletin AB-039 for further information on how to calculate or measure power dissipation. Power dissipation can be minimized by using the lowest possible supply voltage. For example, with a 200mA load, the output will swing to within 3.5V of the power supply rails. Power supplies set to no more than 3.5V above the maximum output voltage swing required by the application will minimize the power dissipation. SAFE OPERATING AREA The Safe Operating Area (SOA curves, Figures 3, 4, and 5) shows the permissible range of voltage and current. The curves shown represent devices soldered to a circuit board with no heat sink. The safe output current decreases as the voltage across the output transistor (VS - VO) increases. For further insight on SOA, consult Application Bulletin AB-039. Output short circuits are a very demanding case for SOA. A short circuit to ground forces the full power supply voltage (V+ or V-) across the conducting transistor and produces a typical output current of 380mA. With 30V OPA551, OPA552 www.ti.com SBOS100A power supplies, this creates an internal dissipation of 11.4W. This far exceeds the maximum rating and is not recommended. If operation in this region is unavoidable, use the DDPAK with a heat sink. SAFE OPERATING AREA--8-PIN DIP 1000 IO (mA) 125C 10 85C 1 0.1 10 Power dissipated in the OPA551 or OPA552 will cause the junction temperature to rise. For reliable operation, the junction temperature should be limited to +125C. Many applications will require a heat sink to assure that the maximum operating junction temperature is not exceeded. The heat sink required depends on the power dissipated and on ambient conditions. For heat sinking purposes, the tab of the DDPAK is typically soldered directly to a circuit board copper area. Increasing the copper area improves heat dissipation. Figure 6 shows typical thermal resistance from junction-to-ambient as a function of copper area. 25C 100 1 HEAT SINKING 100 | VS | - | VO | (V) Depending on conditions, additional heat sinking may be required. Aavid Thermal Products Inc. manufactures surface-mountable heat sinks designed specifically for use with DDPAK packages. Further information is available on Aavid's web site, www.aavid.com. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the thermal protection should trigger more than +25C above the maximum expected ambient condition of your application. This produces a junction temperature of +125C at the maximum expected ambient condition. FIGURE 3. DIP-8 Safe Operating Area. SAFE OPERATING AREA--SO-8 1000 25C THERMAL RESISTANCE vs CIRCUIT BOARD COPPER AREA 125C 10 50 85C 1 0.1 1 10 100 | VS | - | VO | (V) FIGURE 4. SO-8 Safe Operating Area. Thermal Resistance, JA (C/W) IO (mA) 100 OPA551, OPA552 Surface-Mount Package 1oz. copper 40 30 20 10 0 0 1 2 3 4 5 Copper Area (inches2) SAFE OPERATING AREA--DDPAK 1000 25C 25C 1" Copper Circuit Board Copper Area IO (mA) 100 125C 10 125C 1" Copper 85C 1 0.1 1 10 100 OPA551, OPA552 Surface-Mount Package | VS | - | VO | (V) FIGURE 5. DDPAK-7 Safe Operating Area. FIGURE 6. DDPAK Thermal Resistance vs Circuit Board Copper Area. OPA551, OPA552 SBOS100A www.ti.com 11 CAPACITIVE LOADS The dynamic characteristics of the OPA551 and OPA552 have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closedloop gain and capacitive load will decrease the phase margin and may lead to gain peaking or oscillations. Figure 7 shows a circuit that preserves phase margin with capacitive load. Figure 8 shows the small-signal step response for the circuit in Figure 7. Consult Application Bulletin AB-028 for more information. can be used to boost output current. The circuit in Figure 10 is capable of supplying output currents up to 1A. Alternatively, the OPA547, OPA548, and OPA549 series power op amps should be considered for high output current drive, along with programmable current limit and output disable capability. R1 R2 "MASTER" +30V RS(1) 10 OPA551 VIN OPA551 RG 4k RS(1) 10 10nF RF 4k OPA551 VI CS 1.8nF CF 220pF RL "SLAVE" -30V NOTE: (1) RS resistors minimize the circulating current that can flow between the two devices due to VOS errors. FIGURE 7. Driving Large Capacitive Loads. SMALL-SIGNAL STEP RESPONSE OPA551, G = -1, CL = 10nF FIGURE 9. Parallel Amplifers Increase Output Current Capability. OPA551 20mV/div R1 R2 +30V TIP29C CF R3(1) 100 Time (2.5s/div) R4 0.2 VO OPA551 VIN R4 0.2 FIGURE 8. Small-Signal Step Response for Figure 7. LOAD TIP30C INCREASING OUTPUT CURRENT In those applications where the 200mA of output current is not sufficient to drive the desired load, output current can be increased by connecting two or more OPA551s or OPA552s in parallel as shown in Figure 9. Amplifier A1 is the "master" amplifier and may be configured in virtually an op amp circuit. Amplifier A2, the "slave", is configured as a unity gain buffer. Alternatively, external output transistors 12 -30V NOTE: (1) R3 provides current limit and allows the amplifier to drive the load when the output is between 0.7V and -0.7V. FIGURE 10. External Output Transistors Boost Output Current Up to 1 Amp. OPA551, OPA552 www.ti.com SBOS100A INPUT PROTECTION The OPA551 and OPA552 feature internal clamp diodes to protect the inputs when voltages beyond the supply rails are encountered. However, input current should be limited to 5mA. In some cases, an external series resistor may be required. Many input signals are inherently current-limtied, therefore, a limiting resistor may not be required. Please consider that a "large" series resistor, in conjunction with the input capacitance, can affect stability. USING THE OPA552 IN LOW GAINS providing the full slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG1 * Z0. The capacitor values shown in Figure 11 are calculated for NG1 = 2 and NG2 = 10 with no adjustment for parasitics. Actual circuit values can be optimized by check the small-signal step response with actual load conditions. Figure 12 shows the small-signal step response of this OPA552, G = -1 circuit with a 500pF load. It is wellbehaved with no tendency to oscillate. If CS and CF were removed, the circuit would be unstable. The OPA552 family is intended for applications with signal gains of 5 or greater, but it is possible to take advantage of their high slew rate in lower gains using an external compensation technique in an inverting configuration. This technique maintains low noise characteristics of the OPA552 architecture at low frequencies. Depending on the application, a small increase in high frequency noise may result. This technique shapes the loop gain for good stability while giving an easily controlled secondorder low-pass frequency response. Considering only the noise gain (non-inverting signal gain) for the circuit of Figure 11, the low frequency noise gain (NG1) will be set by the resistor ratios, while the high frequency noise gain (NG2) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high frequency noise gain. If this noise gain, determined by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole, set by 1/RFCF, is placed correctly, a very well controlled, 2nd-order lowpass frequency response will result. +30V OPA552 RG 1k CS 1.88nF CF 208pF -30V NG1 = 1 + RF/RG = 2 NG2 = 1 + CS/CF = 10 FIGURE 11. Compensation of the OPA552 for G = 1. SMALL-SIGNAL STEP RESPONSE OPA552, G = -1, CL = 500pF 20mV/div OPA552 Time (1s/div) FIGURE 12. Small-Signal Step Response for Figure 11. OPA551, OPA552 SBOS100A RF 1k VIN To choose the values for both CS and CF, two parameters and only three equations need to be solved. First, the target for the high frequency noise gain (NG2) should be greater than the minimum stable gain for the OPA552. In the circuit in Figure 11, a target NG2 of 10 is used. Second, the signal gain of -1 shown in Figure 11 sets the low frequency noise gain to NG1 = 1 + RF/RG (=2 in this example). Using these two gains, knowing the Gain Bandwidth Product (GBP) for the OPA552 (12MHz), and targeting a maximally flat 2nd-order, low-pass Butterworth frequency response (Q = 0.707), the key frequency in the compensation can be found. For the values shown in Figure 11, the f-3dB will be approximately 956kHz. This is less than that predicted by simply dividing the GBP by NG1. The compensation network controls the bandwidth to a lower value while VOUT www.ti.com 13 OFFSET VOLTAGE ERROR CALCULATION The offset voltage (VOS) of the OPA51 and OPA552 is specified with a 30V power supply and the commonmode voltage centered between the supplies (VS/2 = 0V). Additional specifications for power supply rejection and common-mode rejection are provided to allow the user to easily calculate worst-case excepted offset under the conditions of a given application. Power Supply Rejection Ratio (PSRR) is specified in V/V. For the OPA551 and OPA552, worst-case PSRR is 30V/V, which means for each volt of change in total power supply voltage, the offset may shift by up to 30V/V. Common-Mode Rejection Ratio (CMRR) is specified in dB, which can be converted to V/V using the following equation: CMRR in (V/V) = 10[(CMRR in dB)/-20] (1) For the OPA551 and OPA552, the worst-case CMRR at 30mV supply over the full common-mode range is 96dB, or approxmately 15.8V/V. This means that for every volt of change in common-mode, the offset may shift up to 15.8V. These numbers can be used to 14 calculate excursions from the specified offset voltage under different applications conditions. For example, a common application might configure the amplifier with a -48 single supply with -6V common-mode. This configuration represents a 12V variation in power supply: 30V or 60V in the offset specification versus 48V in the application. In addition, this configuration has an 18V variation in common-mode voltage: VS/2 = -24V is the specification for these power supplies, but the common-mode voltage is -6V in the application. Calculation of the worst-case expected offset would be as follows: Worst-case VOS = (2) maximum specified VOS + (power supply variation * PSRR + (common-mode variation * CMRR) VOSwc = 5mV + (12V * 30V/V) + (18V * 15.8V/V) = 5.64mV OPA551, OPA552 www.ti.com SBOS100A PACKAGE OPTION ADDENDUM www.ti.com 16-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) OPA551FA OBSOLETE DDPAK KTW 7 TBD Call TI Call TI OPA551FA/500 ACTIVE DDPAK KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA551FA/500G3 ACTIVE DDPAK KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA551FAKTWT ACTIVE DDPAK KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA551FAKTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA551PA ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA551PAG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA551UA ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA551UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA551UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA551UA/2K5G4 ACTIVE SOIC D 8 OPA551UAE4 ACTIVE SOIC D 8 TBD Call TI 75 Green (RoHS & no Sb/Br) CU NIPDAU Call TI Level-3-260C-168 HR OPA552FA OBSOLETE DDPAK KTW 7 TBD Call TI Call TI OPA552FA/500 ACTIVE DDPAK KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA552FA/500G3 ACTIVE DDPAK KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA552FAKTWT ACTIVE DDPAK KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA552FAKTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR OPA552PA ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA552PAG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA552UA ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA552UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA552UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA552UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA552UAG4 ACTIVE SOIC D 8 CU NIPDAU Level-3-260C-168 HR 75 (1) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Feb-2009 a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing OPA551FA/500 DDPAK KTW 7 OPA551FAKTWT DDPAK KTW OPA551UA/2K5 SOIC D OPA552FA/500 DDPAK OPA552FAKTWT OPA552UA/2K5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 DDPAK KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA551FA/500 DDPAK KTW 7 500 367.0 367.0 45.0 OPA551FAKTWT DDPAK KTW 7 50 367.0 367.0 45.0 OPA551UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA552FA/500 DDPAK KTW 7 500 367.0 367.0 45.0 OPA552FAKTWT DDPAK KTW 7 50 367.0 367.0 45.0 OPA552UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPSF015 - AUGUST 2001 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.410 (10,41) 0.385 (9,78) 0.304 (7,72) -A- 0.006 -B- 0.303 (7,70) 0.297 (7,54) 0.0625 (1,587) H 0.055 (1,40) 0.0585 (1,485) 0.300 (7,62) 0.064 (1,63) 0.045 (1,14) 0.252 (6,40) 0.056 (1,42) 0.187 (4,75) 0.370 (9,40) 0.179 (4,55) 0.330 (8,38) H 0.296 (7,52) A 0.605 (15,37) 0.595 (15,11) 0.012 (0,305) C 0.000 (0,00) 0.019 (0,48) 0.104 (2,64) 0.096 (2,44) H 0.017 (0,43) 0.050 (1,27) C C F 0.034 (0,86) 0.022 (0,57) 0.010 (0,25) M B 0.026 (0,66) 0.014 (0,36) 0~3 AM C M 0.183 (4,65) 0.170 (4,32) 4201284/A 08/01 NOTES: A. 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