_______________General Description
The MAX536/MAX537 combine four 12-bit, voltage-output
digital-to-analog converters (DACs) and four precision
output amplifiers in a space-saving 16-pin package.
Offset, gain, and linearity are factory calibrated to provide
the MAX536’s ±1 LSB total unadjusted error. The
MAX537 operates with ±5V supplies, while the MAX536
uses -5V and +10.8V to +13.2V supplies.
Each DAC has a double-buffered input, organized as
an input register followed by a DAC register. A 16-bit
serial word is used to load data into each input/DAC
register. The serial interface is compatible with either
SPI/QSPI™ or MICROWIRE™, and allows the input and
DAC registers to be updated independently or simulta-
neously with a single software command. The DAC reg-
isters can be simultaneously updated with a hardware
LDAC pin. All logic inputs are TTL/CMOS compatible.
________________________Applications
Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control Devices
Remote Industrial Controls
Microprocessor-Controlled Systems
____________________________Features
♦Four 12-Bit DACs with Output Buffers
♦Simultaneous or Independent Control of Four
DACs via a 3-Wire Serial Interface
♦Power-On Reset
♦SPI/QSPI and MICROWIRE Compatible
♦±1 LSB Total Unadjusted Error (MAX536)
♦Full 12-Bit Performance without Adjustments
♦±5V Supply Operation (MAX537)
♦Double-Buffered Digital Inputs
♦Buffered Voltage Output
♦16-Pin DIP/SO Packages
______________ Ordering Information
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
________________________________________________________________ Maxim Integrated Products 1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUTC
OUTD
VDD
TP
AGND
VSS
OUTA
OUTB
TOP VIEW
MAX536
MAX537
REFCD
SDO
SCK
CS
SDI
LDAC
DGND
REFAB
DIP/SO
+
__________________Pin Configuration
MAX536/MAX537
DAC A
DAC
REG A
INPUT
REG A
DAC B
DAC
REG B
INPUT
REG B
DAC C
DAC
REG C
INPUT
REG C
DAC D
DAC
REG D
INPUT
REG D
DECODE
CONTROL
OUTA
OUTB
OUTC
OUTD
16-BIT
SHIFT
REGISTER
SR
CONTROL
CS SDI SCK
SDO LDAC AGND
DGND VSS TP
VDD
REFAB
REFCD
________________Functional Diagram
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
19-0230; Rev 3; 3/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-
PACKAGE
INL
(LSB)
MAX536ACPE+ 0°C to +70°C 16 PDIP ±0.5
MAX536BCPE+ 0°C to +70°C 16 PDIP ±1
MAX536ACWE+ 0°C to +70°C 16 Wide SO ±0.5
MAX536BCWE+ 0°C to +70°C 16 Wide SO ±1
MAX536AEPE+ -40°C to +85°C 16 PDIP ±0.5
MAX536BEPE+ -40°C to +85°C 16 PDIP ±1
MAX536AEWE+ -40°C to +85°C 16 Wide SO ±0.5
MAX536BEWE+ -40°C to +85°C 16 Wide SO ±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information continued at end of data sheet.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N12
Bits
MAX536A ±1.0
TA = +25°C
MAX536B ±2.0
MAX536AC ±2.0
MAX536BC ±3.0
MAX536AE ±2.5
Total Unadjusted Error (Note 1) TUE
TA = TMIN to TMAX
MAX536BE ±3.5
LSB
MAX536A ±0.15 ±0.50
Integral Nonlinearity INL
MAX536B ±1
LSB
Differential Nonlinearity
DNL Guaranteed monotonic ±1
LSB
MAX536A ±2.5
TA = +25°C
MAX536B ±5.0
MAX536AC ±5.0
MAX536BC ±7.5
MAX536AE ±6.1
Offset Error
TA = TMIN to TMAX
MAX536BE ±8.5
mV
RL = ∞-0.1 ±1.0
MAX536_C/E -0.6 ±1.5
Gain Error RL = 5kΩ
MAX536_M ±2.0
LSB
VDD Power-Supply Rejection
Ratio
PSRR TA = +25°C, 10.8V < VDD < 13.2V
±0.02 ±0.125
LSB/V
VSS Power-Supply Rejection Ratio
PSRR TA = +25°C, -5.5V < VDD < -4.5V ±0.03 ±0.30
LSB/V
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
2 ____________________________________________________________________________________________________
VDD to AGND or DGND
MAX536 ............................................................-0.3V to +13.2V
MAX537 .................................................................-0.3V to +7V
VSS to AGND or DGND ............................................-7V to +0.3V
SDI, SCK, CS, LDAC, TP, SDO
to AGND or DGND..................................-0.3V to (VDD + 0.3V)
REFAB, REFCD to AGND or DGND ..........-0.3V to (VDD + 0.3V)
OUT_ to AGND or DGND ..........................................VDD to VSS
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) .................842mW
Wide SO (derate 9.52mW/°C above +70°C).................762mW
Operating Temperature Ranges
MAX53_AC_E/BC_E.............................................0°C to +70°C
MAX53_AE_E/BE_E ..........................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
ELECTRICAL CHARACTERISTICS—MAX536
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
MATCHING PERFORMANCE (TA = +25°C)
MAX536A
±1.0
Total Unadjusted Error TUE MAX536B
±2.0
LSB
Gain Error
±0.1 ±1.0
LSB
MAX536A
±1.2 ±2.5
Offset Error MAX536B
±1.2 ±5.0
mV
Integral Nonlinearity INL
±0.2 ±1.0
LSB
REFERENCE INPUT
Reference Input Range REF 0
V
D D
- 4
V
Reference Input Resistance RREF Code dependent, minimum at code 555 5kΩ
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth VREF = 2VP-P
700
kHz
VREF = 10VP-P at 400Hz -100
Reference Feedthrough Input code =
all 0s VREF = 10VP-P at 4kHz -82 dB
Total Harmonic Distortion Plus
Noise
THD+N
VREF = 2.0VP-P at 50kHz
0.024
%
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Leakage Current VIN = 0V or VDD 1.0 µA
Input Capacitance (Note 2) 10 pF
DIGITAL OUTPUT (SDO)
Output Low Voltage VOL SDO sinking 5mA
0.13 0.40
V
Output Leakage Current SDO = 0V to VDD
±10
µA
DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF)
Voltage Output Slew Rate 5 V/µs
Output Settling Time To ±0.5 LSB of full scale 3 µs
Digital Feedthrough 5
nV-s
Digital Crosstalk (Note 3) VREF = 5V 8
nV-s
POWER SUPPLIES
Positive Supply Range VDD
10.8 13.2
V
Negative Supply Range VSS
-4.5 -5.5
V
TA = +25°C 8 18
Positive Supply Current
(Note 4) IDD TA = TMIN to TMAX 25 mA
TA = +25°C -6 -16
Negative Supply Current
(Note 4) ISS TA = TMIN to TMAX -23 mA
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
tPOR 20 µs
SCK Clock Period tCP 100 ns
SCK Pulse Width High tCH 30 ns
SCK Pulse Width Low tCL 30 ns
tCSS 20 ns
tCSH 10 ns
SDI Setup Time tDS 40 26 ns
SDI Hold Time tDH 0ns
tDO1 1kΩpullup on SDO
to VDD, CLOAD = 50pF
SDO high 78 105 ns
SDO low 50 80
SCK Fall to SDO Valid
Propagation Delay (Note 7) tDO2 1kΩpullup on SDO
to VDD, CLOAD = 50pF
SDO high 81 110 ns
SDO low 53 85
tDV 27 45 ns
tTR 40 60 ns
SCK Rise to CS Fall Delay tCS0 Continuous SCK, SCK edge ignored 20 ns
tCS1 SCK edge ignored 20 ns
LDAC Pulse Width Low tLDAC 30 ns
CS Pulse Width High tCSW 40 ns
Internal Power-On Reset
Pulse Width (Note 2)
CS Fall to SCK Rise
Setup Time
SCK Rise to CS Rise
Hold Time
SCK Rise to SDO Valid
Propagation Delay (Note 6)
CS Fall to SDO Enable
(Note 8)
CS Rise to SDO Disable
(Note 9)
CS Rise to SCK Rise
Hold Time
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
Note 5: All input signals are specified with tR= tF≤5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
TIMING CHARACTERISTICS (Note 5)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS—MAX537
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N12
Bits
MAX537A ±0.15 ±0.50
Integral Nonlinearity INL
MAX537B ±1
LSB
Differential Nonlinearity
DNL Guaranteed monotonic ±1
LSB
MAX537A ±3.0
TA = +25°C
MAX537B ±6.0
MAX537AC ±6.0
MAX537BC ±9.0
MAX537AE ±7.0
Offset Error
TA = TMIN to TMAX
MAX537BE ±11.0
mV
RL = ∞-0.3 ±1.5
Gain Error
RL = 5kΩ-0.8 ±3.0
LSB
V
D D
P ow er - S up p l y Rej ecti on Rati o
PSRR TA = +25°C, 4.5V ≤ VDD ≤ 5.5V ±0.01 ±0.5
LSB/V
V
S S
P ow er - S up p l y Rej ecti on Rati o
PSRR TA = +25°C, -5.5V ≤ VSS ≤ -4.5V ±0.02 ±0.7
LSB/V
MATCHING PERFORMANCE (TA = +25°C)
Gain Error
±0.1 ±1.25
LSB
MAX537A ±0.3 ±3.0
Offset Error
MAX537B ±0.3 ±6.0
mV
Integral Nonlinearity
INL ±0.35 ±1.0
LSB
REFERENCE INPUT
Reference Input Range
REF 0 V
D D -
2.2
V
Reference Input Resistance
RREF Code dependent, minimum at code 555 hex 5
kΩ
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth VREF = 2VP-P
700
kHz
VREF = 10VP-P at
400Hz -100
Reference Feedthrough Input code = all 0s VREF = 10VP-P at
4kHz
-82
dB
Total Harmonic Distortion Plus
Noise
THD+N
VREF = 850mVP-P at 100kHz
0.024
%
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage
VIH 2.4
V
Input Low Voltage
VIL 0.8
V
Input Leakage Current
VIN = 0V or VDD 1.0
µA
Input Capacitance (Note 2)
10
pF
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
DIGITAL OUTPUT (SDO)
Output High Voltage VOH SDO sourcing 2mA VDD -
0.5
VDD -
0.25
V
Output Low Voltage
VOL SDO sinking 2mA 0.13 0.40
V
DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF)
Voltage Output Slew Rate
5
V/µs
Output Settling Time
To ±0.5 LSB of full scale 5
µs
Digital Feedthrough
5
nV-s
Digital Crosstalk (Note 3)
5
nV-s
POWER SUPPLIES
Positive Supply Range
VDD 4.5 5.5
V
Negative Supply Range
VSS -4.5 -5.5
V
TA = +25°C 5.5 12
Positive Supply Current (Note 4) IDD
TA = TMIN to TMAX 16
mA
TA = +25°C -4.7 -10
Negative Supply Current (Note 4)
ISS
TA = TMIN to TMAX -14
mA
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset Pulse
Width (Note 2) tPOR 50 µs
SCK Clock Period
tCP 100
ns
SCK Pulse Width High
tCH MAX537_C/E 35
ns
SCK Pulse Width Low
tCL MAX537_C/E 35
ns
CS Fall to SCK Rise Setup Time
tCSS MAX537_C/E 40
ns
SCK Rise to CS Rise Hold Time
tCSH 0
ns
SDI Setup Time
tDS MAX537_C/E 40 24
ns
SDI Hold Time tDH 0ns
SCK Rise to SDO Valid
Propagation Delay (Note 6) tDO1 CLOAD = 50pF, MAX537_C/E
116
200 ns
SCK Fall To SDO Valid
Propagation Delay (Note 7)
tDO2 CLOAD = 50pF, MAX537_C/E
123
210 ns
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
Note 5: All input signals are specified with tR= tF≤5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 10: When disabled, SDO is internally pulled high.
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
CS Fall to SDO Enable
tDV CLOAD = 50pF, MAX537_C/E 75 140
ns
CS Rise to DSO Disable (Note 10)
tTR CLOAD = 50pF, MAX537_C/E 70 130 ns
SCK Rise to CS Fall Delay
tCSO Continuous SCK, SCK edge ignored 35
ns
CS Rise to SCK Rise Hold Time
tCS1 SCK edge ignored, MAX537_C/E 35
ns
LDAC Pulse Width High
tLDAC MAX537_C/E 50
ns
CS Pulse Width High
tCSW MAX537_C/E 100
ns
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
8 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
INL ERROR (LSB)
-1.0
0
REFERENCE VOLTAGE (V)
MAX536/7-01
4 8 12 16
--0.6
-0.2
0.2
0.6
1.0
VDD = +15V
VDD = +12V
VSS = -5V
MAX536
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
1k 10k 100k
MAX536
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
MAX536/7-02
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
1M 10M
-50
-40
-30
-20
-10
10
20
0
REFAB SWEPT 2VP-P
VOUTA MONITORED
10 100 200
MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
MAX1536/7-03
FREQUENCY (kHz)
THD + NOISE (%)
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
DAC CODE = ALL 1s
REFAB = 10VP-P
RL = 10kΩ, CL = 100pF
RL = NO LOAD, CL = 0pF
1
-5
0.1 10 1000
MAX536
FULL-SCALE ERROR vs. LOAD
-4
MAX536/7-04
LOAD (kΩ)
FULL-SCALE ERROR (LSB)
-3
-2
-1
1100
0
MAX536
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT (mA)
-10
-60
TEMPERATURE (°C)
MAX536/7-05
-6
-2
2
6
10
-20 20 60 100 140
VDD = +15V
VSS = -5V
ISS
IDD
INPUT CODE = ALL 0s
500µs/div
REFAB,
5V/div
0V
OUTA,
100µV/div
MAX536
REFERENCE FEEDTHROUGH AT 400Hz
INPUT CODE = ALL 0s
MAX536
REFERENCE FEEDTHROUGH AT 4kHz
50µs/div
REFAB,
5V/div
0V
OUTA,
200µV/div
10 100 200
MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
MAX1536/7-03b
FREQUENCY (kHz)
THD + NOISE (%)
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
DAC CODE = ALL 1s
REFAB = 5VP-P
RL = NO LOAD, CL = 0pF
RL = 10kΩ, CL = 100pF
MAX536
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 9
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
VDD = +15V, VSS = -5V, REFAB = 5V, CL = 100pF, RL = 10kΩ
MAX536
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
5µs/div
CS,
5V/div
OUTA,
2V/div
VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ
MAX536
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
1µs/div
CS,
5V/div
OUTA,
5V/div
OUTA,
5mV/div
VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ
MAX536
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
1µs/div
CS,
5V/div
OUTA,
5V/div
OUTA,
-10V OFFSET
5mV/div
VDD = +15V, VSS = -5V, REFAB = 10V, CS = HIGH,
DIN TOGGLING AT 1⁄2 THE CLOCK RATE,
OUTA = 5V
MAX536
DIGITAL FEEDTHROUGH
SCK,
5V/div
OUTA,
AC-COUPLED,
10mV/div
MAX536
INPUT CODE = ALL 0s
MAX537
REFERENCE FEEDTHROUGH AT 400Hz
500µs/div
REFAB,
1V/div
0V
OUTA,
AC-COUPLED,
100µV/div
INPUT CODE = ALL 0s
MAX537
REFERENCE FEEDTHROUGH AT 4kHz
50µs/div
REFAB,
1V/div
0V
OUTA,
AC-COUPLED,
100µV/div
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
10 ______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
INL ERROR (LSB)
-2.0
0
VREF (V)
MAX536/7-06
12 45
-0.5
0.5
1.0
2.0
MAX537
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
-1.5
-1.0
0
1.5
3
VDD = +5V
VSS = -5V
1k 10k 100k
MAX537
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
MAX536/7-07
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
1M 10M
-50
-40
-30
-20
-10
10
20
0
REFAB SWEPT 2VP-P
VOUTA MONITORED
10 100 200
MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX1536/7-14
FREQUENCY (kHz)
THD + NOISE (%)
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
REFAB = 2.5VP-P
RL = 10kΩ, CL = 100pF
RL = NO LOAD, CL = 0pF
MAX537
10 100 200
MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX1536/7-09
FREQUENCY (kHz)
THD + NOISE (%)
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
REFAB = 1VP-P
RL = 10kΩ, CL = 100pF
RL = NO LOAD, CL = 0pF
-4
-3
0.1 10 1000
MAX537
FULL-SCALE ERROR vs. LOAD
-2
MAX536/7-10
LOAD (kΩ)
FULL-SCALE ERROR (LSB)
-1
0
1
1 100
2
MAX537
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT (mA)
-5
-60
TEMPERATURE (°C)
MAX536/7-11
-3
-1
1
3
5
-20 20 60 100 140
VDD = +5V
VSS = -5V
ISS
IDD
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 11
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ
MAX537
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
5µs/div
CS,
5V/div
OUTA,
1V/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ
MAX537
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
1µs/div
CS,
5V/div
OUTA,
5mV/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ
MAX537
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
1µs/div
CS,
5V/div
OUTA,
5mV/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CS = HIGH,
DIN TOGGLING AT 1⁄2 THE CLOCK RATE,
OUTA = 1.25V
MAX537
DIGITAL FEEDTHROUGH
100ns/div
SCK,
5V/div
OUTA,
AC-COUPLED,
20mV/div
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX537
MAX536/MAX537
_______________Detailed Description
The MAX536/MAX537 contain four 12-bit voltage-output
DACs that are easily addressed using a simple 3-wire
serial interface. They include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see the Functional Diagram on the front page).
The DACs are “inverted” R-2R ladder networks that
convert 12-bit digital inputs into equivalent analog out-
put voltages in proportion to the applied reference-volt-
age inputs. DAC A and DAC B share the REFAB refer-
ence input, while DAC C and DAC D share the REFCD
reference input. The two reference inputs allow different
full-scale output voltage ranges for each pair of DACs.
Figure 1 shows a simplified circuit diagram of one of
the four DACs.
Reference Inputs
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets
the full-scale output voltage for its two correspond-
ing DACs. The REFAB/REFCD voltage range is 0V to
(VDD - 4V) for the MAX536 and 0V to (VDD - 2.2V) for the
MAX537. The output voltages VOUT_ are represented by
a digitally programmable voltage source as:
VOUT_ = NB(VREF)/4096
where NBis the numeric value of the DAC’s binary input
code (0 to 4095) and VREF is the reference voltage.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
12 ______________________________________________________________________________________
______________________________________________________________Pin Description
PIN NAME FUNCTION
OUTB DAC B Output Voltage
2OUTA DAC A Output Voltage
3 VSS Negative Power Supply
AGND Analog Ground
5REFAB Reference Voltage Input for DAC A and DAC B
6DGND Digital Ground
7LDAC
8SDI Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge.
9CS
10 SCK
11 SDO
12 REFCD Reference Voltage Input for DAC C and DAC D
13 TP Test Pin. Connect to VDD for proper operation.
14 VDD Positive Power Supply
15 OUTD DAC D Output Voltage
1
4
16 DAC C Output Voltage
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input
registers to their respective DAC registers.
Chip-Select Input (active low). A low level on CS enables the input shift register and SDO.
On CS’s rising edge, data is latched into the appropriate register(s).
Shift Register Clock Input
Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low.
For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pullup to VDD.
OUTC
VOUT
SHOWN FOR ALL 1s ON DAC
D0 D9 D10 D11
2R 2R 2R 2R 2R
RRR
REF
AGND
Figure 1. Simplified DAC Circuit Diagram
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
The input impedance at each reference input is code
dependent, ranging from a low value of typically 6kΩ
(with an input code of 0101 0101 0101) to a high value
of 60kΩ(with an input code of 0000 0000 0000). Since
the input impedance at the reference pins is code
dependent, load regulation of the reference source is
important.
The REFAB and REFCD reference inputs have a 5kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance becomes 2.5kΩ.
The reference input capacitance is also code depen-
dent and typically ranges from 125pF to 300pF.
Output Buffer Amplifiers
All MAX536/MAX537 voltage outputs are internally
buffered by precision unity-gain followers with a typical
slew rate of 5V/µs for the MAX536 and 3V/µs for the
MAX537.
With a full-scale transition at the MAX536 output (0 to
8V or 8V to 0), the typical settling time to ±0.5 LSB is
3µs when loaded with 5kΩin parallel with 100pF (loads
less than 5kΩdegrade performance).
With a full-scale transition at the MAX537 output (0 to
2.5V or 2.5V to 0), the typical settling time to ±0.5 LSB
is 5µs when loaded with 5kΩin parallel with 100pF
(loads less than 5kΩdegrade performance).
Output dynamic responses and settling performances
of the MAX536/MAX537 output amplifier are shown in
the Typical Operating Characteristics.
Serial-Interface Configurations
The MAX536/MAX537’s 3-wire or 4-wire serial interface is
compatible with both MICROWIRE (Figure 2) and
SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied
either high or low for a 3-wire interface, or used as the
fourth input with a 4-wire interface. The connection
between SDO and the serial-interface port is not neces-
sary, but may be used for data echo. (Data held in the
shift register of the MAX536/MAX537 can be shifted out
of SDO and returned to the microprocessor for data veri-
fication; data in the MAX536/MAX537 input/DAC regis-
ters cannot be read.)
With a 3-wire interface (CS, SCK, SDI) and LDAC tied
high, the DACs are double-buffered. In this mode,
depending on the command issued through the serial
interface, the input register(s) may be loaded
without affecting the DAC register(s), the DAC register(s)
can be loaded directly, or all four DAC registers may be
simultaneously updated from the input registers. With a 3-
wire interface (CS, SCK, SDI) and LDAC tied low (Figure
SCK
SDI
SDO*
CS
LDAC**
SK
SO
SI*
I/O
I/O
MAX536
MAX537
MICROWIRE
PORT
5V
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
†THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
†RP
1kΩ
Figure 2. Connections for MICROWIRE Figure 3. Connections for SPI/QSPI
SDO*
SDI
SCK
CS
LDAC**
MISO*
MOSI
SCK
I/O
I/O
SPI/QSPI
PORT
SS
5V
CPOL = 0, CPHA = 0
*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
MAX536
MAX537
†RP
1kΩ
†THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
_______________________________________________________________________________________ 13
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
14 ______________________________________________________________________________________
CS
SCK
SDI
SDO
LDAC*
tCSO
tCSS tCL
tCH tCP
tDO1 tTR
tCSW
tCSI
tLDAC
tDO2
tCSH
tDS tDH
tDV
*USE OF LDAC IS OPTIONAL
Figure 6. Detailed Serial-Interface Timing Diagram
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD)
Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC
;;
;
;;
CS
SCK
SDI
SDO
MSB
MSB FROM
PREVIOUS WRITE
LSB
LSB FROM
PREVIOUS WRITE
D15 D14 D13 D2 D1 D0
..........
Q15 Q0
COMMAND
EXECUTED
..........
..........
...........
9
816
1
;
;
;;;
CS
SCK
SDI
SDO
MSB
MSB FROM
PREVIOUS WRITE
LSB
LSB FROM
PREVIOUS WRITE
D15 D14 D13 D2 D1 D0
..........
Q15 Q0
INPUT REGISTER(S)
UPDATED
..........
..........
..........
98161
DACs
UPDATED
LDAC
4), the DAC registers remain transparent. Any time an
input register is updated, the change appears at the DAC
output with the rising edge of CS.
The 4-wire interface (CS, SCK, SDI, LDAC) is similar to
the 3-wire interface with
LDAC
tied high, except
LDAC
is
a hardware input that simultaneously and asynchronously
loads all DAC registers from their respective input regis-
ters when driven low (Figure 5).
Serial-Interface Description
The MAX536/MAX537 require 16 bits of serial data. Data is
sent MSB first and can be sent in two 8-bit packets or one
16-bit word (
CS
must remain low until 16 bits are trans-
ferred). The serial data is composed of two DAC address
bits (A1, A0), two control bits (C1, C0), and the 12 data bits
D11…D0 (Figure 7). The 4-bit address/control code deter-
mines the following: 1) the register(s) to be updated and/or
the status of the input and DAC registers (i.e., whether they
are in transparent or latch mode), and 2) the edge on which
data is clocked out of SDO.
Figure 6 shows the serial-interface timing requirements. The
chip-select pin (CS) must be low to enable the DAC’s serial
interface. When CS is high, the interface control circuitry is
disabled and the serial data output pin (SDO) is driven high
(MAX537) or is a high-impedance open drain (MAX536). CS
must go low at least t
CSS
before the rising serial clock (SCK)
edge to properly clock in the first bit. When CS is low, data is
clocked into the internal shift register via the serial data input
pin (SDI) on SCK’s rising edge. The maximum guaranteed
clock frequency is 10MHz. Data is latched into the appropri-
ate MAX536/MAX537 input/DAC registers on CS’s rising
edge.
Interface timing is optimized when serial data is clocked out
of the microcontroller/microprocessor on one clock edge
and clocked into the MAX536/MAX537 on the other edge.
Table 1 lists the serial-interface programming commands.
For certain commands, the 12 data bits are “don’t cares”.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simultane-
ously loaded with the same digital code from the input shift
register. The NOP (no operation) command allows the regis-
ter contents to be unaffected and is useful when the
MAX536/MAX537 are configured in a daisy-chain (see the
Daisy-Chaining Devices section). The command to change
the clock edge on which serial data is shifted out of the
MAX536/MAX537 SDO pin also loads data from all input reg-
isters to their respective DAC registers.
Serial-Data Output
The serial-data output, SDO, is the internal shift register’s
output. The MAX536/MAX537 can be programmed so that
data is clocked out of SDO on SCK’s rising (Mode 1) or
falling (Mode 0) edge . In Mode 0, output data at SDO lags
input data at SDI by 16.5 clock cycles, maintaining compati-
bility with MICROWIRE, SPI/QSPI, and other serial interfaces.
In Mode 1, output data lags input data by 16 clock cycles.
On power-up, SDO defaults to Mode 1 timing.
For the MAX536, SDO is an open-drain output that should be
pulled up to +5V. The data sheet timing specifications for
SDO use a 1kΩpullup resistor. For the MAX537, SDO is a
complementary output and does not require an external
pullup.
Test Pin
The test pin (TP) is used for pre-production analysis of the IC.
Connect TP to VDD for proper MAX536/MAX537 operation.
Failure to do so affects DAC operation.
Daisy-Chaining Devices
Any number of MAX536/MAX537s can be daisy-chained by
connecting the SDO pin of one device (with a pullup resistor,
if appropriate) to the SDI pin of the following device in the
chain (Figure 8).
Since the MAX537’s SDO pin has an internal active pullup,
the SDO sink/source capability determines the time required
to discharge/charge a capacitive load. Refer to the serial
data out VOH and VOL specifications in the Electrical
Characteristics.
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 15
MSB ..................................................................................LSB
16 Bits of Serial Data
Control
Bits
Data Bits
MSB.............................................LSB
A1 A0 C1 C0 D11................................................D0
12 Data Bits
4 Address/
Control Bits
Address
Bits
Figure 7. Serial-Data Format (MSB Sent First)
MAX536/MAX537
When daisy-chaining MAX536s, the delay from
CS
low to SCK high (tCSS) must be the greater of:
tDV + tDS
or
tTR + tRC + tDS - tCSW
where tRC is the time constant of the external pullup resistor
(Rp) and the load capacitance (C) at SDO. For tRC < 20ns,
tCSS is simply tDV + tDS. Calculate tRC from the following
equation:
tRC = Rp(C) ln
where VPULLUP is the voltage to which the pullup resistor is
connected.
Additionally, when daisy-chaining devices, the maximum
clock frequency is limited to:
1
fSCK(max) = ——————————————
2 (tDO + tRC - 38ns + tDS)
For example, with tRC = 23ns (5V ±10% supply with
Rp= 1kΩand C = 30pF), the maximum clock frequency is
8.7MHz.
Figure 9 shows an alternate method of connecting sev
eral
MAX536/MAX537s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
16 ______________________________________________________________________________________
VPULLUP
VPULLUP - 2.4V
Table 1. Serial-Interface Programming Commands
“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.
Mode 0, DOUT clocked out on SCK’s falling edge. All DACs
updated from their respective input registers.
Mode 1 (default condition at power-up), DOUT clocked out on
SCK’s rising edge. All DACs updated from their respective
input registers.
Load DAC D input register; DAC D is immediately updated.012-bit DAC data1X11
Load DAC C input register; DAC C is immediately updated.012-bit DAC data1X01
Load DAC B input register; DAC B is immediately updated.012-bit DAC data1X10
Load DAC A input register; DAC A is immediately updated.012-bit DAC data10 X0
XXXXXXXXXXXXX0101
XXXXXXXXXXXXX0111
Update all DACs from their respective input registers.1XXXXXXXXXXXX01X0
No operation (NOP)XXXXXXXXXXXXX001X
Load all DACs from shift register.X12-bit DAC data000X
Load input register D; all DAC registers updated.112-bit DAC data1111
Load input register C; all DAC registers updated.112-bit DAC data1101
Load input register B; all DAC registers updated.112-bit DAC data1110
Load input register A; all DAC registers updated.112-bit DAC data1100
Load DAC D input register; DAC output unchanged.112-bit DAC data1011
Load DAC C input register; DAC output unchanged.112-bit DAC data1001
Load DAC B input register; DAC output unchanged.112-bit DAC data1010
Load DAC A input register; DAC output unchanged.112-bit DAC data1000
D11…D0C0C1A0A1 FUNCTIONLDAC
16-BIT SERIAL WORD
()
[]
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 17
DIN
CS
TO OTHER
SERIAL DEVICES
MAX536
MAX537
SCK
SDI
CS
SDO
+5V +5V +5V
RP*
1kΩ
MAX536
MAX537
SCK
SDI
CS
SDO
MAX536
MAX537
SCK
SDI
CS
SDO
RP*
1kΩ
RP*
1kΩ
* THE MAX537 HAS AN ACTIVE INTERNAL PULLUP, SO RP IS NOT NECESSARY.
SCK
Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface
TO OTHER
SERIAL DEVICES
MAX536
MAX537
SDI
SCK
LDAC
CS
MAX536
MAX537
SDI
SCK
LDAC
CS
MAX536
MAX537
SDI
SCK
LDAC
CS
DIN
SCK
LDAC
CS1
CS2
CS3
Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are
driven separately, thus controlling which data are written to devices 1, 2, 3…
__________Applications Information
Interfacing to the M68HC11*
PORT D of the 68HC11 supports SPI. The four registers
used for SPI operation are the Serial Peripheral Control
Register, the Serial Peripheral Status Register, the Serial
Peripheral Data I/O Register, and PORT D’s Data Direction
Register. These registers have a default starting location of
$1000.
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose
inputs. Setting bit 6 (SPE) of the Serial Peripheral Control
Register (SPCR) configures PORT D for SPI as follows:
BIT
76543210
NAME
––SS SCK MOSI MISO TXD RXD
Bits 6 and 7 are not used. Writes to these bits are ignored.
The PORT D Data Direction Register (DDRD) deter-
mines whether the port bits are inputs or outputs. Its
configuration is shown below:
Setting DDD_ = 0 configures the port bit as an input, while
setting DDD_ = 1 configures the port bit as an output. Writes
to bits 6 and 7 have no effect.
In SPI mode with MSTR = 1, when a PORT D bit is expected
to be an input (SS, MISO, RXD), the corresponding DDRD bit
(DDD_) is ignored. If the bit is expected to be an output
(SCK, MOSI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.
Table 3. Serial Peripheral Status-Register Definitions
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
18 ______________________________________________________________________________________
NAME
SPIE
SPE
MSTR
CPOL
CPHA
SPR1/0
SPR1 SPR0
0 0 µP clock divided by 2
0 1 µP clock divided by 4
1 0 µP clock divided by 16
1 1 µP clock divided by 32
DEFINITION
When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
Master/Slave select option
Determines the clock phase.
Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a general-
purpose I/O port.
Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to
determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral
Status Register’s SPIF bit or MODF bit is set.
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
clock idles low.
Table 2. Serial Peripheral Control-Register Definitions
DWOM
SPI Clock-Rate Select
NAME DEFINITION
SPIF SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR.
WCOL
MODF
The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by read-
ing the SPSR and then accessing the SPDR.
The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
BIT
76543 210
NAME
– – DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 19
Table 4. M68HC11 Programming Code
MAX536/MAX537
SS is an input intended for use in a multimaster environ-
ment. However, SS or unused PORT D bit RXD, TXD, or
possibly MISO (if DAC readback is not used) should be
configured as a general-purpose output and used as CS by
setting the appropriate Data Direction Register bit.
The SPCR configuration (memory location $1028) is shown
below:
When MSTR = 1 in the SPCR, a write to the Serial
Peripheral Data I/O Register (SPDR), located at memory
location $102A, initiates the transmission/reception of
data. The data transfer is monitored and the appropri-
ate flags are set in the Serial Peripheral Status
Register (SPSR).
The SPSR configuration is shown below:
An example of 68HC11 programming code for a
two-byte SPI transfer to the MAX536/MAX537 is given in
Table 4. SS is used for CS, the high byte of MAX536/
MAX537 digital data is stored in memory location $0100,
and the low byte is stored in memory location $0101.
Interfacing to Other Controllers
When using MICROWIRE, refer to the section on Inter-
facing to the M68HC11 for guidance, since MICROWIRE
can be considered similar to SPI when CPOL = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Bit-
pushing involves arbitrarily assigning I/O port bits as
interface control lines, and then writing to the port each
time a signal transition is required.
Unipolar Output
For a unipolar output, the output voltages and the reference
inputs are the same polarity. Figure 10 shows the
MAX536/MAX537 unipolar output circuit, which is also the typ-
ical operating circuit. Table 5 lists the unipolar output codes.
Bipolar Output
The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
and two resistors are required per DAC. With R1 = R2:
VOUT = VREF [(2NB/4096) - 1]
where NBis the numeric value of the DAC’s binary input
code. Table 6 shows digital codes and corresponding
output voltages for Figure 11’s circuit.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
20 ______________________________________________________________________________________
DAC CONTENTS ANALOG OUTPUT
MSB LSB
4095
1111 1111 1111 +VREF ( ——— )
4096
2049
1000 0000 0001 +VREF ( ——— )
4096
2048 +VREF
1000 0000 0000 +VREF ( ——— ) = ————
4096 2
2047
0111 1111 1111 +VREF ( ——— )
4096
1
0000 0000 0001 +VREF ( ——— )
4096
0000 0000 0000 0V
DAC CONTENTS ANALOG OUTPUT
MSB LSB
2047
1111 1111 1111 +VREF ( ——— )
2048
1
1000 0000 0001 +VREF ( ——— )
2048
1000 0000 0000 0V
1
0111 1111 1111 -VREF ( ——— )
2048
2047
0000 0000 0001 -VREF ( ——— )
2048
2048
0000 0000 0000 -VREF ( ——— ) = -VREF
2048
Table 5. Unipolar Code Table
Table 6. Bipolar Code Table
NOTE: 1 LSB = (VREF) ( 4096 )
1
BIT
76543210
NAME
SPIE SPE
DWOM
MSTR CPOL CPHA SPR1 SPR0
SETTING AFTER RESET
00 0 0 0 1 U
*U*
SETTING FOR TYPICAL SPI COMMUNICATION
0101000
** 1**
*U = Unknown
**Depends on µP clock frequency.
Always configure the 68HC11 as the “master” controller
and the MAX536/MAX537 as the “slave” device.
BIT
765 4 321 0
NAME
SPIF
WCOL
– MODF – – – –
RESET CONDITIONS
000 0 000 0
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 21
MAX536
MAX537
DAC A
DAC B
DAC C
DAC D
OUTA
2
1
16
15
OUTB
OUTC
OUTD
DGNDAGND
VSS
346
-5V
REFAB REFCD
13
14
125
REFERENCE INPUTS +12V (+5V)
NOTE: ( ) ARE FOR MAX537.
VDD TP
Figure 10. Unipolar Output Circuit Figure 11. Bipolar Output Circuit
VREF
DAC
OUTPUT
R1 R2
+12V (+5V)
VOUT
–5V
NOTES: ( ) ARE FOR MAX537.
VREF IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537.
R1 = R2 = 10kΩ 0.1%
MAX536
MAX537
DAC B
OUTB
MAX536/MAX537
10kΩ
15kΩ
REFAB TP VDD
VSS AGND DGND
643
-5V
1
14135
+12V
(+5V)
AC
REFERENCE
INPUT
+4V (+750mV)
-4V
(-750mV)
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
DAC A OUTA
MAX536/MAX537
REFAB TP VDD
VSS DGND
63
-5V
2
14135
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
+
VIN
-
+
VBIAS
-
AGND
4
+12V (+5V)
Figure 12. AC Reference Input Circuit Figure 13. AGND Bias Circuit
MAX536/MAX537
Using an AC Reference
In applications where the reference has AC signal compo-
nents, the MAX536/MAX537 have multiplying capability
within the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to the
reference input where the AC signal is offset before being
applied to REFAB/REFCD. The reference voltage must
never be more negative than DGND.
The MAX536’s total harmonic distortion plus noise
(THD+N) is typically less than 0.012%, given a 5VP-P signal
swing and input frequencies up to 35kHz, or given a 2VP-P
swing and input frequencies up to 50kHz. The typical -3dB
frequency is 700kHz as shown in the Typical Operating
Characteristics graphs.
For the MAX537, with an input signal amplitude of
0.85mVP-P, THD+N is typically less than 0.024% with a
5kΩload in parallel with 100pF and input frequencies up
to 100kHz, or with a 2kΩload in parallel with 100pF and
input frequencies up to 95kHz.
Offsetting AGND
AGND can be biased from DGND to the reference voltage
to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage VOUTA is:
VOUTA = VBIAS + NB(VIN)
where VBIAS is the positive offset voltage (with respect
to DGND) applied to AGND, and NBis the numeric
value of the DAC’s binary input code. Since AGND is
common to all four DACs, all outputs will be offset by
VBIAS in the same manner. As the voltage at AGND
increases, the DAC’s resolution decreases because its
full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
Power-Supply Considerations
On power-up, VSS should come up first, VDD next, then
REFAB or REFCD. If supply sequencing is not possible,
tie an external Schottky diode between VSS and AGND
as shown in Figure 14. On power-up, all input and DAC
registers are cleared (set to zero code) and SDO is in
Mode 0 (serial data is shifted out of SDO on the clock’s
rising edge).
For rated MAX536 performance, VDD should be 4V
higher than REFAB/REFCD and should be between
10.8V and 13.2V. When using the MAX537, VDD should
be at least 2.2V higher than REFAB/REFCD and should
be between 4.75V and 5.5V. Bypass both VDD and VSS
with a 4.7µF capacitor in parallel with a 0.1µF capacitor
to AGND. Use short lead lengths and place the bypass
capacitors as close to the supply pins as possible.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest quality ground available.
Good PCB ground layout minimizes crosstalk between
DAC outputs, reference inputs, and digital inputs.
Reduce crosstalk by keeping analog lines away from
digital lines. Wire-wrapped boards are not recommend-
ed.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
22 ______________________________________________________________________________________
MAX536
MAX537
1N5817
3
4
VSS
AGND
Figure 14. When VSS and VDD cannot be sequenced, tie a
Schottky diode between VSS and AGND.
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 23
Ordering Information (continued)
+Denotes a lead(Pb)-free/RoHS-compliant package.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 PDIP P16+9 21-0043 —
16 SO W16+7 21-0042 90-0107
PART TEMP RANGE PIN-
PACKAGE
INL
(LSB)
MAX537ACPE+ 0°C to +70°C 16 PDIP ±0.5
MAX537BCPE+ 0°C to +70°C 16 PDIP ±1
MAX537ACWE+ 0°C to +70°C 16 Wide SO ±0.5
MAX537BCWE+ 0°C to +70°C 16 Wide SO ±1
MAX537AEPE+ -40°C to +85°C 16 PDIP ±0.5
MAX537BEPE+ -40°C to +85°C 16 PDIP ±1
MAX537AEWE+ -40°C to +85°C 16 Wide SO ±0.5
MAX537BEWE+ -40°C to +85°C 16 Wide SO ±1
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/94 Initial release —
3 3/11 Removed dice and ceramic SB packages and changed voltage supply
specifications 1–7, 13, 21, 22, 23