ADF7241
Rev. 0 | Page 50 of 72
WRITING TO THE ADF7241
Block Write
Packet RAM memory locations can be written to in block
format using the SPI_PKT_WR. The SPI_PKT_WR command
is 0x10. This command provides pointer-based write access to
the packet RAM. The address of the location written to is calcu-
lated from the base address in Register txpb, Field tx_pkt_base
(0x314[7:0]), plus an index. The index is zero for the first data
word following the command word and is auto-incremented
for each consecutive data word written. The first data word follow-
ing an SPI_PKT_WR command is, thus, stored in the location
with Address txpb, Field tx_pkt_base (0x314[7:0]), the second
in packet RAM location with Address txpb, Field tx_pkt_base + 1,
and so on. This feature makes this command efficient for bulk
writes of data that recurrently begin at the same address. Figure 56
shows the access sequence for Command SPI_PKT_WR.
The MCR, BBRAM, and packet RAM memory locations can be
written to in block format using the SPI_MEM_WR command.
The SPI_MEM_WR command code is 00011xxxb, where xxxb
represent Bits[10:8] of the first 11-bit address. If more than one
data byte is written, the write address is automatically incre-
mented for every byte sent until CS is set high, which terminates
the memory access command. See for more details.
The maximum block write for the MCR, packet RAM, and
BBRAM memories are 256 bytes, 256 bytes, and 64 bytes,
respectively. These maximum block-write lengths should not be
exceeded.
Figure 57
Example
Write 0x00 to the rc_cfg register (Location 0x13E).
• The first five bits of the SPI_MEM_WR command are
00011.
• The 11-bit address of rc_cfg is 00100111110.
• The first byte sent is 00011001 or 0x19.
• The second byte sent is 00111110 or 0x3E.
• The third byte sent is 0x00.
Thus, 0x193F00 is written to the part.
Random Address Write
MCR, BBRAM, and packet RAM memory locations can be
written to in random address format using the SPI_MEMR_WR
command. The SPI_MEMR_WR command code is 00001xxxb,
where xxxb represent Bits[10:8] of the 11-bit address. The lower
eight bits of the address should follow this command and then
the data byte to be written to the address. The lower eight bits of
the next address are entered followed by the data for that
address until all required addresses within that block are
written, as shown in Figure 58. Note that the SPI_MEMR_WR
command facilitates the modification of individual elements of
a packet in RX_BUFFER and TX_BUFFER without the need to
download and upload an entire packet.
The address location of a particular byte in RX_BUFFER and
TX_BUFFER in the packet RAM is determined by adding the
relative location of a byte to Address Pointer rx_pkt_base
(Register rxpb; 0x315[7:0]) or Address Pointer tx_pkt_base
(Register txpb; 0x314[7:0]), respectively.
Program RAM Write
The program RAM can only be written to using the memory
block write, as illustrated in Figure 59. The SPI_PRAM_WR
command is 0x1E. The program RAM is organized in eight
pages with a length of 256 bytes each. The code module must be
stored in the program RAM starting from Address 0x0000, or
Address 0x00 in Page 0. The current program RAM page is
selected with Register prampg, Field pram_page (0x313[3:0]).
Prior to uploading the program RAM, the radio controller code
module must be divided into blocks of 256 bytes commensurate
with the size of the program RAM pages. Each 256-byte block is
uploaded into the currently selected program RAM page using
the SPI_PRAM_WR command. Figure 59 illustrates the
sequence required for uploading a code block of 256 bytes to a
PRAM page. The SPI_PRAM_WR command code is followed
by Address Byte 0x00 to align the code block with the base
address of the program RAM page. Figure 60 shows the overall
upload sequence. With the exception of the last page written to
the program RAM, all pages must be filled with 256 bytes of
module code.
READING FROM THE ADF7241
Block Read
Command SPI_PKT_RD provides pointer-based read access
from the packet RAM. The SPI_PKT_RD command is 0x30.
The address of the location to be read is calculated from the base
address in Register rxpb, Field rx_pkt_base, plus an index. The
index is zero for the first readback word. It is auto-incremented
for each consecutive SPI_NOP command. The first data byte
following a SPI_PKT_RD command is invalid and should be
ignored. Figure 61 shows the access sequence for Command
SPI_PKT_RD.
The SPI_MEM_RD command can be used to perform a block
read of MCR, BBRAM, and packet RAM memory locations.
The SPI_MEM_RD command code is 00111xxxb, where xxxb
represent Bits[10:8] of the first 11-bit address. This command is
followed by the remaining eight bits of the address to be read
and then two SPI_NOP commands (dummy byte). The first
byte available after writing the address should be ignored, with
the second byte constituting valid data. If more than one data
byte is to be read, the read address is automatically incremented
for subsequent SPI_NOP commands sent. See Figure 62 for
more details.
Random Address Read
MCR, BBRAM, and Packet RAM memory locations can be read
from in a nonsequential manner using the SPI_MEMR_RD
command. The SPI_MEMR_RD command code is 00101xxxb,
where xxxb represent Bits[10:8] of the 11-bit address. This
command is followed by the remaining eight bits of the address
to be written and then two SPI_NOP commands (dummy byte).