1. General description
The 74HC14; 74HCT14 is a high-speed Si-gate CMOS device and is pin compatible with
Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74HC14; 74HCT14 provides six inverting buffers with Schmitt-trigger action. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
2. Features and benefits
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce eds 20 0 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
74HC14; 74HCT14
Hex inverting Schmitt trigger
Rev. 6 — 19 September 2012 Product data sheet
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 2 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temper ature range Name Description Version
74HC14N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT14N
74HC14D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74HCT14D
74HC14DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; bod y
width 5.3 mm SOT337-1
74HCT14DB
74HC14PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT14PW
74HC14BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
74HCT14BQ
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
(one Schmitt trigger)
mna204
1A 1Y
12
2A 2Y
34
3A 3Y
56
4A 4Y
98
5A 5Y
11 10
6A 6Y
13 12
8
9
10
11
001aac497
12
13
2
1
4
3
6
5
mna025
AY
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 3 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level.
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configura tion DHVQFN14
14
1A V
CC
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND 4Y
001aac498
1
2
3
4
5
6
78
10
9
12
11
14
13
001aac499
14
GND(1)
Transparent top view
3Y 4A
3A 5Y
2Y 5A
2A 6Y
1Y 6A
GND
4Y
1A
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin de scription
Symbol Pin Description
1A to 6A 1, 3, 5, 9, 11, 13 data input 1
1Y to 6Y 2, 4, 6, 8, 10, 12 data output 1
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
Input Output
nA nY
LH
HL
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 4 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages - 500 mW
Table 5. Re commended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC14 74HCT14 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 5 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ Max Min Max Min Max
74HC14
VOH HIGH-level
output voltage VI= VT+ or VT
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI= VT+ or VT
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND; VCC =6.0V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --2.0- 20 - 40A
CIinput
capacitance -3.5- - - - - pF
74HCT14
VOH HIGH-level
output voltage VI= VT+ or VT; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI= VT+ or VT; VCC = 4.5 V
IO = 20 A; - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND; VCC =5.5V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; other pins
at VCC or GND; IO=0A;
VCC = 4.5 V to 5.5 V
- 30 108 - 135 - 147 A
CIinput
capacitance -3.5- - - - - pF
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 6 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
11. Dynamic characteristics
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
Table 7. Dynamic characteristics
GND = 0 V; CL=50pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to
+125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
74HC14
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 2.0 V - 41 125 155 190 ns
VCC = 4.5 V - 15 25 31 38 ns
VCC = 5.0 V; CL=15pF - 12 - - - ns
VCC = 6.0 V - 12 21 26 32 ns
tttransition time see Figure 6 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 n s
VCC = 6.0 V - 6 13 15 19 n s
CPD power dissipation
capacitance per package; VI=GNDtoV
CC [3] -7- - -pF
74HCT14
tpd propagation delay nA to nY; see Figure 6 [1]
VCC = 4.5 V - 20 34 43 51 ns
VCC = 5.0 V; CL=15pF - 17 - - - ns
tttransition time V CC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI=GNDtoV
CC 1.5 V [3] -8- - -pF
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 7 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
12. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
mna722
t
PLH
t
PHL
V
M
V
M
90 %
10 %
V
M
V
M
nY output
nA input
V
I
GND
V
OH
V
OL
t
TLH
t
THL
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC14 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT14 1.3 V 1.3 V 0.1VCC 0.9VCC
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Load circuitry for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
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Product data sheet Rev. 6 — 19 September 2012 8 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
13. Transfer characteristics
14. Transfer characteristics waveforms
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC14 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT14 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 8 and Figure 9.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ Max Min Max Min Max
74HC14
VT+ positive-going
threshold
voltage
VCC = 2.0 V 0.7 1.18 1.5 0.7 1.5 0.7 1.5 V
VCC = 4.5 V 1.7 2.38 3.15 1.7 3.15 1.7 3.15 V
VCC = 6.0 V 2.1 3.14 4.2 2.1 4.2 2.1 4.2 V
VTnegative-going
threshold
voltage
VCC = 2.0 V 0.3 0.52 0.9 0.3 0.9 0.3 0.9 V
VCC = 4.5 V 0.9 1.4 2.0 0.9 2.0 0.9 2.0 V
VCC = 6.0 V 1.2 1.89 2.6 1.2 2.6 1.2 2.6 V
VHhysteresis
voltage VCC = 2.0 V 0.2 0.66 1.0 0.2 1.0 0.2 1.0 V
VCC = 4.5 V 0.4 0.98 1.4 0.4 1.4 0.4 1.4 V
VCC = 6.0 V 0.6 1.25 1.6 0.6 1.6 0.6 1.6 V
74HCT14
VT+ positive-going
threshold
voltage
VCC = 4.5 V 1.2 1.41 1.9 1.2 1.9 1.2 1.9 V
VCC = 5.5 V 1.4 1.59 2.1 1.4 2.1 1.4 2.1 V
VTnegative-going
threshold
voltage
VCC = 4.5 V 0.5 0.85 1.2 0.5 1.2 0.5 1.2 V
VCC = 5.5 V 0.6 0.99 1.4 0.6 1.4 0.6 1.4 V
VHhysteresis
voltage VCC = 4.5 V 0.4 0.56 - 0.4 - 0.4 - V
VCC = 5.5 V 0.4 0.6 - 0.4 - 0.4 - V
Fig 8. Tr ansfer characteristics Fig 9. Transfer characteristics definitions
mna207
VO
VI
VHVT+
VT
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Product data sheet Rev. 6 — 19 September 2012 9 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
a. VCC =2.0V b. V
CC =4.5V
c. VCC =6.0V
Fig 10. Typical 74HC transfer characteristics
0 2.0
50
0
10
20
30
40
0.4 0.8 1.2 1.6
mna846
ICC
(μA)
VI (V)
05
1.0
0
0.2
0.4
0.6
0.8
1234
mna847
ICC
(mA)
VI (V)
0 6.0
ICC
(mA)
VI (V)
1.0
0
0.2
0.4
0.6
0.8
1.2 2.4 3.6 4.8
mna848
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 10 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd =f
i(trICC(AV) +t
fICC(AV))VCC where:
Padd = additional power dissipation (W);
fi= input frequency (MHz);
tr=rise time (ns); 10%to90%;
tf= fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 12
and Figure 13.
An example of a relaxation circuit using the 74HC14; 74HCT14 is shown in Figure 14.
a. VCC =4.5V b. V
CC =5.5V
Fig 11. Typical 74HCT transfer characteristics
05
1.5
0
0.3
0.6
0.9
1.2
1234
mna849
ICC
(mA)
VI (V)
0123 6
1.8
0
0.6
0.3
1.2
1.5
0.9
45
mna850
ICC
(mA)
VI (V)
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Product data sheet Rev. 6 — 19 September 2012 11 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
(1) Positive-going edge.
(2) Negative-going edge.
Fig 12. A verage additional supply current as a function of VCC for 74HC14; linear change of VI between 0.1VCC to
0.9VCC.
0246
400
300
100
0
200
mna852
ICC(AV)
(μA)
VCC (V)
positive - going
edge
negative - going
edge
(1) Positive-going edge.
(2) Negative-going edge.
Fig 13. Average additional supply current as a function of VCC for 74HCT14; linear change of VI between 0.1VCC
to 0.9VCC.
0246
400
300
100
0
200
mna853
VCC (V)
ICC(AV)
(μA)
negative - going
edge
positive - going
edge
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Product data sheet Rev. 6 — 19 September 2012 12 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
For 74HC14 and 74HCT14:
For K-factor see Figure 15
Fig 14. Relaxation oscillator
mna035
R
C
f1
T
---1
KRC
------------------
=
K-factor for 74HC14 K-factor for 74HCT14
Fig 15. Typical K-factor for relaxation oscillator
9
&&
9

DDD




.
9
&&
9
  
DDD






.
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 13 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
16. Package outline
Fig 16. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
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Product data sheet Rev. 6 — 19 September 2012 14 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
Fig 17. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
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Product data sheet Rev. 6 — 19 September 2012 15 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
Fig 18. Package outline SOT337-1 (SSOP14)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
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Product data sheet Rev. 6 — 19 September 2012 16 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
Fig 19. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
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Product data sheet Rev. 6 — 19 September 2012 17 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
Fig 20. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 18 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
17. Abbreviations
18. Revision history
Table 11. Ab br eviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT14 v.6 20120919 Product data sheet - 74HC_HCT14 v.5
Modifications: Figure 15 added (typical K-factor for relaxation oscillator).
74HC_HCT14 v.5 20111219 Product data sheet - 74HC_HCT14 v.4
Modifications: Legal pages updated.
74HC_HCT14 v.4 20110117 Product data sheet - 74HC_HCT14 v.3
74HC_HCT14 v.3 20031030 Product specification - 74HC_HCT14_CNV v.2
74HC_HCT14_CNV v.2 19970826 Product specification - -
74HC_HCT14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 19 September 2012 19 of 21
NXP Semiconductors 74HC14; 74HCT14
Hex inverting Schmitt trigger
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full dat a
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsisten cy or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio nThe information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
19.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
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contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
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authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe propert y or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.