SCBS149D - JULY 1994 - REVISED MARCH 2004 D Members of the Texas Instruments D D D D D D D D D D SN54LVT16646 . . . WD PACKAGE SN74LVT16646 . . . DGG OR DL PACKAGE (TOP VIEW) Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Ioff and Power-Up 3-State Support Hot Insertion Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flowthrough Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) 1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR description/ordering information The 'LVT16646 devices are 16-bit bus transceivers and registers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the LVT16646 devices. ORDERING INFORMATION -40C 85C -40 C to 85 C -55C to 125C ORDERABLE PART NUMBER PACKAGE TA Tube SN74LVT16646DL Tape and reel SN74LVT16646DLR TSSOP - DGG Tape and reel SN74LVT16646DGGR CFP - WD Tube SNJ54LVT16646WD SSOP - DL TOP-SIDE MARKING LVT16646 LVT16646 SNJ54LVT16646WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(& *"!$# #"')"*% " +&#)#("' +&* & &*% ") &.( '*$%&' ('!(*! /(**('0 *"!$#"' +*"#&'1 !"& '" '&#&(*-0 '#-$!& &'1 ") (-+(*(%&&* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCBS149D - JULY 1994 - REVISED MARCH 2004 description/ordering information (continued) Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS DATA I/Os OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 X X X X X Input B1 THRU B8 Unspecified X X X X X Unspecified Input H X X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus Store A, B unspecified Store B, A unspecified L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus The data output functions may be enabled or disabled by various signals at OE and DIR. Data input functions always are enabled; i.e., data at the bus pins are stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OE L DIR L CLKAB CLKBA X X SAB X BUS B BUS A BUS A BUS B SCBS149D - JULY 1994 - REVISED MARCH 2004 SBA L OE L DIR H DIR X X X CLKAB CLKBA X X SAB L SBA X BUS B BUS A BUS A OE X X H CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SAB SBA X X X X X X STORAGE FROM A, B, OR A AND B OE L L DIR L H CLKAB X H or L CLKBA H or L X SAB X H SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCBS149D - JULY 1994 - REVISED MARCH 2004 logic diagram (positive logic) 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 56 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB To Seven Other Channels 29 28 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 1D C1 To Seven Other Channels 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2B1 SCBS149D - JULY 1994 - REVISED MARCH 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . -0.5 V to 7 V Current into any output in the low state, IO: SN54LVT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT16646 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT16646 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54LVT16646 SN74LVT16646 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 5.5 V IOH IOL High-level output current -24 -32 mA Low-level output current 48 64 mA t /v Input transition rise or fall rate 10 10 ns / V High-level input voltage 2 2 0.8 Outputs enabled V V 0.8 V TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SCBS149D - JULY 1994 - REVISED MARCH 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54LVT16646 TYP MAX TEST CONDITIONS VCC = 2.7 V, VCC = MIN to MAX, II = -18 mA IOH = -100 A VCC = 2.7 V, IOH = - 8 mA IOH = - 24 mA VCC = 3 V VCC = 2.7 V VOL VCC = 3 V VCC = 3.6 V, VCC = 0 or MAX, II MIN -1.2 VCC -0.2 2.4 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 IOL = 64 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V V 0.55 0.55 Control inputs A or B ports Ioff VCC = 0, II(hold) VCC = 3 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, VI or VO = 0 to 4.5 V VI = 0.8 V A or B ports VI = 2 V VO = 3 V 1 1 10 10 20 20 5 5 -10 75 75 -75 -75 Outputs high Outputs low Outputs disabled ICC VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 3.5 A -10 100 VO = 0.5 V IO = 0, V V IOH = - 32 mA IOL = 100 A VI = VCC VI = 0 VCC = 3.6 V, VI = VCC or GND -1.2 UNIT VCC -0.2 2.4 2 VCC = 3.6 V ICC SN74LVT16646 TYP MAX MIN A A A 1 1 A -1 -1 A 0.12 0.12 5 5 0.12 0.12 0.2 0.2 mA mA 3.5 pF Cio 12 12 All typical values are at VCC = 3.3 V, TA = 25C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Unused pins at VCC or GND This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. pF ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCBS149D - JULY 1994 - REVISED MARCH 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVT16646 VCC = 3.3 V 0.3 V MIN fclock tw Clock frequency MAX SN74LVT16646 VCC = 2.7 V MIN MAX 150 Pulse duration, CLK high or low tsu Setup time, A or B before CLKAB or CLKBA th Hold time, A or B after CLKAB or CLKBA VCC = 3.3 V 0.3 V MIN 150 MAX VCC = 2.7 V MIN 150 MAX 150 3.3 3.3 3.3 3.3 Data high 1.3 1.4 1.3 1.4 Data low 2.4 3 2.4 3 Data high 0.5 0 0.5 0 Data low 0.6 0.5 0.5 0.5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) SN54LVT16646 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ MAX SN74LVT16646 VCC = 2.7 V MIN MAX 150 CLKBA or CLKAB A or B A or B B or A SBA or SAB A or B OE A or B OE A or B DIR A or B VCC = 3.3 V 0.3 V MIN TYP MAX VCC = 2.7 V MIN UNIT MAX 150 MHz 1.8 6 6.9 1.8 3.8 5.7 6.7 2.1 5.9 6.6 2.1 3.9 5.7 6.5 1.3 4.9 5.6 1.3 3 4.7 5.4 1 4.8 5.8 1 3.1 4.7 5.6 1.4 6.4 7.4 1.4 4 6.2 7.2 1.4 6.4 7.4 1.4 4.3 6.2 7.2 1 5.7 7.4 1 3 5.4 6.4 1 6.5 7.5 1 3.1 5.6 6.5 2.3 6.7 7.1 2.3 4.6 6.5 6.9 2.2 6 6.5 2.2 4.5 5.8 5.9 1 5.9 7.7 1 3.3 5.7 6.7 1.2 5.9 7.3 1.2 3.5 5.8 6.7 1.7 7.3 8.5 1.7 4.7 7.2 DIR A or B tPLZ 1.5 7.8 7.4 1.5 4.9 6.6 All typical values are at VCC = 3.3 V, TA = 25C. These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 8.3 7.2 ns ns ns ns ns ns ns ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SCBS149D - JULY 1994 - REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION 6V S1 500 From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 1.5 V 0V VOH 1.5 V Output 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPHL tPLH 2.7 V Output Control tPLZ Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH 90 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TBD Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) 74LVT16646DGGRE4 ACTIVE TSSOP DGG 56 Call TI 74LVT16646DGGRG4 NRND TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT16646DGGR NRND TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT16646DL NRND SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVT16646DGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT16646DGGR TSSOP DGG 56 2000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C - JANUARY 1995 - REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0-8 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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