SCBS149D − JULY 1994 − REVISED MARCH 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DMembers of the Texas Instruments
Widebus Family
DState-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
DSupport Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
DSupport Unregulated Battery Operation
Down to 2.7 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DBus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
DIoff and Power-Up 3-State Support Hot
Insertion
DDistributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
DFlowthrough Architecture Optimizes
PCB Layout
DLatch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
The ’LVT16646 devices are 16-bit bus
transceivers and registers designed for
low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ′LVT16646 devices.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
SSOP − DL
Tube SN74LVT16646DL
LVT16646
−40°C to 85°CSSOP − DL Tape and reel SN74LVT16646DLR LVT16646
−40 C to 85 C
TSSOP − DGG Tape and reel SN74LVT16646DGGR LVT16646
−55°C to 125°CCFP − WD Tube SNJ54LVT16646WD SNJ54LVT16646WD
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
!"#$%&' #"'('
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+&#)#("' +&* & &*% ") &.( '*$%&' ('!(*! /(**('0
*"!$#"' +*"#&'1 !"& '" '&#&(*-0 '#-$!& &'1 ") (--
+(*(%&&*
Widebus is a trademark of Texas Instruments.
SN54LVT16646 . . . WD PACKAGE
SN74LVT16646 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCBS149D − JULY 1994 − REVISED MARCH 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE
is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the
other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS DATA I/Os
OPERATION OR FUNCTION
OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8
OPERATION OR FUNCTION
X X ↑X X X Input Unspecified†Store A, B unspecified†
XXX ↑X X Unspecified†Input Store B, A unspecified†
H X ↑ ↑ X X Input Input Store A and B data
HX H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
LL X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†The data output functions may be enabled or disabled by various signals at OE and DIR. Data input functions always are enabled; i.e., data at
the bus pins are stored on every low-to-high transition of the clock inputs.
SCBS149D − JULY 1994 − REVISED MARCH 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LDIR
LCLKAB
XCLKBA
XSAB
XSBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
LDIR
HCLKAB
XCLKBA
XSAB
LSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
XDIR
XCLKAB CLKBA
XSAB
XSBA
X
STORAGE FROM
A, B, OR A AND B
LDIR
LCLKAB
XCLKBA
H or L SAB
XSBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
HX
XXX
XX
XL H H or L X H X
↑
↑
↑↑
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE OE
OEOE
Figure 1. Bus-Management Functions
SCBS149D − JULY 1994 − REVISED MARCH 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1 1B1
1D
C1
1D
C1
One of Eight Channels
52
5
3
2
54
55
56
1
1SAB
1CLKAB
1SBA
1CLKBA
1DIR
1OE
To Seven Other Channels
2A1 2B1
1D
C1
1D
C1
One of Eight Channels
42
15
26
27
31
30
29
28
2SAB
2CLKAB
2SBA
2CLKBA
2DIR
2OE
To Seven Other Channels
SCBS149D − JULY 1994 − REVISED MARCH 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) −0.5 V to 7 V. . . .
Current into any output in the low state, IO: SN54LVT16646 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT16646 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVT16646 48 mA. . . . . . . . . . . . . . . . . . . . . . .
SN74LVT16646 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 56°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51−7.
recommended operating conditions (see Note 4)
SN54LVT16646 SN74LVT16646
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCBS149D − JULY 1994 − REVISED MARCH 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVT16646 SN74LVT16646
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V
VCC = MIN to MAX‡, IOH = −100 µA VCC−0.2 VCC−0.2
VOH
VCC = 2.7 V, IOH = − 8 mA 2.4 2.4
V
VOH
VCC = 3 V
IOH = − 24 mA 2V
VCC = 3 V IOH = −32 mA 2
VCC = 2.7 V
IOL = 100 µA 0.2 0.2
VCC = 2.7 V IOL = 24 mA 0.5 0.5
VOL
IOL = 16 mA 0.4 0.4
V
VOL
VCC = 3 V
IOL = 32 mA 0.5 0.5 V
VCC = 3 V IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 3.6 V, VI = VCC or GND
Control inputs
±1±1
VCC = 0 or MAX‡, VI = 5.5 V Control inputs 10 10
I
I
VI = 5.5 V 20 20 µA
II
V
CC
= 3.6 V VI = VCC A or B ports§5 5
µA
VCC = 3.6 V
VI = 0
A or B ports§
−10 −10
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
II(hold)
VCC = 3 V
VI = 0.8 V
A or B ports
75 75
A
II(hold) VCC = 3 V VI = 2 V A or B ports −75 −75 µA
IOZH VCC = 3.6 V, VO = 3 V 1 1 µA
IOZL VCC = 3.6 V, VO = 0.5 V −1 −1 µA
VCC = 3.6 V, IO = 0,
Outputs high 0.12 0.12
I
CC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs low 5 5 mA
ICC
VI = VCC or GND
Outputs disabled 0.12 0.12
mA
∆ICC¶VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND 0.2 0.2 mA
CiVI = 3 V or 0 3.5 3.5 pF
Cio VO = 3 V or 0 12 12 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§Unused pins at VCC or GND
¶This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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SCBS149D − JULY 1994 − REVISED MARCH 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVT16646 SN74LVT16646
VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 150 150 150 150 MHz
twPulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns
tsu
Setup time,
Data high 1.3 1.4 1.3 1.4
ns
tsu
Setup time,
A or B before CLKAB↑ or CLKBA↑Data low 2.4 3 2.4 3 ns
th
Hold time,
Data high 0.5 0 0.5 0
ns
t
h
Hold time,
A or B after CLKAB↑ or CLKBA↑Data low 0.6 0.5 0.5 0.5
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
SN54LVT16646 SN74LVT16646
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
fmax 150 150 MHz
tPLH
CLKBA or
A or B
1.8 6 6.9 1.8 3.8 5.7 6.7
ns
tPHL
CLKBA or
CLKAB A or B 2.1 5.9 6.6 2.1 3.9 5.7 6.5 ns
tPLH
A or B
B or A
1.3 4.9 5.6 1.3 3 4.7 5.4
ns
tPHL A or B B or A 1 4.8 5.8 1 3.1 4.7 5.6 ns
tPLH
SBA or SAB‡
A or B
1.4 6.4 7.4 1.4 4 6.2 7.2
ns
tPHL
SBA or SAB‡
A or B 1.4 6.4 7.4 1.4 4.3 6.2 7.2 ns
tPZH
OE
A or B
1 5.7 7.4 1 3 5.4 6.4
ns
tPZL
OE
A or B 1 6.5 7.5 1 3.1 5.6 6.5 ns
tPHZ
OE
A or B
2.3 6.7 7.1 2.3 4.6 6.5 6.9
ns
tPLZ
OE
A or B 2.2 6 6.5 2.2 4.5 5.8 5.9 ns
tPZH
DIR
A or B
1 5.9 7.7 1 3.3 5.7 6.7
ns
tPZL DIR A or B 1.2 5.9 7.3 1.2 3.5 5.8 6.7 ns
tPHZ
DIR
A or B
1.7 7.3 8.5 1.7 4.7 7.2 8.3
ns
tPLZ
DIR
A or B
1.5 7.8 7.4 1.5 4.9 6.6 7.2
ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
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SCBS149D − JULY 1994 − REVISED MARCH 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 2.7 V
0 V
1.5 V 1.5 V 2.7 V
0 V
2.7 V
0 V
1.5 V 1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 2.7 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
90 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74LVT16646DGGRE4 ACTIVE TSSOP DGG 56 TBD Call TI Call TI
74LVT16646DGGRG4 NRND TSSOP DGG 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT16646DGGR NRND TSSOP DGG 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT16646DL NRND SSOP DL 56 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVT16646DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVT16646DGGR TSSOP DGG 56 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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