MC33163DWR2G - ON SEMICONDUCTOR - Datasheet.Directory

August, 2008 − Rev. 6

1Publication Order Number:

MC34163/D

MC34163, MC33163

3.4 A, Step-Up/Down/

Inverting Switching

Regulators

The MC34163 series are monolithic power switching regulators that

contain the primary functions required for dc−to−dc converters. This

series is specifically designed to be incorporated in step−up,

step−down, and voltage−inverting applications with a minimum

number of external components.

These devices consist of two high gain voltage feedback

comparators, temperature compensated reference, controlled duty

cycle oscillator, driver with bootstrap capability for increased

efficiency, and a high current output switch. Protective features consist

of cycle−by−cycle current limiting, and internal thermal shutdown.

Also included is a low voltage indicator output designed to interface

with microprocessor based systems.

These devices are contained in a 16 pin dual−in−line heat tab plastic

package for improved thermal conduction.

Features

•Output Switch Current in Excess of 3.0 A

•Operation from 2.5 V to 40 V Input

•Low Standby Current

•Precision 2% Reference

•Controlled Duty Cycle Oscillator

•Driver with Bootstrap Capability for Increased Efficiency

•Cycle−by−Cycle Current Limiting

•Internal Thermal Shutdown Protection

•Low Voltage Indicator Output for Direct Microprocessor Interface

•Heat Tab Power Package

•Moisture Sensitivity Level (MSL) Equals 1

•Pb−Free Packages are Available*

Control Logic

and Thermal

Shutdown

LVI

OSC

Voltage

Feedback 2

Voltage

Feedback 1

GND

Timing

Capacitor

VCC

Ipk Sense

Bootstrap

Input

Switch

Emitter

GND

Switch

Collector

Driver

Collector

ILimit

VFB

Figure 1. Representative Block Diagram

(Bottom View)

LVI Output

This device contains 114 active transistors.

116

(Top View)

LVI Output

Voltage Feedback 2

Voltage Feedback 1

GND

Timing Capacitor

VCC

Ipk Sense

Bootstrap Input

Switch

Emitter

GND

Switch Collector

Driver Collector

PIN CONNECTIONS

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

x = 3 or 4

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

PDIP−16

P SUFFIX

CASE 648C

SOIC−16W

DW SUFFIX

CASE 751G

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MC3x163DW

AWLYYWWG

MC3x163P

AWLYYWWG

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

MC34163, MC33163

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MAXIMUM RATINGS (Note 1)

Rating Symbol Value Unit

Power Supply Voltage VCC 40 V

Switch Collector Voltage Range VC(switch) −1.0 to + 40 V

Switch Emitter Voltage Range VE(switch) −2.0 to VC(switch) V

Switch Collector to Emitter Voltage VCE(switch) 40 V

Switch Current (Note 2) ISW 3.4 A

Driver Collector Voltage VC(driver) −1.0 to +40 V

Driver Collector Current IC(driver) 150 mA

Bootstrap Input Current Range (Note 2) IBS −100 to +100 mA

Current Sense Input Voltage Range VIpk (Sense) (VCC−7.0) to (VCC+1.0) V

Feedback and Timing Capacitor Input Voltage Range Vin −1.0 to + 7.0 V

Low Voltage Indicator Output Voltage Range VC(LVI) −1.0 to + 40 V

Low Voltage Indicator Output Sink Current IC(LVI) 10 mA

Thermal Characteristics

P Suffix, Dual−In−Line Case 648C

Thermal Resistance, Junction−to−Air

Thermal Resistance, Junction−to−Case (Pins 4, 5, 12, 13)

DW Suffix, Surface Mount Case 751G

Thermal Resistance, Junction−to−Air

Thermal Resistance, Junction−to−Case (Pins 4, 5, 12, 13)

RqJA

RqJC

RqJA

RqJC

°C/W

Operating Junction Temperature TJ+150 °C

Operating Ambient Temperature (Note 3)

MC34163

MC33163

0 to +70

−40 to + 85

°C

Storage Temperature Range Tstg −65 to +150 °C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1500 V per MIL−STD−883, Method 3015.

Machine Model Method 150 V.

2. Maximum package power dissipation limits must be observed.

3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

ORDERING INFORMATION

Device Package Shipping†

MC33163DW SOIC−16W 47 Units / Rail

MC33163DWG SOIC−16W

(Pb−Free) 47 Units / Rail

MC33163DWR2 SOIC−16W 1000 Units / Reel

MC33163DWR2G SOIC−16W

(Pb−Free) 1000 Units / Reel

MC33163P PDIP−16 25 Units / Rail

MC33163PG PDIP−16

(Pb−Free) 25 Units / Rail

MC34163DW SOIC−16W 47 Units / Rail

MC34163DWG SOIC−16W

(Pb−Free) 47 Units / Rail

MC34163DWR2 SOIC−16W 1000 Units / Reel

MC34163DWR2G SOIC−16W

(Pb−Free) 1000 Units / Reel

MC34163P PDIP−16 25 Units / Rail

MC34163PG PDIP−16

(Pb−Free) 25 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC34163, MC33163

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ELECTRICAL CHARACTERISTICS (VCC = 15 V, Pin 16 = VCC, CT = 620 pF, for typical values TA = 25°C, for min/max values TA is

the operating ambient temperature range that applies (Note 5), unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

OSCILLATOR

Frequency

TA = 25°C

Total Variation over VCC = 2.5 V to 40 V, and Temperature

fOSC

−

kHz

Charge Current Ichg −225 −mA

Discharge Current Idischg −25 −mA

Charge to Discharge Current Ratio Ichg/Idischg 8.0 9.0 10 −

Sawtooth Peak Voltage VOSC(P) −1.25 −V

Sawtooth Valley Voltage VOSC(V) −0.55 −V

FEEDBACK COMPARATOR 1

Threshold Voltage

TA = 25°C

Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C)

Total Variation over Line, and Temperature

Vth(FB1)

4.9

−

4.85

5.05

0.008

−

5.2

0.03

5.25

%/V

Input Bias Current (VFB1 = 5.05 V) IIB(FB1) −100 200 mA

FEEDBACK COMPARATOR 2

Threshold Voltage

TA = 25°C

Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C)

Total Variation over Line, and Temperature

Vth(FB2)

1.225

−

1.213

1.25

0.008

−

1.275

0.03

1.287

%/V

Input Bias Current (VFB2 = 1.25 V) IIB(FB2) −0.4 0 0.4 mA

CURRENT LIMIT COMPARATOR

Threshold Voltage

TA = 25°C

Total Variation over VCC = 2.5 V to 40 V, and Temperature

Vth(Ipk Sense)

−

230

250

−

270

Input Bias Current (VIpk (Sense) = 15 V) IIB(sense) −1.0 20 mA

DRIVER AND OUTPUT SWITCH (Note 4)

Sink Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded)

Non−Darlington Connection (RPin 9 = 110 W to VCC, ISW/IDRV ≈ 20)

Darlington Connection (Pins 9, 10, 11 connected)

VCE(sat)

−

0.6

1.0

1.4

Collector Off−State Leakage Current (VCE = 40 V) IC(off) −0.02 100 mA

Bootstrap Input Current Source (VBS = VCC + 5.0 V) Isource(DRV) 0.5 2.0 4.0 mA

Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) VZVCC + 6.0 VCC + 7.0 VCC + 9.0 V

LOW VOLTAGE INDICATOR

Input Threshold (VFB2 Increasing) Vth 1.07 1.125 1.18 V

Input Hysteresis (VFB2 Decreasing) VH−15 −mV

Output Sink Saturation Voltage (Isink = 2.0 mA) VOL(LVI) −0.15 0.4 V

Output Off−State Leakage Current (VOH = 15 V) IOH −0.01 5.0 mA

TOTAL DEVICE

Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC,

Pins 6, 14, 15 = GND, remaining pins open)

ICC −6.0 10 mA

4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

5. Tlow =0°C for MC34163 Thigh =+70°C for MC34163

=−40°C for MC33163 = + 85°C for MC33163

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, OUTPUT SWITCH ON-OFF TIME ( s)ton-t μ

100

CT, OSCILLATOR TIMING CAPACITOR (nF)

0.1

1.0 1.0 10

off

Figure 2. Output Switch On−Off Time

versus Oscillator Timing Capacitor

Figure 3. Oscillator Frequency Change

versus Temperature

2.0

-55

TA, AMBIENT TEMPERATURE (°C)

fOSC, OSCILLATOR FREQUENCY CHANGE (%)Δ

-2.0

-4.0

-6.0

-25 0 25 50 75 100 125

VCC = 15 V

CT = 620 pF

VCC = 15 V

TA = 25°C

1)ton, RDT = ∞

2)ton, RDT = 20 k

3)ton, toff, RDT = 10 k

4)toff, RDT = 20 k

5)toff, RDT = ∞

Figure 4. Feedback Comparator 1 Input Bias

Current versus Temperature

2.8

2.4

2.0

1.6

1.2

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Isource (DRV), BOOTSTRAP INPUT CURRENT SOURCE (mA)

VCC = 15 V

Pin 16 = VCC + 5.0 V

Figure 5. Feedback Comparator 2 Threshold

Voltage versus Temperature

7.6

7.4

7.2

7.0

6.8

-55 -25 0 25 50 75 100 12

TA, AMBIENT TEMPERATURE (°C)

IZ = 25 mA

, BOOTSTRAP INPUT ZENER CLAMP VOLTAGE (V)

Figure 6. Bootstrap Input Current

Source versus Temperature

Figure 7. Bootstrap Input Zener Clamp

Voltage versus Temperature

IIB, INPUT BIAS CURRENT (A)μ

140

-55

TA, AMBIENT TEMPERATURE (°C)

120

100

60 -25 0 25 50 75 100 125

Vth(FB2), COMPARATOR 2 THRESHOLD VOLTAGE (mV

)

1300

1280

1260

1240

1220

1200

-55

TA, AMBIENT TEMPERATURE (°C)

-25 0 25 50 75 100 125

Vth Typ = 1250 mV

Vth Min = 1225 mV

VCC = 15 V

VFB1 = 5.05 V Vth Max = 1275 mV

VCC = 15 V

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VCE (sat)

-0.4

0 0.8 2.4 3.2

IE, EMITTER CURRENT (A)

, SOURCE SATURATION (V)

-0.8

-1.2

-1.6

-2.0

1.2

1.0

IC, COLLECTOR CURRENT (A)

0.8

0.6

0.4

0.2

0GND

VCE (sat), SINK SATURATION (V)

1.6

Bootstrapped, Pin 16 = VCC + 5.0 V

Non-Bootstrapped, Pin 16 = VCC

VCC

0 0.8 2.4 3.21.6

Figure 8. Output Switch Source Saturation

versus Emitter Current

Figure 9. Output Switch Sink Saturation

versus Collector Current

Darlington, Pins 9, 10, 11 Connected

Grounded Emitter Configuration

Collector Sinking Current From VCC

Pins 7, 8 = VCC = 15 V

Pins 4, 5, 12, 13, 14, 15 = GND

TA = 25°C, (Note 2)

Saturated Switch, RPin9 = 110 W to VCC

Darlington Configuration

Emitter Sourcing Current to GND

Pins 7, 8, 10, 11 = VCC

Pins 4, 5, 12, 13 = GND

TA = 25°C, (Note 2)

Figure 10. Output Switch Negative Emitter

Voltage versus Temperature

Figure 11. Low Voltage Indicator Output Sink

Saturation Voltage versus Sink Current

Figure 12. Current Limit Comparator Threshold

Voltage versus Temperature

Figure 13. Current Limit Comparator Input Bias

Current versus Temperature

Vth (Ipk Sense), THRESHOLD VOLTAGE (mV)

254

252

250

248

246

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

IIB (Sense) INPUT BIAS CURRENT ( A)

1.6

1.4

1.2

1.0

0.8

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

0.6

VE, EMITTER VOLTAGE (V)

-0.4

-0.8

-1.2

-1.6

-2.0

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

IC = 10 mA

VOL (LVI) , OUTPUT SATURATION VOLTAGE (V)

0.5

0.4

0 2.0 4.0 6.0 8.0

Isink, OUTPUT SINK CURRENT (mA)

0.3

0.2

0.1

VCC=5 V

TA=25°C

GND

VCC = 15 V

VIpk (Sense) = 15 V

IC = 10 mA

VCC = 15 V

Pins 7, 8, 9, 10, 16 = VCC

Pins 4, 6 = GND

Pin 14 Driven Negative

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ICC, SUPPLY CURRENT (mA)

Figure 14. Standby Supply Current

versus Supply Voltage

Figure 15. Standby Supply Current

versus Temperature

ICC, SUPPLY CURRENT (mA)

8.0

6.0

4.0

2.0

00 10203040

VCC, SUPPLY VOLTAGE (V)

Pins 7, 8, 16 = VCC

Pins 4, 6, 14 = GND

Remaining Pins Open

TA = 25°C

7.2

6.4

5.6

4.8

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

4.0

VCC = 15 V

Pins 7, 8, 16 = VCC

Pins 4, 6, 14 = GND

Remaining Pins Open

Figure 16. Minimum Operating Supply

Voltage versus Temperature

3.0

2.6

2.2

1.8

1.4

1.0

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

VCC(min), MINIMUM OPERATING SUPPLY VOLTAGE (V)

Pin 16 Open

CT = 620 pF

Pins 7,8 = VCC

Pins 4, 14 = GND

Pin 9 = 1.0 kW to 15 V

Pin 10 = 100 W to 15 V

Figure 17. P Suffix (DIP−16) Thermal Resistance

and Maximum Power Dissipation

versus P.C.B. Copper Length

ÎÎÎ

Graphs represent symmetrical layout

3.0 mm

Printed circuit board heatsink example

100

10 20 30 40 50

L, LENGTH OF COPPER (mm)

PD, MAXIMUM POWER DISSIPATION (W)

5.0

4.0

3.0

2.0

1.0

PD(max) for TA = 70°C

2.0 oz

Copper

ÎÎ

Pin 16 = VCC

RqJA

R , THERMAL RESISTANCE

JAθ

JUNCTION-TO-AIR ( C/W)°

Figure 18. DW Suffix (SOP−16L) Thermal Resistance and

Maximum Power Dissipation versus P.C.B. Copper Length

0.4

0.8

1.2

1.6

2.0

2.4

02030504010

L, LENGTH OF COPPER (mm)

100 2.8

PD(max) for TA = 50°C

RqJA

R , THERMAL RESISTANCE

JAθ

JUNCTION-TO-AIR ( C/W)°

, MAXIMUM POWER DISSIPATION (W)

ÎÎÎ

ÎÎ

2.0 oz.

Copper

Graph represents symmetrical layout

3.0 mmL

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Feedback

Comparator

LVI

Current

Limit

(Bottom View)

0.25 V

Ipk Sense

RSC

VCC

Timing Capacitor

Shutdown

RDT

Voltage Feedback 1

Voltage Feedback 2

LVI Output

1.125 V

15 k1.25 V

45 k

Thermal

Oscillator

Latch

2.0 mA

7.0 V Bootstrap Input

Switch Emitter

GND

Switch Collector

Driver Collector

+Sink Only

Positive True Logic

Figure 19. Representative Block Diagram

GND

Comparator Output

Timing Capacitor CT

Oscillator Output

Output Switch

Output Voltage

Nominal Output

Voltage Level

1.25 V

0.55 V

Off

Figure 20. Typical Operating Waveforms

Startup Quiescent Operation

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INTRODUCTION

The MC34163 series are monolithic power switching

regulators optimized for dc−to−dc converter applications.

The combination of features in this series enables the system

designer to directly implement step−up, step−down, and

voltage−inverting converters with a minimum number of

external components. Potential applications include cost

sensitive consumer products as well as equipment for the

automotive, computer, and industrial markets. A

Representative Block Diagram is shown in Figure 19.

OPERATING DESCRIPTION

The MC34163 operates as a fixed on−time, variable

off−time voltage mode ripple regulator. In general, this

mode of operation is somewhat analogous to a capacitor

charge pump and does not require dominant pole loop

compensation for converter stability. The Typical Operating

Waveforms are shown in Figure 20. The output voltage

waveform shown is for a step−down converter with the

ripple and phasing exaggerated for clarity. During initial

converter startup, the feedback comparator senses that the

output voltage level is below nominal. This causes the

output switch to turn on and off at a frequency and duty cycle

controlled by the oscillator, thus pumping up the output filter

capacitor. When the output voltage level reaches nominal,

the feedback comparator sets the latch, immediately

terminating switch conduction. The feedback comparator

will inhibit the switch until the load current causes the output

voltage to fall below nominal. Under these conditions,

output switch conduction can be inhibited for a partial

oscillator cycle, a partial cycle plus a complete cycle,

multiple cycles, or a partial cycle plus multiple cycles.

Oscillator

The oscillator frequency and on−time of the output switch

are programmed by the value selected for timing capacitor

CT. Capacitor CT is charged and discharged by a 9 to 1 ratio

internal current source and sink, generating a negative going

sawtooth waveform at Pin 6. As CT charges, an internal

pulse is generated at the oscillator output. This pulse is

connected to the NOR gate center input, preventing output

switch conduction, and to the AND gate upper input,

allowing the latch to be reset if the comparator output is low.

Thus, the output switch is always disabled during ramp−up

and can be enabled by the comparator output only at the start

of ramp−down. The oscillator peak and valley thresholds are

1.25 V and 0.55 V, respectively, with a charge current of

225 mA and a discharge current of 25 mA, yielding a

maximum on−time duty cycle of 90%. A reduction of the

maximum duty cycle may be required for specific converter

configurations. This can be accomplished with the addition

of an external deadtime resistor (RDT) placed across CT. The

resistor increases the discharge current which reduces the

on−time of the output switch. A graph of the Output Switch

On−Off Time versus Oscillator Timing Capacitance for

various values of RDT is shown in Figure 2. Note that the

maximum output duty cycle, ton/ton + toff, remains constant

for values of CT greater than 0.2 nF. The converter output

can be inhibited by clamping CT to ground with an external

NPN small−signal transistor.

Feedback and Low Voltage Indicator Comparators

Output voltage control is established by the Feedback

comparator. The inverting input is internally biased at 1.25 V

and is not pinned out. The converter output voltage is

typically divided down with two external resistors and

monitored by the high impedance noninverting input at Pin 2.

The maximum input bias current is ±0.4 mA, which can cause

an output voltage error that is equal to the product of the input

bias current and the upper divider resistance value. For

applications that require 5.0 V, the converter output can be

directly connected to the noninverting input at Pin 3. The high

impedance input, Pin 2, must be grounded to prevent noise

pickup. The internal resistor divider is set for a nominal

voltage of 5.05 V. The additional 50 mV compensates for a

1.0% voltage drop in the cable and connector from the

converter output to the load. The Feedback comparator’s

output state is controlled by the highest voltage applied to

either of the two noninverting inputs.

The Low Voltage Indicator (LVI) comparator is designed

for use as a reset controller in microprocessor−based

systems. The inverting input is internally biased at 1.125 V,

which sets the noninverting input thresholds to 90% of

nominal. The LVI comparator has 15 mV of hysteresis to

prevent erratic reset operation. The Open Collector output is

capable of sinking in excess of 6.0 mA (see Figure 11). An

external resistor (RLVI) and capacitor (CDLY) can be used to

program a reset delay time (tDLY) by the formula shown

below, where Vth(MPU) is the microprocessor reset input

threshold. Refer to Figure 21.

Ǔǒ

tDLY = RLVI CDLY In

1 −Vth(MPU)

Vout

Current Limit Comparator, Latch and Thermal

Shutdown

With a voltage mode ripple converter operating under

normal conditions, output switch conduction is initiated by

the oscillator and terminated by the Voltage Feedback

comparator. Abnormal operating conditions occur when the

converter output is overloaded or when feedback voltage

sensing is lost. Under these conditions, the Current Limit

comparator will protect the Output Switch.

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The switch current is converted to a voltage by inserting

a fractional ohm resistor, RSC, in series with VCC and output

switch transistor Q2. The voltage drop across RSC is

monitored by the Current Sense comparator. If the voltage

drop exceeds 250 mV with respect to VCC, the comparator

will set the latch and terminate output switch conduction on

a cycle−by−cycle basis. This Comparator/Latch

configuration ensures that the Output Switch has only a

single on−time during a given oscillator cycle. The

calculation for a value of RSC is:

RSC +0.25 V

Ipk (Switch)

Figures 12 and 13 show that the Current Sense comparator

threshold is tightly controlled over temperature and has a

typical input bias current of 1.0 mA. The propagation delay

from the comparator input to the Output Switch is typically

200 ns. The parasitic inductance associated with RSC and the

circuit layout should be minimized. This will prevent

unwanted voltage spikes that may falsely trip the Current

Limit comparator.

Internal thermal shutdown circuitry is provided to protect

the IC in the event that the maximum junction temperature

is exceeded. When activated, typically at 170°C, the Latch

is forced into the “Set” state, disabling the Output Switch.

This feature is provided to prevent catastrophic failures from

accidental device overheating. It is not intended to be used

as a replacement for proper heatsinking.

Driver and Output Switch

To aid in system design flexibility and conversion

efficiency, the driver current source and collector, and

output switch collector and emitter are pinned out

separately. This allows the designer the option of driving the

output switch into saturation with a selected force gain or

driving it near saturation when connected as a Darlington.

The output switch has a typical current gain of 70 at 2.5 A

and is designed to switch a maximum of 40 V collector to

emitter, with up to 3.4 A peak collector current. The

minimum value for RSC is:

RSC(min) +0.25 V

3.4 A +0.0735 W

When configured for step−down or voltage−inverting

applications, as in Figures 21 and 25, the inductor will

forward bias the output rectifier when the switch turns off.

Rectifiers with a high forward voltage drop or long turn−on

delay time should not be used. If the emitter is allowed to go

sufficiently negative, collector current will flow, causing

additional device heating and reduced conversion

efficiency.

Figure 10 shows that by clamping the emitter to 0.5 V, the

collector current will be in the range 10 mA over

temperature. A 1N5822 or equivalent Schottky barrier

rectifier is recommended to fulfill these requirements.

A bootstrap input is provided to reduce the output switch

saturation voltage in step−down and voltage−inverting

converter applications. This input is connected through a

series resistor and capacitor to the switch emitter and is used

to raise the internal 2.0 mA bias current source above VCC.

An internal zener limits the bootstrap input voltage to VCC

+7.0 V. The capacitor’s equivalent series resistance must

limit the zener current to less than 100 mA. An additional

series resistor may be required when using tantalum or other

low ESR capacitors. The equation below is used to calculate

a minimum value bootstrap capacitor based on a minimum

zener voltage and an upper limit current source.

CB(min) +IDt

DV+4.0 mA ton

4.0 V +0.001 ton

Parametric operation of the MC34163 is guaranteed over

a supply voltage range of 2.5 V to 40 V. When operating

below 3.0 V, the Bootstrap Input should be connected to

VCC. Figure 16 shows that functional operation down to

1.7 V at room temperature is possible.

Package

The MC34163 is contained in a heatsinkable 16−lead

plastic dual−in−line package in which the die is mounted on

a special heat tab copper alloy lead frame. This tab consists

of the four center ground pins that are specifically designed

to improve thermal conduction from the die to the circuit

board. Figures 17 and 18 show a simple and effective

method of utilizing the printed circuit board medium as a

heat dissipater by soldering these pins to an adequate area of

copper foil. This permits the use of standard layout and

mounting practices while having the ability to halve the

junction−to−air thermal resistance. These examples are for

a symmetrical layout on a single−sided board with two

ounce per square foot of copper.

APPLICATIONS

The following converter applications show the simplicity

and flexibility of this circuit architecture. Three main

converter topologies are demonstrated with actual test data

shown below each of the circuit diagrams.

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RBL

2200

1N5822

LVI

Current

Limit

(Bottom View)

-16

0.25 V

RSC

0.075

Vin

12 V

680 pF

1.125 V

15 k1.25 V

45 k

Feedback

Comparator

Cin

330

Coilcraft LO451-A

0.02

Vout

5.05 V/3.0 A

Low Voltage

Indicator Output CDLY

RLVI

10 k

Thermal

Oscillator

Latch

2.0 mA

7.0 V

180 mH

Test Condition Results

Line Regulation Vin = 8.0 V to 24 V, IO = 3.0 A 6.0 mV = ±0.06%

Load Regulation Vin = 12 V, IO = 0.6 A to 3.0 A 2.0 mV = ±0.02%

Output Ripple Vin = 12 V, IO = 3.0 A 36 mVpp

Short Circuit Current Vin = 12 V, RL = 0.1 W3.3 A

Efficiency, Without Bootstrap Vin = 12 V, IO = 3.0 A 76.7%

Efficiency, With Bootstrap Vin = 12 V, IO = 3.0 A 81.2%

Figure 21. Step−Down Converter

Figure 22. External Current Boost Connections for I

(

Switch

)

Greater Than 3.4 A

Figure 22A. External NPN Switch Figure 22B. External PNP Saturated Switch

(Bottom View)

MC34163, MC33163

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180 mH

Coilcraft

LO451-A

LVI

Current

Limit

(Bottom View)

-16

0.25 V

RSC

0.075

Vin

12 V

680 pF

1.125 V

15 k1.25 V

45 k

Feedback

Comparator

Cin

330

Vout

28 V/600 mA

1N5822

47 k

2.2 k

Thermal

Oscillator

Latch

2.0 mA

7.0 V

RLVI

1.0 k

Low Voltage

Indicator

Output

Test Condition Results

Line Regulation Vin = 9.0 V to 16 V, IO = 0.6 A 30 mV = ±0.05%

Load Regulation Vin = 12 V, IO = 0.1 A to 0.6 A 50 mV = ±0.09%

Output Ripple Vin = 12 V, IO = 0.6 A 140 mVpp

Efficiency Vin = 12 V, IO = 0.6 A 88.1%

Figure 23. Step−Up Converter

Figure 24. External Current Boost Connections for I

(

Switch

)

Greater Than 3.4 A

Figure 24A. External NPN Switch Figure 24B. External NPN Saturated Switch

(Bottom View)

MC34163, MC33163

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180 mH

LVI

Current

Limit

(Bottom View)

-16

0.25 V

RSC

0.075

Vin

12 V

470 pF

1.125 V

15 k1.25 V

45 k

Feedback

Comparator

Cin

330

Vout

-12 V/1.0 A

Coilcraft LO451-A

1N5822

953

8.2 k

0.02

Thermal

Oscillator

Latch

2.0 mA

7.0 V

2200

Test Condition Results

Line Regulation Vin = 9.0 V to 16 V, IO = 1.0 A 5.0 mV = ±0.02%

Load Regulation Vin = 12 V, IO = 0.6 A to 1.0 A 2.0 mV = ±0.01%

Output Ripple Vin = 12 V, IO = 1.0 A 130 mVpp

Short Circuit Current Vin = 12 V, RL = 0.1 W3.2 A

Efficiency, Without Bootstrap Vin = 12 V, IO = 1.0 A 73.1%

Efficiency, With Bootstrap Vin = 12 V, IO = 1.0 A 77.5%

Figure 25. Voltage−Inverting Converter

Figure 26. External Current Boost Connections for I

(

Switch

)

Greater Than 3.4 A

Figure 26A. External NPN Switch Figure 26B. External PNP Saturated Switch

(Bottom View)

15 Q3

(Bottom View)

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Figure 27. Printed Circuit Board and Component Layout

(Circuits of Figures 21, 23, 25)

All printed circuit boards are 2.58” in width by 1.9” in height.

Cin

RLVI

Vin

RSC

+- +

MC34163 Step−Down

Bottom View Top View

Cin

RLVI

Vin

RSC

+-+

MC34163 Step−Up

Cin

Vin

RSC

+-+

MC34163 Voltage−Inverting

MC34163, MC33163

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Calculation Step−Down Step−Up Voltage−Inverting

ton

toff

(Notes 1, 2, 3)

Vout )VF

Vin *Vsat *Vout

Vout )VFVin

Vin Vsat

|Vout|)VF

Vin *Vsat

ton

toff

ǒton

toff )1Ǔƒ

ton

toff

ǒton

toff )1Ǔƒ

ton

toff

ǒton

toff )1Ǔ

CTƒ

32.143 · 106

IL(avg) Iout Iout ǒton

toff )1ǓIout ǒton

toff )1Ǔ

Ipk (Switch) IL(avg) )

DIL

2IL(avg) )

DIL

2IL(avg) )

DIL

RSC 0.25

Ipk (Switch)

0.25

Ipk (Switch)

0.25

Ipk (Switch)

LǒVin *Vsat *Vout

DILǓton ǒVin *Vsat

DILǓton

Vripple(pp) DILǒ1

OǓ2

)(ESR)2

ƒ[

ton Iout

CO[

ton Iout

Vout Vref ǒR2

R1)1ǓVref ǒR2

R1)1Ǔ

Vin −

Vout −

Iout −

DIL −

p −

Vripple(pp) −

Nominal operating input voltage.

Desired output voltage.

Desired output current.

Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less

than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit

threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will

proportionally reduce converter output current capability.

Maximum output switch frequency.

Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value

since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)

electrolytic designed for switching regulator applications.

The following Converter Characteristics must be chosen:

NOTES: 1. Vsat − Saturation voltage of the output switch, refer to Figures 8 and 9.

NOTES: 2. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V.

NOTES: 3. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum

NOTES: 3. operating input voltage.

Figure 28. Design Equations

MC34163, MC33163

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PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

CASE 648C−04

ISSUE D

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.744 0.783 18.90 19.90

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

E0.050 BSC 1.27 BSC

F0.040 0.70 1.02 1.78

G0.100 BSC 2.54 BSC

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.040 0.39 1.01

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

16 9

16X

0.005 (0.13) T

SEATING

PLANE

0.005 (0.13) T

16X

MC34163, MC33163

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PACKAGE DIMENSIONS

SOIC−16W

DW SUFFIX

CASE 751G−03

ISSUE C

14X

B16X

SEATING

PLANE

0.25 B S

16 9

hX 45_

0.25

H8X

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE B DIMENSION AT MAXIMUM

MATERIAL CONDITION.

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D10.15 10.45

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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MC34163/D

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