1Rev.1.1
K
■ DESCRIPTION
The SRM2AV400LLBT8 is a 524,288words x 8-bit asynchronous, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. The asynchronous and static nature of the memory requires no external clock and no
refreshing circuit. 3-state output allows easy expansion of memory capacity. The temperature range of the
SRM2AV400LLBT8 is from –40 to 85°C, and it is suitable for the industrial products.
■ FEATURES
● Fast Access time........................ 85ns (2.4V)
● Low supply current ..................... LL Version
● Completely static........................ No clock required
● Supply voltage............................ 2.4V to 3.3V
● 3-state output with wired-OR capability
● Non-volatile storage with back-up batteries
● Package ..................................... SRM2AV400LLBT TFBGA-48 pin (Tape CSP)
4M-bit Static RAM
PF1066-02
SRM2AV400LLBT
8
■ BLOCK DIAGRAM
●Super Low Voltage Operation and Low Current Consumption
●Access Time 85ns (2.4V)
●524,288 Words x 8-bit Asynchronous
●Wide Temperature Range
Super Low Voltage
Operation
Products
I/O Buffer
8
I/O1 I/O8
CS1
OE
WE
OE , WE
Control
Logic
CS1,CS2
Control
Logic
11
8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Address Buffer
Memory Cell Array
2048 x 256 x 8
Column Gate
2048
256
256 x 8
X DecoderY Decoder
CS2
SRM2AV400LLBT
8
Rev.1.12
■ PIN CONFIGURATION
■ PIN DESCRIPTION
A0 to A18
WE
OE
CS1
CS2
I/O1 to 8
VDD
VSS
NC
Address Input
Write Enable
Output Enable
Chip Select1
Chip Select2
Data I/O
Power Supply (2.4V to 3.3V)
Power Supply (0V)
No connection
A
B
C
D
E
F
G
H
213456
NC
A7
A14
A16
VDD
A17
A13
NC
NC
A6
A12
A18
A15
WE
A8
NC
NC
A4
A5
VDD
CS2
A9
A11
NC
NC
A3
A2
NC
GND
A10
OE
NC
NC
A1
I/O1
I/O3
I/O5
I/O7
CS1
NC
NC
A0
I/O2
GND
I/O4
I/O6
I/O8
NC
TFBGA-48 pin
Top view (Looking through part)
SRM2AV400LLBT
SRM2AV400LLBT
8
Rev.1.1 3
K
■ ABSOLUTE MAXIMUM RATINGS
■ DC RECOMMENDED OPERATING CONDITIONS
● Terminal Capacitance
■ ELECTRICAL CHARACTERISTICS
● DC Electrical Characteristics
Supply voltage
Input voltage
Input/Output voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
Parameter VDD
VI
VI/O
PD
T
opr
T
stg
T
sol
Symbol Ratings Unit
– 0.5 to 4.0
– 0.5
*
to VDD + 0.3
– 0.5
*
to VDD + 0.3
0.5
– 40 to 85
– 65 to 150
260°C, 10s (at lead)
(VSS=0V)
*
VI,VI/O (Min.) = –2.0V (when pulse width is less than 50ns)
V
V
V
W
°C
°C
–
(Ta = –40 to 85 °C)
Parameter
Supply voltage
Input voltege
Symbol
VDD
VSS
VIH
VIL
V
V
V
V
*
if pulse width is less than 50ns it is – 2.0V
Min.
2.4
0.0
0.75VDD
– 0.3
*
Typ.
3.0
0.0
–
–
Max.
3.3
0.0
VDD+0.3
0.3
Min.
2.7
0.0
2.0
– 0.3
*
Typ.
3.0
0.0
–
–
Max.
3.3
0.0
VDD+0.3
0.6
Unit
Parameter Symbol Conditions Unit
Input leakage current
Standby supply current
Average operating current
Operating Supply Current
High level output voltage
ILI
ILO
VOH IOH
Low level output voltage VOL
IDDS
IDDS1
IDDA
IDDA1
IDDO
IOL
µA
(V
SS
=0V, Ta = –40 to 85 °C)
V
DD
= 2.4 to 3.3V
V
DD
= 2.4 to 3.3V V
DD
= 2.7 to 3.3V
V
I
= 0 to V
DD
CS1 = V
IH
or CS2 = V
IL or
WE=V
IL
or OE = V
IH
, V
I/O
= 0 to V
DD
CS1 = V
IH or
CS2= V
IL
Output leakage current
–1.0
Min. Typ.
*1
Max.
– 1.0
µA–1.0 – 1.0
mA
–
–
–
1.0
15
1.0 µA
mA
–25 35
mA
–4.0 6.0
mA
– 4.0 6.0
V
V
2.0
V
DD
–0.2
–
–
–
–
–
–
–
–
0.4
0.2
*1 : Typical values are measured at Ta = 25°C and V
DD
= 3.0V
(Ta = 25°C, f = 1MHz)
Parameter Symbol Unit
Conditions
Address Capacitance
Input Capacitance
I/O Capacitance
CADD
CI
CI/O
VADD = 0V
VI = 0V
VI/O = 0V
Max.Min. Typ.
Note : This parameter is made by the inspection data of sample, not of all products
V
I
= V
IL
or V
IH
I
I/O
= 0mA, t
cyc
= Min.
V
I
= V
IL
or V
IH
I
I/O
= 0mA, t
cyc
= 1µs
V
I
= V
IL
or V
IH
I
I/O
= 0mA
–
–
–
–
–
–
8
8
10
pF
pF
pF
–0.5mA
–100µA
1.0mA
100µA
–
–
0.5
Ta ≤ 25°C, VDD ≤ 3.0V
CS1 = CS2 ≥ VDD – 0.2V
or CS2 ≤ 0.2V
SRM2AV400LLBT
8
Rev.1.14
1TTL
I/O C
L
*1 Test Conditions
1. Input pulse level : 0.3V to 0.8VDD (2.4Vto 3.3V)
2. tr = tf = 5ns
3. Input and output timing reference levels :1/2VDD (2.4V to 3.3V)
4. Output load : CL =50pF (Includes Jig Capacitance)
*2 Test Conditions
1. Input pulse level : 0.3V to 0.8VDD (2.4V to 3.3V)
2. tr = tf = 5ns
3. Input timing reference levels :1/2VDD (2.4V to 3.3V)
4. Output timing reference levels : ±200mV (The level changed from stable
output voltage level)
5. Output load :CL = 5pF (Includes Jig Capacitance)
❍ Write Cycle
● AC Electrical Characteristics
❍ Read Cycle
1TTL
I/O C
L
Unit
SRM2AV400LLBT8
2.4 to 3.0V
Min. Max.
85
–
–
–
–
5
5
–
–
0
–
5
–
85
85
85
45
–
–
30
30
–
30
–
Parameter Symbol Test
Conditions
(VSS = 0V, Ta = –40 to 85°C)
Read cycle time
Address access time
CS1 access time
CS2 access time
OE access time
CS1 output set time
CS2 output set time
CS1 output floating
CS2 output floating
OE output set time
OE output floating
Output hold time
t
RC
t
ACC
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
OLZ
t
OHZ
t
OH
1
1
1
1
1
2
2
2
2
2
2
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
SRM2AV400LLBT
8
2.4 to 3.3V
Min. Max.
85
70
70
70
0
60
0
35
0
–
5
–
–
–
–
–
–
–
–
–
35
–
Parameter Symbol Test
Conditions
Write cycle time
Chip select time (CS1)
Chip select time (CS2)
Address enable time
Address setup time
Write pulse width
Address hold time
Data setup time
Data hold time
WE output floating
WE output set time
(V
SS
= 0V, Ta = –40 to 85°C)
tWC
tCW1
tCW2
tAW
tAS
tWP
tWR
tDW
tDH
tWHZ
tOW
1
1
1
1
1
1
1
1
1
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRM2AV400LLBT
8
Rev.1.1 5
K
● DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
● Timing Chart
Parameter Symbol Conditions Min. Typ.* Max. Unit
Data retention supply voltage
Data retention curren
Data hold time
Operation recovery time
V
DDR
I
DDR
tCDR
tR
V
µA
ns
ms
(V
SS
= 0V, Ta = –40 to 85°C)
V
DDR
= 2.5V
CS1 = CS2≥ V
DD
– 0.2V or CS2 ≤0.2V
* : Reference data at Ta=25°C
1.2
–
0
5
–
0.4
––
–
–
3.3
13
t
CHZ2
CS1
Read Cycle
*1
A0 to 18
OE
I/O1 to 8
(Dout)
t
RC
t
ACC
t
OE
t
OHZ
t
OLZ
Write Cycle 1 (CS1 Control)
*2, *3
t
AW
t
DW
t
WR
t
DH
Write Cycle 3 (WE Control)
*3
A0 to 18
CS1
WE
I/O1 to 8
(Dout)
(Din)
t
OH
High-Z
t
CHZ1
t
CLZ1
CS2 CS2
t
WC
t
CW1
t
WP
t
DW
t
WR
t
AS
t
WHZ
t
OW
t
DH
A0 to 18
CS1
WE
I/O1 to 8
(Dout)
(Din)
t
CW2
Write Cycle 2 (CS2 Control)
*2, *3
t
WC
t
AW
t
DW
t
WR
t
AS
t
DH
A0 to 18
CS1
WE
I/O1 to 8
(Dout)
(Din)
High-Z
CS2 CS2
t
CW2
t
WP
t
CW1
t
AS
t
WC
t
ACS1
t
WP
t
ACS2
t
CLZ2
t
CW2
t
CW1
Note : *1 During read cycle time, WE is to be "High" level.
*2 In write cycle time that is controlled by CS1 or CS2, output buffer is to be "Hi-Z" state even if OE is "Low" level.
*3 When output buffer is in output state, be careful that do not input the opposite signals to the output data.
SRM2AV400LLBT
8
Rev.1.16
● Reading data
(1) Reading data from byte
Data is able to be read when the address is set while holding CS1 = "Low",CS2= "High", OE ="Low",
and WE = "High".
Since I/O pins are in "Hi-Z" state when OE = "High", the data bus line can be used for any other objective, then
access time is apparently able to be cut down.
● Writing data
(1)Writing data into byte
There are the following three ways of writing data into the memory.
i) Hold CS2 = "High", WE = "Low", set address and give "Low" pulse to CS1.
ii) Hold CS1 = "Low", WE = "Low", set address and give "High" pulse to CS2.
iii) Hold CS1 = "Low", CS2 = "High", set address and give "Low" pulse to WE.
Anyway, data on I/Opins are latched up into the memory cell during CS1 = "Low" , CS2 ="High" , and WE = "Low".
As DATA I/O pins are in "Hi-Z" when CS1= "High", CS2 = "Low", or OE= "High", the contention on the data bus
can be avoided. But while I/O pins are in the output state, the data that is opposite to the output data should not
be given.
● Standby mode
When CS1 is "High" or CS2 is "Low" the chip is in the standby mode (only retaining data operation). In this case
data I/O pins are Hi-Z, and all inputs of addresses, WE, OE, and data are inhibited. When
CS1 = CS2 ≥ VDD - 0.2V or CS2 ≤ 0.2V, there is almost no current flow except through the high resistance parts
of the memory.
● Data retention at low voltage
In case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage.
But it is impossible to write or read in this mode.
■ FUNCTIONS
● Truth Table
CS1 OE X
X
H
L
H
WE I/O1 to 8 I
DD
MODE
High-Z
High-Z
High-Z
Data In
Data Out
X : High or Low
CS2
X
L
H
H
H
H
X
L
L
L
X
X
H
X
L
Not Selected
Not Selected
Output disable
Byte Write
Byte Read
I
DDS,
I
DDS1
I
DDS,
I
DDS1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
Data retention timing (CS2 Control)
V
DD
CS2
tCDR tR
V
DDR
≥ 1.2V
CS2 ≤ 0.2V
2.2V2.2V
Data hold time
0.3 0.3
VIH VIH
Data retention timing (CS1 Control)
VDD
CS1
t
CDR
t
R
VDDR ≥ 1.2V
CS1 ≥VDD – 0.2V
2.2V2.2V
Data hold time
VIL VIL
0.8xVDD 0.8xVDD
SRM2AV400LLBT
8
Rev.1.1 7
K
TFBGA-48 pin
Unit : mm
■ PACKAGE DIMENSIONS
123 456
H
G
F
E
D
C
B
A
654321
A
B
C
D
E
F
G
H
BO TT OM VIEW
SIDE VIEW
T OP VIEW
SRAM Die
Base Tape
INDEX
0.75 Typ.
1.0 Max.
0.75 Typ.
8.0 ± 0.2
0.2
10.0 ± 0.2
φ0.35±0.05
+0.1
–0.05
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of
any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual
property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 2000 All right reserved.
Rev.1.1
Revised January,2000
Printed in Japan T
SRM2AV400LLBT
8
