AD7579/AD7580 SPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group | Group | Group Test Symbol | Device | T.-Taax | 1 2,3 4 Test Condition Unite Resolution RES ~1,2, | 10 Minimum Resolution for Which Bits No Missing Codes Are Guaranteed Integral Nonlinearity INL -1,2 I ! 1 +LSB max Differential Nonlinearity DNL -1,2 0.9 0.9 0.9 +LSB max Full-Scale Error FSE -1,2 5 5 5 +LSB max Zero Code Error ZCE -1,2 2 2 2 Figure 6 +LSB max Power Supply Rejection PSR -1,2 0.5 +LSB max Zero Code Error ZCE ~1,2 3 3 3 Figure 7 or Figure 8 +LSB max Conversion Time tconv -1,2 16.9 16.9 16.9 ps min 18.5 18.5 18.5 ps3 max Clock Range -1,2 | 250 kHz min 2.5 MHz max Signal-to-Noise Ratio SNR -1,2 55 55 55 dB min Total Harmonic Distortion THD -1,2 -58 58 58 dB max Attenuator Input Resistance -1,2 5 5 5 kfO min 15 15 15 kf max Comparator Input Resistance -1,2 | 10 10 10 Figure 6 MOQ min Reference Input Current rer -1,2 1.5 1.5 1.5 mA max Digital Input Low Voitage Vin -1,2 | 0.8 0.8 0.8 Vox Digital Input High Voltage Vin -1,2 | 24 2.4 24 V min Input Current ln -1,2 | 10 10 10 Vin = 0 Vor Vpp +A max Input Capacitance Cn -1,2 10 pF max Digital Output Low Voltage Vor -1,2 | 04 0.4 0.4 Isnx = 1.6 mA V max Digital Output High Voltage Vou -1,2 | 4.0 4.0 4.0 Isource = 400 pA V min Floating State Leakage Current lour -1,2 | 10 10 10 Vour = 010 Vop +pA max Floating State Output Capacitance | Copy -1,2 10 pF max Supply Current from Vpp Ipp ~1,2 10 10 10 mA max NOTE Wop = +5 V + 5%, Veer = +2.5 V, AGND = DGND = 0V, fo, = 2.5 MHz. 6-102 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7579/AD7580 4.2.1 Life Test Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). 2 9 be} 1.6k Y 14 AA i | I Io 13k> 1 | : ad 47, 1/2W | 3k coy 2a} WA 1 Ly 23 NC {3] 22|NC { 1 I ot 4 21] NC I Pe ! 1 | LE} = ap7s79 = ESINS {e] Ad7580 19] NC | | Lr] wet | 7 lot to Sea 18 TNC I 1! 4.7k . \ |} 4m _{a 77] we fs 16] NC ! \ 4.7k I | 10 15 | NC , t 4.7k 47k | WW | " 14 f We a ' 12 [13 4.7k ALL RESISTORS ARE 1/4W TYPE 9 8 WITH +5% TOLERANCE UNLESS o g sa Ig NOTED OTHERWISE. 6 CIRCUIT CONFIGURATION FOR 3 B.|. MODES 238 1. STATIC BLL. > 2. STATIC B.I. WITH INITIALIZATION 3. DYNAMIC BI. AD7579/AD7580 signals applied to Vcc, CLK WR, AO/RDY. 1. Static Burn-In SEQ Voc | CLK WR AO/RDY Power-Up v ov ov OV Burn-In 5V |0V 5V O0vV 2. Static Burn-In with Initialization SEQ Voc | CLK WR A0/RDY Power-Up 5V [0V OV OV Start Conversions | 5 V | SQR-Wave OV OV FREQ = 20 kHz Min of 16 Vio =0V CLK-Periods Vu = Vec 5.V | SQR-Wave Vec 0V Convert 5 V_ | SQR-Wave Vec OV Min of 64 CLK Periods Burn-In 5V {OV Vec OV 6-106 ANALOG-TO-DIGITAL CONVERTERS REV. A,AD7579/AD7580 differential input to the other ends. This is shown in Figure 7. The span is 5 V and the common mode range is 0 to +10 V. In Figure 8, one end of each attenuator is tied t0 Vag (2.5 V), and this allows each of the other legs to go to 2.5 V without causing the comparator input to go negative. Assuming Vrer is 2.5 V, the span of this circuit is 5 V and the common mode range is 2.5 V to +7.5 V. Note that reducing Vpp below 5 volts causes a corresponding reduction in CMR. See Specifications page for full details. 6.1 Single-Ended Applications. In many cases, users of the AD7579/AD7580 will want to measure single-ended input voltages (i.e., ground referred signals). The circuits of Figures 6, 7 and 8 can be easily adapted to accept such signals. If Vin() in Figure 6 is tied to AGND, then the analog input range is 0 V to +2.5 V. By connecting Vin() of Figure 7 to AGND, the analog input range becomes 0 V to +5 V. Figure 8 can be modified as in Figure 9 to accept input voltages in the range 2.5 V to +2.5 V. Each of these circuits are special cases of the differential input circuits and are achieved by making the negative input to the internal com- parator equal to AGND. 6-108 ANALOG-TO-DIGITAL CONVERTERS REV. A