Pentium II Processor at 350 MHz, 400 MHz, and 450 MHz twa iS) 38 Table 22. BCLK Signal Quality Guidelines for Kdge Finger Measurement i T# Parameter Min Nom Max Unit Figure Notes V1: BCLK VIL 0.5 Vv 14 V2: BCLK VI 2.0 Vv 14 V3: VIN Absolute Voltage Range 0,5 3,3 Vv 14 2 V4: Rising Edge Ringback 2.0 Vv 14 3 V5: Falling Edge Ringback 0.5 Vv 14 3 V6": Tline Ledge Voltage 1,0 1,7 Vv 14 At Ledge Midpoint + V7": Tline Ledge Oscillation 0.2 Vv 14 Peak-to-Peak > NOTES: 1, Unless otherwise noted, all specifications in this table apply to all Pentium I processor frequencies and cache sizes. 2. This is the Pentium II processor system bus clock overshoot and undershoot measurement guideline. 3, The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal may dip back to after passing the Vim (rising) or Vir (falling) voltage limits. This guideline is an absolute value. 4, The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The midpoint voltage level of this ledge should be within the range of the guideline. 5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline. Figure 14. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers I T3 > V3 . ve A o oD as = V7 oO % > V6 % vi , V5 / V3 i 16 ye 14 _1@- T5 > Time 000808 Guidelines AGTL+ Signal Quality Specifications and Measurement Many scenarios have been simulated to generate a set of GTL+ layout guidelines which are available in AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset (Order Number 243735). Refer to the Pentium IT Processor Developer's Manual (Order Number 243502) for the GTL+ buffer specification. Datasheeta Pentium I Processor at 350 MHz, 400 MHz, and 450 MHz | ntl 8 Figure 15. Low to High AGTL+ Receiver Ringback Tolerance ly + __ > [nan | VREE +0.2 f aeeennmeee | VREF t * f Vrer 0.2 | Vstart Time - Note: High to Low case is analogous. 00091 4a 3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in Figure 16 for the non- AGTL+ signal group. Figure 16. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback * Settling Limi Overshoot | \ - imit Vu = Voc ae \ a Rising-Edge Ringback Falling-Edge Ringback Settling Limit Vo & A ' | SS ss Time > Undershoot -_ 000767b 40 Datasheet| Pentium I Processor at 350 MHz, 400 MHz, and 450 MHz | ntl 8 4.0 Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10% of the total signal swing (Vu1-Vio) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be done either with or without the input protection diodes present. Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. Thermal Specifications and Design Considerations Initial Pentium II processors take advatange of S.E.C.C. package technology. This technology uses an extended thermal plate for heatsink attachment. The extended thermal plate interface is intended to provide accessiblity for multiple types of thermal solutions. Follow-on releases of the Pentium II processor use S.E.C.C.2 packaging technology. This pakaging technology doesnt incorporate an extended thermal plate. Processors which use S.E.C.C.2 packaging technology have either a PLGA or an OLGA processor core that is surface mounted onto the substrate. All three of these package variations require unique thermal measuring processes. This chapter provides needed data for designing a thermal solution. However, for the correct thermal measuring processes please refer to AP-586, Pentium I] Processor Thermal Design Guidelines (Order Number 243331). Figure 17 provides a side view of an S.E.C.C. package. This figure provides the thermal plate location. Figure 17. Pentium U Processor S.E.C.C. - Side View Left Latch Right Latch -. \ Extended Thermal Plate Datasheet| Nn 5 Pentium II Processor at 350 MHz, 400 MHz, and 450 MHz 4.1 Thermal Specifications Table 27 and Table 28 provide the thermal design power dissipation and maximum and minimum temperatures for Pentium II processors with S.E.C.C. and S.E.C.C.2 package technologies, respectively. While the processor core dissipates the majority of the thermal power, thermal power dissipated by the L2 cache also impacts the overall processor power specification. Systems should design for the highest possible thermal power, even if a processor with a lower thermal dissipation is planned. Table 27. Thermal Specifications for S.E.C.C. Packaged Processors I Extended Processor Core L2 Cache Processor | Thermal Plate Min Max Min Max Frequency Size Power Power? TPLATE TPLATE TCOVER TCOVER (MHz) (Kbytes) (Ww) (Ww) (CC) (C) ec} (CC) 4504 512 27.1 26.4 5 70 5 75 4004 512 24,3 23.6 5 75 5 75 3504 512 21,5 20.8 5 75 5 75 NOTES: 1, These values are specified at nominal Veccor: for the processor core and nominal Vcci2 for the L2 cache. 2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL + bus termination. The maximum power for each of these components does not occur simultaneously. 3, Extended Thermal Plate power is the processor power that is dissipated through the extended thermal plate. 4, These processors use the extended thermal plate for the Pentium II processor (see Figure 17), Table 28. Thermal Specifications for S.E.C.C.2 Packaged Processors! Processor Min Max Min Max Core L2 Cache | Processor PLGA PLGA OLGA | OLGA | L2Cache | L2 Cache Min Max Frequency Size Power Tcase Tease Tyoxe Tyonc | Min Tcase | Max Tease | Teover Tecover (MHz) (Kbytes) CW) ec) CC) CC} CC) (C) ec) CC) CC) 450 512 27,1 N/A N/A 5 90 5 105 5 75 400 512 24,3 N/A N/A 5 90 5 105 5 75 350 512 21,5 5 80 N/A N/A 5 105 5 75 NOTES: 1, These values are specified at nominal Veccog: for the processor core and nominal Vcci2 for the L2 cache. 2, Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL + bus termination. The maximum power for each of these components does not occur simultaneously. For S.E.C.C. packaged processors, the extended thermal plate is the attach location for all thermal solutions. The maximum and minimum extended thermal plate temperatures are specified in Table 27, For S.E.C.C.2 packaged processors, thermal solutions attach to the processor by connecting through the substrate to the cover. The maximum and minimum temperatures of the pertinent locations are specified in Table 28. A thermal solution should be designed to ensure the temperature of the specified locations never exceeds these temperatures. The total processor power is a result of heat dissipation that is a combination of heat from both the processor core and L2 cache. The overall system chassis thermal design must comprehend the entire processor power. In S.E.C.C. packaged processors, the extended thermal plate power is a component of this power, and is composed of a combination of the processor core and the L2 cache dissipating heat through the extended thermal plate. The heatsink need only be designed to dissipate the extended thermal plate power. See Table 27 for current Pentium II processor thermal design specifications. Datasheet 43Pentium II Processor at 350 MHz, 400 MHz, and 450 MHz 4.1.1 Table 29. Table 30. 5.0 intel. For S.E.C.C.2 packaged processors, no extended thermal plate exists and thermal solutions need to contact the core package directly and attach through the substrate to the cover. The total processor power that must be dissipated for S.E.C.C.2 processors can be thought of just as it is for S-E.C.C. packaged processors: a combination of both the processor core and L2 cache. In regards to the core, thermal specifications depend on the packaging technology used. Pentium II processors in S.E.C.C.2 utilizing PLGA core packaging technology have a case temperature specified. Pentium II processors in S.E.C.C.2 utilizing OLGA core packaging technology have a junction temperature specified. Specifics on how to measure these two paramaters are outlined in AP-586, Pentium II Processor Thermal Design Guidelines (Order Number 243331). In addition, there are surface mounted SRAM components for the L2 Cache on the substrate that have a separate Tcasr specification in Table 28. Thermal Diode The Pentium II processor incorporates an on-die diode that must be used to monitor the die temperature (junction temperature). A thermal sensor located on the motherboard, or a stand-alone measurement kit, may monitor the die temperature of the Pentium II processor for thermal management or instrumentation purposes. Table 29 and Table 30 provide the diode parameter and interface specifications. Thermal Diode Parameters! Symbol Min Typ Max Unit Notes Lorward bias 5 500 uA 2 n_ideality 1.0000 1,0065 1.0173 3,4 NOTES: 1, Not 100% tested. Specified by design characterization. 2. Intel does not support or recommend operation of the thermal diode under reverse bias. 3, Atroom temperature with a forward bias of 630 mV. 4, n_ideality is the diode ideality factor parameter, as represented by the diode equation: T-Io(e (Vd*q)/(nkT) - 1). Thermal Diode Interface Pin Name SC 242 Connector Signal # Pin Description THERMDP Bl4 diode anode THERMDN B15 diode cathode S.E.C.C. and S.E.C.C.2 Mechanical Specifications 44 Pentium II processors use either S.E.C.C. or S.E.C.C.2 package technology. Both package types contain the processor core, L2 cache, and other passive components. The cartridges connect to the motherboard through an edge connector. Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a complete terminology listing. DatasheetPentium II Processor at 350 MHz, 400 MHz, and 450 MHz 46 Figure 19. Pentium I Processor (S.E.C.C. Package)Extended Thermal Plate Side Dimensions Figure 20. |}________. 3.805+.020 2.473+.016 Ri Hy | @ A io 9 2.070+.020 | 1.2354.020 1) @ ch - 4 2X 125.005 bo Ay 8 |G | | (7 (7 i 2X .342+.005 These dimensions are from the bottom of the substrate edge fingers 2X .365+.005 | i 1.745.005 w 1.8774.020 + T v005a Pentium I Processor (S.E.C.C. Package)Bottom View Dimensions az 5.255+.006 Cover + I | ~ T ; T as | oe ee ee Vere U u Thermal Plate _____ 2.181+4.015 oar _. 3.2434.015 > i< 5.341+.010 > it 5.505+.010 > y007 Datasheet56 Pentium II Processor at 350 MHz, 400 MHz, and 450 MHz Figure 35. Pentium I Processor Substrate (S.E.C.C.2 Package), Edge Finger Contact Dimensions OLGA Package Figure 36. E "a i i = : 5 n [ ce @ : ssT I 1 UO ee) O PIN AlZI . PIN Al | . q " To TH j SUBSTRATE ee DETAIL A IN NEXT FIGURE ; 2.835 1.850 mp re 2.49 008 2.10. 008 o. 100 Pentium II Processor Markings (S.E.C.C.2 Package) 2-D Matrix Mark See Note NOTE: Hologram Please refer to the Pentium IT Location Processor Specification Update foecerssor for this information. Datasheet| Pentium I Processor at 350 MHz, 400 MHz, and 450 MHz | ntl 8 6.2 6.2.1 Mechanical Specifications This section documents the mechanical specifications of the boxed Pentium II processor fan heatsinks. Motherboard manufacturers and system designers should take into account the spacial requirement for both the boxed Pentium II processor in the S.E.C.C. package and the boxed Pentium II processor in the S.E.C.C.2 package. Boxed Processor Fan Heatsink Dimensions The boxed processor is shipped with an attached fan heatsink. Clearance is required around the fan heatsink to ensure unimpeded air flow for proper cooling. The space requirements and dimensions for the boxed processor in the S.E.C.C. package are shown in Figure 39 (Side View), Figure 40 (Front View), and Figure 43 (Top View). Spacial requirements and dimensions for the boxed processor in the S.E.C.C.2 package are shown in Figure 41 (Side View), Figure 42 (Front View), and Figure 43 (Top View). All dimensions are in inches. Figure 39. Side View Space Requirements for the Boxed Processor with S.E.C.C. Packaging 66 Fan Heatsink 3.E.C.C. Processor Package A | / / J 2 f , 242-Contact Slot DatasheetPentium II Processor at 350 MHz, 400 MHz, and 450 MHz intel. Figure 40. Front View Space Requirements for the Boxed Processor with S.E.C.C. Packaging Power Cable D Connector S NS s] 7 Ges A oo oO c Ss / | NI Cc > C oO oO A E Figure 41. Side View Space Requirements for the Boxed Processor with $.E.C.C.2 Packaging _ Fan Heatsink $.E.C.C.2 Processor Package 242-Contact Slot Connector 67 DatasheetPentium I Processor at 350 MHz, 400 MHz, and 450 MHz | Nn Table 43. Input Signals Name Active Level Clock Signal Group Qualified A20M# Low Asynch CMOS Input Always! BPRI# Low BCLK AGTL+ Input Always BRI1# Low BCLK AGTL+ Input Always BCLK High Clock Always DEFER# Low BCLK AGTL+ Input Always FLUSH# Low Asynch CMOS Input Always! IGNNE# Low Asynch CMOS Input Always! INIT# Low Asynch CMOS Input Always! INTR High Asynch CMOS Input APIC disabled mode LINT[L:0] High Asynch CMOS Input APIC enabled mode NMI High Asynch CMOS Input APIC disabled mode PICCLK High APIC Clock Always PREQ# Low Asynch CMOS Input Always PWRGOOD High Asynch CMOS Input Always RESET# Low BCLK AGTL+ Input Always RS[2:0]# Low BCLK AGTL+ Input Always RSP# Low BCLK AGTL+ Input Always SLP# Low Asynch CMOS Input During Stop-Grant state SMI# Low Asynch CMOS Input STPCLK# Low Asynch CMOS Input TCK High JTAG Input TDI High TCK JTAG Input TESTHI High Asynch Power/Other Always TMS High TCK JTAG Input TRST# Low Asynch JTAG Input TRDY# Low BCLK AGTL+ Input NOTE: 1, Synchronous assertion with active TDRY# ensures synchronization, Datasheet