PIC16F1619-E/ML - Microchip Technology

 2014-2017 Microchip Technology Inc. DS80000629B-page 1

PIC16(L)F1615/1619

The PIC1 6(L)F161 5/1619 famil y devi ces th at you have

received conform functionally to the current Device

Data Sheet (DS40001770C), except for the anomalies

des c ribed in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata describ ed in this document will be addressed

in future revisions of the PIC16(L)F1615/1619 silicon.

Data S heet clarif ications and corrections start on page

6, following the discussion of silic on issues.

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate website

(www.microchip.com).

For example, to identify the silicon revision level

using MPLAB IDE in conjunction with a hardware

debugger:

1. Using the appropriate interface, connect the

device to the hardware debugg er.

2. Open an MPLAB IDE project.

3. Configure the MPLAB IDE project for the

appropriate device and hardware debugger.

4. Based on the version of MPLAB IDE you are

using, do one of the following:

a) For MPLAB IDE 8, select Programmer >

Reconnect.

b) For MPLAB X IDE, select Window >

Dashboard and click the Refresh Debug

Tool Status icon ( ).

5. Depending on the development tool used, the

part number and Device Revision ID value

appear in the Output window.

The DEVREV values for the various PIC16(L)F1615/

1619 silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A4).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number

DEVICE ID<13:0>(1,2)

DEV<8:0> Revision ID for Silicon Revision

PIC16F1615 307Ch 4h

PIC16LF1615 307Eh 4h

PIC16F1619 307Dh 4h

PIC16LF1619 307Fh 4h

Note 1: The Device ID is located in the configuration memory at address 8006h.

2: Refer to the “PIC12(L)F1612/16(L)F161X Memory Programming Specification” (DS40001 720) for det ailed

information on Device and Revision IDs for your specific device.

PIC16(L)F1615/1619 Family

Silicon Errata and Data Sheet Clarification

PIC16(L)F1615/1619

DS80000629B-page 2  2014-2017 Mic rochip Technology Inc.

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary

Affected

Revisions(1)

EUSART Transmit 1.1 Duplicate transm is sio n. X

Master

Synchronous

Serial Port

(MSSP)

SPI Slave Mode 2.1 Slave Select release during Sleep corrupts data. X

SPI Slave Mode 2.2 Receive data lost when Slave Select enable

occurs just before Sleep execution. X

SPI Slave Mode 2.3 WCOL improperly set during Sleep. X

Enhanced

Capture/Compare/

PWM (ECCP)

Compare Mode 3.1 Compare Toggle mode yields unexpected

results. X

Fixed Voltage

Reference (FVR) ADC Conv ersion 4.1 First conversion of FVR signal may contain

errors. X

Analog-to-Digital

Converter (ADC) Positive Voltage

Reference 5.1 Using the FVR as the ADC positive voltage

reference may cause missing codes. X

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

 2014-2017 Microchip Technology Inc. DS80000629B-page 3

PIC16(L)F1615/1619

Silicon Errata Issues

1. Module: EUSART

1.1 Dupl icate Transmissio n

Under certain conditions, a byte written to the

TXREG register can be transmitted twice. This

happens when a byte is written to TXREG just

as the TSR register becomes empty. This new

byte is immediately transferred to the TSR

until the completion of the current instruction

cycle. If the new byte in the TSR register is

transmitted before this instruction cycle has

completed, the duplicate in the TXREG register

will subsequently be transferred to the TSR

and transmitted.

Work around

1. Monitor the transmit interrupt flag bit (TXIF).

Wr ite s to the TXREG regis ter ca n be perfo rme d

once the TXIF bit is set, indicating that the

TXREG register is empty.

2. Monitor the TMRT bit of the TXSTA register.

Wr ite s to the TXREG regis ter ca n be perfo rme d

once the TMRT bit is set, indicating that the

Transmit Shift Register (TSR) is empty.

Affected Silicon Revisions

2. Module: Master Synchronous Serial Port

(MSSP)

2.1 Slave Select Release During Sleep Corrupts

Data

When the MSSP module is configured in SPI

Slave m ode with SS pi n c on trol ena ble d (SS P M

= 0100) and the device is in Slee p mode during

SPI activity, if the SPI master releases the SS

line (SS goes high) before the device wakes

from Sleep and updates SSPBUF, the received

data will be lost.

Work around

Method 1: The SPI master must wait a minimum

of parameter SP83 (1.5TCY + 40 ns) after the

last SCK edge AND the additional wake-up time

from Sleep (de vice depe ndent) bef ore releas ing

the SS line.

Meth od 2: If both the master and slave devices

have an available pin, once the slave has

completed the transaction and BF or SSPIF is

set, the slave could toggle an output to inform

the master that the transaction is complete and

that it is safe to release the SS line.

Affected Silicon Revisions

2.2 Receive Data Lost

When the MSSP module is configured in SPI

Slave mode with SS pin c ont rol ena ble d (SSPM

= 0100) and the device i s in Sleep mode durin g

SPI activity, if the SPI master enables SS (SS

goes low ) within 1 TCY before Sl eep is ex ecuted,

the data written into the SSPBUF by the slave

for transm ission will remain in the SSPBUF, and

the byte received by the sl ave will b e completel y

discarded. The MSb of the data byte that is

currently loaded into SSPBUF will be

transmitted on each of the eight SCK clocks,

resulting in either a 0x00 or 0xFF to be

incorrectly transmitted. This issue typically

occurs when the device wakes up from Sleep to

process data and immediately goes back to

Sleep during the next transmission.

Work around

The SPI slave must wait a minimum of 2.25 *

TCY from the time the SS line becomes active

(SS goes low) before executing the Sleep

command.

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A4).

PIC16(L)F1615/1619

DS80000629B-page 4  2014-2017 Mic rochip Technology Inc.

2.3 WCOL Improperly Set During Sleep

When the MSSP module is configured with

either of the Slave modes listed below and

Sleep is executed during transmission, the

WCOL bit is erroneously set. Although the

WCOL bit is set, it does not cause a break in

transmission or reception.

Mode 1: SPI slave mode with SS disabled

(SSPM = 0101) and CKE = 0.

Mode 2: SPI slave mode with SS enabled

(SSPM = 0100) and SS is not set and then

cleared before each consecutive transmission.

This typically occurs during multiple byte

transmissions in which the master does not

release the SS line until all transmission has

completed.

Work around

Meth od 1: The WCOL bit can be ignored since

the issue does not interfere with MSSP

hardware.

Method 2: Clear the SSPEN bit after each

transaction, then set SSPEN before the next

transmission.

Affected Silicon Revisions

3. Module: Enhanced Capture/Compare/

PWM (ECCP)

3.1 Compare Toggle Mode Yields Unexpected

Results

The ECCP Compare Toggle mode

(CCP1M<3:0> bits = 0010) works properly as

long as th e Tim er1 Prescaler value is confi gured

to 1:1. When the Timer1 prescaler value is

configured to any other value, the ECCP

Compare output yields unexpected results.

Work around

Only use the Compare Toggle mode when the

Timer1 Prescaler value is set to 1:1.

Affected Silicon Revisions

4. Module: Fixed Volt age Reference (FVR)

4.1 First Conversion of FVR Signal May Contain

Errors

When usi ng the ADC to sample the outp ut of the

FVR, the first conversion result may contain

errors. This can occur particularly if both the

FVR and ADC modules have been powered

down for sign ifica nt time p rior to the c onversio n.

Work around

Method 1:

Prior to the conversion, provide 'FVR

Stabilization Period' per the graph provided in

the Electrical Specification chapter of the data

sheet. As shown in this graph, this stabilization

time is typically in the range 25 to 30 us. During

this stabilization time, the ADC should be

enabled and set to sample the VREFL (VSS)

node. The following steps should be followed:

1. Enable ADC with sampl e path set to VREFL

(VSS);

2. Enable FVR with ADFVR bits set to zero;

3. Configure FVR gain to the desired level per

data sheet instructions;

4. Allow time for FVR stabilization. (Poll for

FVRRDY = 1);

5. Configure ADC sample path to FVR and

required AD C acqui si tion time allow ed ;

6. Initiate the ADC conversion.

Method 2:

Alternately, the FVR and ADC modules can be

enabled and a series of ADC conv ersio ns of the

sampled FVR output performed while both

modules remain active. In this case, the first

conversion result should be discarded and the

subsequent results utilized. It is noted that this

approac h, in ef fect, pro vides for the st abil izatio n

time referred to above.

Affected Silicon Revisions

 2014-2017 Microchip Technology Inc. DS80000629B-page 5

PIC16(L)F1615/1619

5. Module: Analog-to-Digital Converter

(ADC)

5.1 Using the FVR as the ADC Positive Voltage

Reference May Cause Missing Codes

Using the FVR as the pos itive vol tag e refer ence

for the ADC can cause an increase in missing

codes.

Work around

Increase the bit conversion time, known as T AD,

to 8 µs or higher.

Affected Silicon Revisions

PIC16(L)F1615/1619

DS80000629B-page 6  2014-2017 Mic rochip Technology Inc.

Data Sheet Clarifications

The foll owing ty pographic corrections and clar ification s

are to be note d fo r the latest versi on of the devi ce dat a

sheet (DS40001770C):

1. Module: eXtreme Low-Power (XLP)

Features

The line stating:

• Secondary Oscillator: 500 nA @ 32 kHz

should be removed. This device does not

have a seconda ry oscillator featu re.

2. Module: Electrical Characteristics

Parameters D080A and D090A should be as

follows:

3. Module: DC and AC Characteristics

Graphs and Charts

Figures 36-29 and 36-30 should be removed

from the docum en t.

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

Standard Operating Conditions (unless otherwise stated)

Param.

No. Sym. Characteristic Min. Typ† Max. Units Conditions

VOL Output Low Voltage(3)

D080A High Drive I/O(1) —2.5V—VIOL = 100 mA, VDD = 5.0V

VOH Output High Volt age(3)

D090A High Drive I/O(1) —2.5V—VIOL = 100 mA, VDD = 5.0V

 2014-2017 Microchip Technology Inc. DS80000629B-page 7

PIC16(L)F1615/1619

APPENDIX A: DOCUMENT

REVISION HISTORY

Rev A Document (12/2014)

Initial release of this document.

Rev B Document (09/2017)

Added modules 1-5 to Silicon Errata Issues.

Data Sheet Clarifications: Deleted modules 3-6 and

modules 8- 15.

Other minor corrections.

DS80000629B-page 8  2014-2017 Mic rochip Technology Inc.

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only for your c on ve nience

and may be supers eded by u pdates. It is y our res po ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

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OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microch ip name and logo, the Microchip logo, AnyRate, A V R,

A VR logo, AVR Freaks, BeaconThings, BitCloud, c hipKIT, chipKIT

logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,

Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK

MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST

logo, MPLAB, Opto Lyzer, PIC, picoPower, PICSTART, PIC32

logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,

SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are

registe r ed trademarks of Microchip Technology Incorporated in

the U.S. A. and other coun tries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are regist ered

trademarks of Microchip Technology Incorpora ted in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,

CryptoAuthentication, CryptoComp anion, CryptoContro ller,

dsPICDEM, ds PICDEM.net, Dynamic Average Matc hing, DAM,

ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-

Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,

MiWi, motorBenc h, MPASM, MPF, MPLAB Certified logo, MPL IB,

MPLINK, Mult iTRAK, NetDetach, Omniscient Code Generation,

PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,

RightTouch logo, REAL ICE, Ripple Bloc ker, SAM-ICE , Serial

Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher I I,

Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Silicon S tor age Technology is a regis tered tradema rk of Microchi p

Technology Inc. in other countries.

GestIC i s a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Reserved.

ISBN: 978-1-5224-2173-3

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of t he most secure famili es of its kind on the market t oday, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microch ip rece ived IS O/T S-16 94 9:20 09 certificat ion for i ts worldwid e

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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 2014-2017 Microchip Technology Inc. DS80000629B-page 9

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