Digitally Programmable Delay Units series: PDU-10256H (8-Bit) ECL Interfaced Specifications: Delay variation: Monotonic in one direction a Programmed delay tolerance: + 5% or 1 ns whichever is greater. = (Inherert delay (Too): 12 ns typ. Test Conditions @ input pulse-width: =150% of Max. delay. w Input pulse spacing: >3 times of Max. delay. gB Input pulse voltage: = Propayation delay: Address tc output (Tsua) . Enable to output (Tsue) m Low propagation delay @ Power dissipation: 925 mw typ. m= Input & output ECL buffered Supply voliage: 5 Vde - 5%. a a ECL logic. @ Measurements taken @ Ta= 25C, VEE= 5V. 3.6 ns typ. 1.7 ns typ. Features: a 8-BIT ECL programmable delay line Operating emperature: 0-70 C. a Output same polarity of input Temperature Coefficient: 100 PPM/ C. a Completely interfaced @ DC parmete-s: See ECL-10KH Logic Table or Page 6. w@ Compact & low profile a ADDRESS 7 I 2945 5 7 al 8 R T VV Yo YY YY 7 tre | 7200 ; { 7|42| aifts}salsatas/ asp [_---- ~~ 100 =; 4 Vu O28 2 ge ose | 4.500 1 { i ' I. | Ma 1.400 | IN 1) DELAY | 075 TYP 9 # 700 i 19.47 NETWORK 7 ++ 100 | anno 2248 _ Lyle out Tor lee Fee a9 G2 Ga | | 400 48 47 42 4) 40 a4 3a 42 25 L-~~- -~- 4 oo aga mec & : 2.450 { t or case stand-offs TRUTH TABLE oo Address (Bit No.) Incremental Delay Total Programmed 8 7 6 5 4 3 2 1 Enabe Delay Out Part No. Per Step (ns) Delay (ns) PDU-10256H-.5 5+ 3 127.5 0 0 0 0 0 0 0 0 0 To | PDU-10256H-1 1 + 56 255 Q 0 0 0 0 0 0 1 0 T, PDU-10256H-2 2 + 5 510 0 0 0 0 0 0 1 0 0 T, PDU-10256H-3 3 + 1.0 765 0 0 0 0 0 0 1 1 0 T, PDU-102564-4 4 +10 1,020 _ PDU-102364-5 5 =15 1,275 Oo; oO] O07 OJ OF 1] OF 0 a qT, PDU-10256-4-6 6 +15 1,530 O);o;/ 0); 0) o0];1] 1] 1 0 i, PDU-102564-7 7 +18 1,785 Oo; o;] a); 0/1) 0} O] 0 0 Ts PDU-102564-8 8 + 2.0 2,040 Oo; Oo; 0; 0; 1p rt ry 1 0 Tis PDU-10256 4-9 9 + 20 2,296 olololi ol o olo 0 T PDU-10256-4-10 10 + 2.0 2,550 6. oloflofalatra] 4] 0 Ts, O;ol;t]o;yoyo} ot] o 0 Ts2 O7;oO;rpyilyty 1] 4 0 Tes NOTE: 1. crthe sake of simplicity all 256 programmable steps 4 are not shown in this truth table. of 1 o;o;oyo] oo] 0 0 Toa 2. Affer Bit 6, the incremental delay tolerance is 5% of o , ; \ i i i ' Tier programmed delay. 12B 1 1 1 1 1 1 1 1 0 255 1a} oro; o}o)] of 0 1 0 0 = Logic 0 1= Logic 1 0 = Don't care. T, .- Reference or inherent delay of unit. T, __+T,,, multiplier of incremental delay 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 m@ (201) 773-2299 m FAX (201) 773-9672 55