16-Bit Latched Transceivers
SCCS059 - August 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered. CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
Copyright © 2000, Texas Instruments Incorporated
Features
FCT-E speed at 3.4 ns
Power-off disable outputs permits live insertion
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of 40˚C to +85˚C
•V
CC = 5V ± 10%
CY74FCT16543T Features:
64 mA sink current, 32 mA source current
Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
CY74FCT162543T Features:
Balanced 24 mA output drivers
Reduced system switching noise
Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
CY74FCT162H543T Features:
Bus hold retains last active state
Eliminates the need for external pull-up or pull-down
resistors
Functional Description
The CY74FCT16543T and CY74FCT162543T are 16-bit,
high-speed,lowpowerlatchedtransceiversthatareorganizedastwo
independent 8-bit D-type latched transceivers containing two sets of
eight D-type latches with separate Latch Enable (LEAB, LEAB) and
Output Enable (OEAB, OEAB) controls for each set to permit
independent control of inputting and outputting in either direction of
data flow. For data flow from A to B, for example, the A-to-B input
Enable(CEAB) mustbe LOWin orderto enter data fromAor to take
data from B as indicated in the truth table. With CAEB LOW, a LOW
signal on the A-to-B Latch Enable (LEAB) makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the LEAB
signal puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB both LOW,
thethree-stateBoutputbuffersareactiveandreflectthedatapresent
at the output of the A latches. Control of data from B to A is similar,
but uses CEAB, LEAB, and OEAB inputs flow-through pinout and
small shrink packaging and in simplifying board design. The output
buffers are designed with a power-off disable feature to allow live
insertion of boards.
The CY74FCT16543T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162543T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162543T is ideal for driving transmission lines.
TheCY74FCT162H543T is a 24-mAbalanced output partthat
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
2
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .....................Com’l 55°C to +125°C
Ambient Temperature with
Power Applied.................................Com’l 55°C to +125°C
DC Input Voltage .................................................0.5V to +7.0V
DC Output Voltage..............................................0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Logic Block Diagrams PinConfiguration
1OEAB
SSOP/TSSOP
Top View
GND
VCC
FCT16543T-1
FCT16543T-2
TO 7 OTHER CHANNELS
D
C
1B1
1OEBA
1A1
1CEBA
1LEAB
1OEAB
1LEBA
1CEAB
D
C
D
C
2B1
2OEBA
2A1
2CEBA
2OEAB
2LEBA
2CEAB
1LEAB
1CEAB
1A1
VCC
GND
2LEAB
1A2
1A3
1A5
1A4
1A6
1A7
1A8
GND
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
GND
2OEAB
2CEAB
2LEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
GND
VCC
1LEBA
1CEBA
1B1
VCC
GND
1B2
1B3
1B5
1B4
1B6
1B7
1B8
GND
2B1
2B2
2B3
2B4
2B6
2B7
2B8
GND
2OEBA
2CEBA
2LEBA
2B5
D
C
FCT16543T-3
TO 7 OTHER CHANNELS
Pin Description
Name Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A A-to-B Data Inputs or B-to-A Three-State Outputs[9]
B B-to-A Data Inputs or A-to-B Three-State Outputs[9]
Function Table[1]
Inputs Latch
Status Output
Buffers
CEAB LEAB OEAB A to B B
H X X Storing High Z
X H X Storing X
X X H X High Z
L L L Transparent Current A
Inputs
L H L Storing Previous A
Inputs[2]
Operating Range
Range Ambient
Temperature VCC
Industrial 40°C to +85°C 5V ± 10%
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
3
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresis[6] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=18 mA 0.7 1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LOW Current VCC=Max., VI=GND ±1µA
IOZH High Impedance Output Cur-
rent (Three-State Output pins) VCC=Max., VOUT=2.7V ±1µA
IOZL High Impedance Output Cur-
rent (Three-State Output pins) VCC=Max., VOUT=0.5V ±1µA
IOS Short Circuit Current[7] VCC=Max., VOUT=GND 80 140 200 mA
IOOutput Drive Current[7] VCC=Max., VOUT=2.5V 50 180 mA
IOFF Power-Off Disable VCC=0V, VOUT4.5V[8] ±1µA
Notes:
1. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.
2. Data prior to LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level. L = LOW Voltage Level.
X = Don’t Care. Z = High Impedance.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Tested at +25˚C.
9. On the 74FCT162H543T, these pins have bus hold.
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
4
Output Drive Characteristics for CY74FCT16543T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VOH Output HIGH Voltage VCC=Min., IOH=3 mA 2.5 3.5 V
VCC=Min., IOH=15 mA 2.4 3.5
VCC=Min., IOH=32 mA 2.0 3.0
VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V
Output Drive Characteristics for CY74FCT162543T, CY74FCT162H543T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
IODL Output LOW Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
VOH Output HIGH Voltage VCC=Min., IOH=24 mA 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V
Capacitance[6] (TA = +25˚C, f = 1.0 MHz)
Parameter Description Test Conditions Typ.[5] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.[5] Max. Unit
ICC QuiescentPowerSupplyCurrent VCC=Max. VIN0.2V,
VINVCC0.2V 5 500 µA
ICC QuiescentPowerSupplyCurrent
(TTL inputs HIGH) VCC=Max. VIN=3.4V[10] 0.5 1.5 mA
ICCD Dynamic Power Supply
Current[11] VCC=Max., One Input
Toggling, 50% Duty Cycle,
Outputs Open, OE=GND
VIN=VCC or
VIN=GND 60 100 µA/MHz
ICTotal Power Supply Current[12] VCC=Max., f1=10 MHz,
50% Duty Cycle, Outputs
Open, One Bit Toggling,
OE=GND
VIN=VCC or
VIN=GND 0.6 1.5 mA
VIN=3.4V or
VIN=GND 0.9 2.3 mA
VCC=Max., f1=2.5 MHz,
50% Duty Cycle, Outputs
Open, Sixteen Bits Toggling,
OE=GND
VIN=VCC or
VIN=GND 2.4 4.5[13] mA
VIN=3.4V or
VIN=GND 6.4 16.5[13] mA
Notes:
10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
ICC = Power Supply Current for a TTL HIGH input
(VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair
(HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
5
Switching Characteristics Over the Operating Range[14]
CY74FCT16543T
CY74FCT162543T CY74FCT16543AT
CY74FCT162543AT Fig.
No.[15]
Parameter Description Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay
Transparent Mode
A to B or B to A
1.5 8.5 1.5 6.5 ns 1, 3
tPLH
tPHL Propagation Delay
LEBA to A, LEAB to B 1.5 12.5 1.5 8.0 ns 1, 5
tPZH
tPZL Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
1.5 12.0 1.5 9.0 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
1.5 9.0 1.5 7.5 ns 1, 7, 8
tSU Set-up Time HIGH or LOW
A or B to LEAB or LEBA 2.0 2.0 ns 4
tHHold Time HIGH or LOW
A or B to LEAB or LEBA 2.0 2.0 ns 4
tWLEBA or LEAB Pulse Width LOW 4.0 4.0 ns 5
tSK(O) Output Skew[16] 0.5 0.5 ns
CY74FCT16543CT
CY74FCT162543CT
CY74FCT162H543CT CY74FCT16543ET
CY74FCT162543ET Fig.
No.[15]
Parameter Description Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay
Transparent Mode
A to B or B to A
1.5 5.1 1.5 3.4 ns 1, 3
tPLH
tPHL Propagation Delay
LEBA to A, LEAB to B 1.5 5.6 1.5 3.7 ns 1, 5
tPZH
tPZL Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
1.5 7.8 1.5 4.8 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
1.5 6.5 1.5 4.0 ns 1, 7, 8
tSU Set-up Time HIGH or LOW
A or B to LEAB or LEBA 2.0 1.0 ns 4
tHHold Time HIGH or LOW
A or B to LEAB or LEBA 2.0 1.0 ns 4
tWLEBA or LEAB Pulse Width LOW 4.0 3.0 ns 5
tSK(O) Output Skew[16] 0.5 0.5 ns
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. See “Parameter Measurement Information” in the General Information section.
16. Skew between any two outputs of the same package switching in the same directional. This parameter is ensured by design.
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
6
Ordering Information CY74FCT162H543T
Ordering Information CY74FCT16543
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
3.4 CY74FCT16543ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT16543ETPVC/PVCT O56 56-Lead (300-Mil) SSOP
5.1 CY74FCT16543CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial
6.5 CY74FCT16543ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial
8.5 CY74FCT16543TPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial
Ordering Information CY74FCT162543
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
3.4 74FCT162543ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162543ETPVC O56 56-Lead (300-Mil) SSOP
74FCT162543ETPVCT O56 56-Lead (300-Mil) SSOP
5.1 74FCT162543CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162543CTPVC O56 56-Lead (300-Mil) SSOP
74FCT162543CTPVCT O56 56-Lead (300-Mil) SSOP
6.5 74FCT162543ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial
8.5 CY74FCT162543TPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
5.1 74FCT162H543CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
7
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
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