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©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
HUF75332P3
N-Channel UltraFET Power MOSFET
55 V, 60 A, 19 mΩ
These N-Channel power MOSFETs are manufactured
using the innovative UltraFET process. This advanced
process technology achieves the lowest possible on-
resistance per silicon area, resulting in outstanding
performance. This device is capable of withstanding high
energy in the avalanche mode and the diode exhibits very
low reverse recovery time and stored charge. It was
designed for use in applications where power efficiency is
important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery-
operated products.
Formerly developmental type TA75332.
Features
• 60A, 55V
• Simulation Models
- Temp era ture Com pen sated PSPI CE® a nd SABER™
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Packaging
Product r e liability inform a tion can be found at http ://www.fairchildsemi.com/p r oducts/discre te/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchi ld semiconduct or products are manufactured, assembled and t ested under ISO9000 and QS9000 quality systems certificat ion.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75332P3 TO-220AB 75332P
D
G
S
JEDEC TO-220AB
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
Data Sheet October 2013
Symbol
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . V DSS 55 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR 55 V
Gate to Sou rc e Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Dr a i n Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 60
Figure 4 A
Pulsed Aval a n che Ra tin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figure 6
Powe r Dis sipati o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
0.97 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . .TL
P ackage Body for 10s , See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Str esses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess onl y rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V
Zero Gate Voltage Drain Current IDSS VDS = 50V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 150oC--250µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STAT E SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resistance rDS(ON) ID = 60A , VGS = 10V (Figure 9) - 0.016 0.019 Ω
THERMAL SPEC I F IC A T I ONS
Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.03 oC/W
Thermal Resistance Junction to Ambient RθJA TO-220 - - 62 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID ≅ 60A,
RL = 0.50Ω, V GS = 10V,
RGS = 6.8Ω
--130ns
Turn-On Delay Time td(ON) -9-ns
Rise Time tr-90- ns
Turn-Off Delay Time td(OFF) -50- ns
Fall Ti me tf-45- ns
Turn-Off Time tOFF --125ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,
ID ≅ 60A,
RL = 0.50Ω
Ig(REF) = 1.0mA
(Figure 13)
-7085nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 40 50 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 2.5 3.0 nC
Gate to Source Gate Charge Qgs -6-nC
Reverse Transfer Capacitance Qgd -15-nC
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1M H z
(Figure 12)
- 1300 - pF
Output Capacitance COSS - 480 - pF
Reverse Transfer Capacitance CRSS - 115 - pF
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Sour ce to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNI TS
Source to Drain Diode Voltage VSD ISD = 60A - - 1.25 V
Reverse Recovery Time trr ISD = 60A, dISD/ dt = 100A/µs--75ns
Reverse Recovered Charge QRR ISD = 60A, dISD/dt = 100A/µs - - 140 nC
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPA TI ON vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 175
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
20
40
60
80
50 75 100 125 150 175
025
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
10-4 10-3 10-2 10-1 100101
10-5
0.1
1
2
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Fairchild Applicat ion Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS
Typical Performance Curves (Continued)
101
100
10-1
10-2
10-3
10-4
10-5
50
100
1000 TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
100
500
10 100
11200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
C
= 25
o
C
100
µ
s
10ms
1ms
V
DSS(MAX)
= 55V
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
STARTING TJ = 25oC
10
100
0.001 0.01 0.1 1 10
500
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[ (IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
30
60
90
120
150
0 1.5 3.0 4.5 6.0 7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
TC = 25oC
ID, DRAIN CURRENT (A)
VGS = 5V
VGS = 6V
VGS = 10V
VGS = 7V
VGS = 20V
DUTY CYCLE = 0.5% MAX
0
30
60
90
120
150
0 1.5 3.0 4.5 6.0 7.5
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 15V
175oC
-55oC
25oC
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
FIGURE 9. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATU RE
FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAG E
NOT E: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves (Continued)
1.0
1.5
2.0
2.5
-40 0 40 80 120 160 200
0.5-80
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 80µs
VGS = 10V, ID = 60A
DUTY CYCLE = 0.5% MAX
0.8
1.0
1.2
-40 0 40 80 120 160 200
0.6-80
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VO LTAG E
VGS = VDS, ID = 250µA
1.0
1.1
1.2
-40 0 40 80 120 160 200
0.9-80
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
0
500
1000
1500
2000
0 102030405060
VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS
COSS
CRSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
2
4
6
8
10
10 20 30 40 50 600
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
Qg, GATE CHARGE (nC)
ID = 60A
ID = 45A
ID = 30A
ID = 15A
WAVE F ORMS IN
DESCENDING ORDER:
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY W AVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PE AK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
PSPICE Elec trical Model
.SUBCKT HUF75332 2 1 3 ; rev 17 February 1999
CA 12 8 1.8e-9
CB 15 14 1.73e-9
CIN 6 8 1.19e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 58.85
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEM P 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1e - 9
LGATE 1 9 1e-9
LSOURCE 3 7 1e-9
K1 LSOURCE LGA TE 0.0085
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 4.5e-3
RGATE 9 20 1.3
RLDRAIN 2 5 10
RLGATE 1 9 10
RLSOURCE 3 7 10
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.95e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AM OD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VA LUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),4.6))}
.MODEL DBODYMOD D (IS = 1.3e -12 R S = 3.0e-3 IKF = 20 XTI = 6 TRS 1 = 2.7e-3 TRS2 = 7.0e-7 CJO = 1.7e-9 TT = 4.0e-8 M = 0.45 vj = 0.75)
.MODEL DBREAKMOD D (RS = 1.71e-2 I KF = 1.0e-5 TRS1 = -4.0e- 4 T RS2 = -1.55e-5)
.MODEL DPLCAPMOD D (CJO = 1.8e-9 IS = 1e-30 N = 1 M = 0.9 vj = 1.45)
.MODEL MMEDMOD NMOS (VTO = 3.18 3 KP = 2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1. 3)
.MODEL MSTROMOD NMOS (VTO = 3.66 KP = 51.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.703 KP = 0.008 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 13)
.MODEL RBREAKMOD RE S (TC1 = 1.0 5e-3 TC2 = 4.5e-7)
.MODEL RDRAINMOD RES (TC1 = 1. 16e-2 TC2 = 1.7e-5)
.MODEL RSLCMOD RES (TC1 = 3.96e-3 TC2 = 2.7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -1.0e-5)
.MODEL RVTE MPMOD RES (TC1 = -2.75e-3 TC2 = 5.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8 VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= 0)
.ENDS
NOT E: For fur th er discussion of the PSPICE m odel, consult A Ne w PSPICE Sub-Circuit for the Power MOSFET Featuring Gl oba l
Temperature Options; IEEE P ower Electronics Specialist Conference Records, 1991, written b y William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
SABER Electrical Model
REV 17 Feb ruary 1999
template huf75332 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 1. 3e-12, xti = 6, cjo = 1.7e-9, tt = 4.0e-8, m = 0.45, vj = 0.75)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.8e-9, is = 1e-30, m = 0.9, vj = 1.45)
m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1)
m..model mweakmod = (type =_n, vto = 2.703, kp = 8.0e-3, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8, voff = -3)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -8)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0)
c.ca n12 n8 = 1.8e-9
c.cb n15 n14 = 1.73e-9
c.ci n n6 n8 = 1.19e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplc ap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 1.0e-9
l.lsou rce n3 n7 = 1.0e-9
k.kl i (l.lgate) i (l.lsource) = l (l.lgate), l (l.lsource), 0.0085
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstr ong n16 n6 n8 n8 = model= mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mwea kmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 4.5e-7
res.rdbody n71 n5 = 3.0e-3, tc1 = 2.7e-3, tc2 = 7.0e-7
res.rdbreak n72 n5 = 1.71e-2, tc1 = -4.0e-4, tc2 = -1.55e-5
res.rdrain n50 n16 = 4.5e-3, tc1 = 1.16e-2 , tc2 = 1. 7e-5
res.rgate n9 n20 = 1.3
res.rldrain n2 n5 = 10
res.r l gate n1 n9 = 10
res.rlsource n3 n7 = 10
res.rsl c1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6
res.rsl c2 n5 n50 = 1e3
res.rsourc e n8 n7 = 5.95e-3, tc1 = 1e -3, tc2 = 1e-5
res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 5.0e-7
res.rvthres n22 n8 = 1, tc1 = - 2.8e-3, tc2 = -1.0e-5
spe.e break n11 n7 n17 n18 = 58.85
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n1 9 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equa tions {
i (n51- >n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4.6) )
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
SPICE Thermal Model
REV 11February 1999
HUF75332
CTHERM1 th 6 4.00e-3
CTHERM2 6 5 7.00e-3
CTHERM3 5 4 7.50e-3
CTHERM4 4 3 8.00e-3
CTHERM5 3 2 1.85e-2
CTHERM6 2 tl 12.55
RTHERM1 th 6 7.09e-3
RTHERM2 6 5 1.77e-2
RTHERM3 5 4 4.97e-2
RTHERM4 4 3 2.79e-1
RTHERM5 3 2 4.21e-1
RTHERM6 2 tl 5.58e-2
SABER Thermal Model
SABER thermal mode l HUF75332
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.00e-3
ctherm.ctherm2 6 5 = 7.00e-3
ctherm.ctherm3 5 4 = 7.50e-3
ctherm.ctherm4 4 3 = 8.00e-3
ctherm.ctherm5 3 2 = 1.85e-2
ctherm.ctherm 6 2 tl = 12.55
rtherm.rtherm1 th 6 = 7.09e-3
rtherm.rtherm2 6 5 = 1.77e-2
rtherm.rtherm3 5 4 = 4.97e-2
rtherm.rtherm4 4 3 = 2.79e-1
rtherm.rtherm5 3 2 = 4.21e-1
rtherm.rtherm6 2 tl = 5.58e-2
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF75332P3
©2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0
HUF75332P3
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